Sophie BARON, PH-ESS LEADE, 15/06/06 1

TTC upgrade Status May 2006

Overview AB/RF optical links Receiver crate Status and schedules Documentation

Sophie BARON, PH-ESS LEADE, 15/06/06 2

Overview AB/RF optical links Receiver crate Status and schedules Documentation

Sophie BARON, PH-ESS LEADE, 15/06/06 3

OVERVIEW

TTClab (build 4)

AB/RF Tx and Rx modules

TTC Receiver Crates

Optical fibres

Sophie BARON, PH-ESS LEADE, 15/06/06 4

Overview AB/RF optical links Receiver crate Status and schedules Documentation

Sophie BARON, PH-ESS LEADE, 15/06/06 5

AB/RF OPTICAL LINKS [Analog solution]

Analog Modules o Transmitter module: RF_Tx_A (EDA-01331)o Receiver module: RF_Rx_A (EDA-01332)

6U 4TE VME (VME 64x and VME 64 compatible)o 3 internal registers

• Power warning led threshold (RW)

• CH/2 1Power monitoring (Read Only)

Miteq links 3GHzo validated - Specs:

• Measured Phase Noise:– 400MHz -> 0.4ps (pkpk)– 40MHz -> 0.4ps (pkpk)– 10MHz -> 13ps (pkpk)

More results in the evaluation report

• Typical output levels:– Bunch Clock = 0dBm continuous sinewave– Orbit = 1Vpk pulse on 50 Ohms

• Quantities:– 10 links have been ordered in November05– 10 to be ordered soon

=> Enough to work until 2007

Sophie BARON, PH-ESS LEADE, 15/06/06 6

AB/RF OPTICAL LINKS [Analog solution]

3200 € 3200 €2000 € 2000 €

150 € 150 €

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RECEIVER CRATE [Digital Solution]

We tried to find a cheaper solution with the same form factor Digital Modules (RF_Tx_D and RF_Rx_D)

o First test boards made with PHOTON 155Mbps/TRR-1B43 pair• Standard modules of the TTC modules• Performance evaluated on the same setup than the analog links• Results available in the test report• AB/RF agreed that this could be a cheaper solution for 70% of the links, including

the TTC• If the final results are as good as expected, they will use this solution for these 70%

and maintain the boards the same way.

o Optical components identified and ordered• Photon getting obsolete• OCP components pin compatible components• Price:

– Orbit, 10MHz, 40MHz: 156Mbps links

– 400MHz: 1.2Gbps

o Design on-going (PH/ESS). • Close to the analog boards, but higher density.

Tx Rx

156Mbps PHOTON 197 97

156Mbps AMS 313 227

1.2Gbps AMS 635 295

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Overview AB/RF optical links Receiver crate Status and schedules Documentation

Sophie BARON, PH-ESS LEADE, 15/06/06 9

RECEIVER CRATE [Overview]

o 6U VME crate:o VME Crate controllero AB/RF receiver VME moduleso RF2TTC VME module

• Receives timing signals from the AB/RF modules and machine states from the BST optical link

o BC and Orbit fanout

Sophie BARON, PH-ESS LEADE, 15/06/06 10

RECEIVER CRATE [Crates – Power Supplies - Controllers]

Provided by PH/ESS Common Crates:

o 1 LHC standard 6U VME 64x crate per experimento Available

(less) Common Power supplies: o (+3.3V/100A, +5V/100A, +-12V/10A, 48V/12A)o ATLAS, CMS, LHCb: OP06.0710o ALICE: OP17.0701

(no) Common Controllers:o ALICE: Standard VP315/317 from CCTo ATLAS, TTC lab: Standard VP110 from CCTo CMS: CAEN PCI-controller card A2818 + V2718 VME-PCI optical

bridgeo LHCb:CAEN V1718 VME-USB bridgeo POOL items. One of each will be reserved as from August 06.

Sophie BARON, PH-ESS LEADE, 15/06/06 11

RECEIVER CRATE [TTC Clock fanout]

TTC Clock fanout (EDA-01240-V1, PH/MIC) o Dual 1:18 ECL fanouto 4 NIM outputs per input (ALICE requirement)o 1 status led per input (presence of clock). o Maximum densityo The 2 dual modules can be daisy chained.o Fully AC coupled

Prototype produced and debugged

Power: 5V-5A, Jitter: In/Out skew=8ps rms, Cy2Cy=11ps rms Skew between outputs: a few ps

Production will begin after full validation & design modifications

Sophie BARON, PH-ESS LEADE, 15/06/06 12

BC ring1

BC ring2

BC REF

BC INPUTS

Orb ring1

Orb ring2

ORBIT INPUTS

BC OUTPUTS

ORBIT OUTPUTS

BC1/ecl BC1/nim

BC2/ecl BC2/nim

BC/ecl BC/nim

Or1/ecl Or1/nim

Or2/ecl Or2/nim

VMEBC1 lockBC2 lockBCref lockOrbit1Orbit2

Or2/ecl Or2/nim

BC/ecl BC/nim

MAIN

MAIN

RF2TTC

1 2 Ref IntBC

BST

Orb

LHC Mode

RECEIVER CRATE [RF2TTC overview]

VME64x - 6U – 4TE module Inputs

o 3 BC inputs (BC1, BC2, BCref) (RF signals)o 2 Orbit inputs (Orb1, Orb2) (RF signals)o 1 Optical input for the BST signals

Outputs o 4 ECL BC outputs (BC1, BC2, BCref, MainBC)

• AC coupled

• 4 NIM copies

o 3 NECL Orbit outputs (Orb1, Orb2, MainOrb)• DC coupled

• Synchronised respectively to BC1, BC2, MainBC

• 3 NIM copies

Status leds

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RECEIVER CRATE [RF2TTC functionalities]

Adjustable parameters (via VME registers)o BC1, BC2, BCref, MainBC

• Adjustable level on the comparator input (BC1, BC2 and BCref)• Multiplexing between each input and the internal 40.078MHz clock• Adjustable phase shift (steps of 0.5ns)

o Orbit1, Orbit2, Main Orbit• Adjustable level on the comparator input to match various types of signals (Orb1

and 2)• Adjustable phase shift before the latching with the corresponding BC (Orb1 and 2)• Multiplexing between each input and an internal counter• Adjustable length, coarse delay (steps of 25ns), phase shift (steps of 0.5ns) before

the output Status control

o Status registers (locking BC, BST ready, machine modes, Orbit alignment)o Leds

Manual or automatic mode to switch between the internal clock (orbit) and one of the machine clock (orbit)

timeinjection~15 min

ramping~28 min

squeeze~15 min

physics~10-20 H

Beam Dump

E(45

0GeV

->

7TeV

)

Beam Dump

E(45

0GeV

->

7TeV

)

Sophie BARON, PH-ESS LEADE, 15/06/06 14

text

text

FPGA

MAIN BC CLOCK

BC2 CLOCK

BC1 CLOCK

text

VME BACKPLANE

FROM RF OPTICALRECEIVERS

INTERNAL CLOCK

Sine2Square

PhaseAdjust

Sine2Square

Sine2Square

PLL&VCXO

PLL&VCXO

ECL Driver

Sine2Square

Sine2Square

Stretcher

Stretcher

FineDelay

FineDelay

PLL&VCXO

BC1

BC2

BC ref

PECL2NIM

PLL&VCXO

PhaseAdjust

PhaseAdjust

PhaseAdjust

ORBIT1

ORBIT2

VME BUS

MUX2:1

MUX2:1

MUX2:1

FAN1:4

FAN1:4

INTERNALCNT

ECL Driver

ECL2NIM

CoarseDelay

MAIN BC

I2C interface

BC1 ECL/OUT

BC1 NIM/OUT

BC2 ECL/OUT

BC2 NIM/OUT

BCrefECL/OUT

BCrefNIM/OUT

MAIN BCECL/OUT

MAIN BCNIM/OUT

ORBIT1NECL/OUT

ORBIT1NIM/OUT

ORBIT2NECL/OUT

ORBIT2NIM/OUT

MAIN ORBITNECL/OUT

MAIN ORBITNIM/OUT

Sine pulse1V peak (0-1V)

5ns width

Sinusoidal frequencies40.07XX MHz

varying0.6V pk-pk /8

or 0.6V pk-pk (CMS)

Sinusoidal frequency40.07XX MHz

fixed0.6V pk-pk / 8

or 0.6V pk-pk (CMS)

5nssquarepulse

40 ns LVPECL

ECLcomparator

AD96685

DELAY25

QPLL

BC & ORBIT SOURCESSELECTION, DACsadjustment for Orbit

comparators

BST decoder

VME INTERFACE

BSTSIGNAL

OPTICALTTC

FRAMES

MACHINE MODES

RE

MO

TE

CO

NT

RO

L

S1

S4

D

C2C1 ENB

Multiplexer

MACHINE MODES

FIN

E D

EL

AY

S C

ON

TR

OL

MAIN BC

INTERNALCLOCK

INTERNALCLOCK

TTCrx

BC1 lock

BC2 lock

BCref lock

MAIN BC lock

BCsel[1..0]

BOARD STATUS

Lock, TTCready, ...

Orbit sel

Orbit sel

BC1 lockBC2 lock

BCref lockMAIN BC lock

Orbit1Orbit2

Machine Mode Run/No

VME accessVME_Berr

BST_ready

MAIN BC int/BC1BC2/Bcref

MAIN ORBIT Or1/Or2/Int

STATUS REGISTERS

BC1sel

BC2sel

BCref sel

I2C

Orbitdetect

Orbitdetect

Orb2 det

MAIN BCsel[1..0]

RF2TTC BOARDBLOCK DIAGRAM V1.7

28/04/2006

LVPECL2LVDS

LVPECL2LVDS

LVPECL2LVDS

LVDS2ECL

LVDS2ECL

LVDS2ECL

DELAY25

DELAY25

DELAY25

QPLLMUX4:1

LVPECL2LVDS

Adjust.Stretch

er

2.5VCMOS

2.5VCMOS

2.5VCMOS

2.5VCMOS

DiffNECL

LVDS

LVDS

LVDS

LVDS

Orb1 det

Step 500ps, range 25ns

LVPECL QUARTZ80.158MHz

DiffNECL

DiffNECL

ACCOUPLING

ACCOUPLING

ACCOUPLING

Diff LVPECL

Diff LVPECL

Diff LVPECL

Diff LVPECL

ACCOUPLING

Diff LVPECL

CAPACITIVECOUPLING +THEVENIN

TERMINATION FORDC LEVEL OF 1.2V

Diff LVPECL

Diff LVPECL

Diff LVPECL

Diff LVPECL

LVDS800mV swing

LVDS800mV swing

LVDS800mV swing

LVDS800mV swing

LVDS

LVDS

LVDS

LVDS

MC10EP89 ECLcoax cable

drivers

ECL2NIMCONVERSION

USING BSR17ATRANSISTORS

74AHC123

PECL

PECL

PECL

PECL

DACs& Ref

Voltage

V_comp5

5nssquarepulse

40 ns LVPECL

ECL2NIMCONVERSION

USING BSR17ATRANSISTORS

v

Q

QSET

CLR

D

Sync

Q

QSET

CLR

D

Sync

FineDelay

FineDelay

FineDelay

S1

S4

D

C2C1 ENB

Multiplexer

CoarseDelay

Adjust.Stretch

er

S1

S4

D

C2C1 ENB

Multiplexer

Q

QSET

CLR

D

Sync

INTERNALCNT

Q

QSET

CLR

D

Sync

INTERNALCNT

CoarseDelay

Adjust.Stretch

er

PLL&VCXO

ECLcomparator

AD96685

V_comp3

V_comp1

V_comp4

V_comp2

FAN1:4

LVDS2ECL

BC1_CLOCK

FAN1:4

LVDS2ECL

BC2_CLOCK

FAN1:4

LVDS2ECL

BCref_CLOCK

MC10EP89 ECLcoax cable

driversBC1_clock

BC2_clock

LVDS2ECL

NECL

ECL Driver

PECL2NIM

ECL Driver

PECL2NIM

ECL Driver

PECL2NIM

ECL Driver

ECL2NIM

ECL Driver

ECL2NIM

RECEIVER CRATE [RF2TTC block diagram]

Adjustable

Reset possible

Monitored via a VME register

Status Led

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Overview AB/RF optical links Receiver crate Status and schedules Documentation

Sophie BARON, PH-ESS LEADE, 15/06/06 16

STATUS & Schedules

Mo

du

les

Sp

ecs

Co

mp

on

ent ch

oice

Sch

ematics

Review

layou

t

Firm

ware

So

ftware

Co

mp

on

ents

ord

ering

Pro

totyp

e

Valid

ation

Pro

du

ction

AB

/RF

m

od

ules

Analog Tx and Rx

NOW NOWJUNE-SEPT

(test beam)

Oct

Digital Tx and Rx

NOW NOW

Receiver

Crate

Crate

AUG-SEPT

(test beam)

Power Supply

Controller

Fanout July

RF2TTC NOW

3Weeks

NOW

2Months

NOW

2Months

NOW

6 Weeks

Mid JULY

Oct

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Overview AB/RF optical links Receiver crate Status and schedules Documentation

Sophie BARON, PH-ESS LEADE, 15/06/06 18

DOCUMENTATION

TTC upgrade proposal on EDMShttps://edms.cern.ch/cedar/plsql/doc.info?cookie=5173380&document_id=628545&version=2&p_tab=TAB6

TTC upgrade sitehttp://ttc-upgrade.web.cern.ch/ttc-upgrade/Default.htm

RF2TTC Review on INDICO/Projects/TTChttp://indico.cern.ch/categoryDisplay.py?categId=1099