tunnel barrier engineering for flash … · engineered tunnel barriers based on the simulation...
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TUNNEL BARRIER ENGINEERING FOR FLASH MEMORY TECHNOLOGY
A DISSERTATION
SUBMITTED TO THE DEPARTMENT OF MATERIALS SCIENCE AND
ENGINEERING
AND THE COMMITTEE ON GRADUATE STUDIES
OF STANFORD UNIVERSITY
IN PARTIAL FULLFILLMENT OF THE REQUIREMENTS
FOR THE DEGREE OF
DOCTOR OF PHILIOSOPHY
Sarves Verma
May 2010
http://creativecommons.org/licenses/by-nc/3.0/us/
This dissertation is online at: http://purl.stanford.edu/ds551wt1033
© 2010 by Sarves Verma. All Rights Reserved.
Re-distributed by Stanford University under license with the author.
This work is licensed under a Creative Commons Attribution-Noncommercial 3.0 United States License.
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I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.
Krishna Saraswat, Primary Adviser
I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.
Paul McIntyre, Co-Adviser
I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.
Yi Cui
Approved for the Stanford University Committee on Graduate Studies.
Patricia J. Gumport, Vice Provost Graduate Education
This signature page was generated electronically upon submission of this dissertation in electronic format. An original signed hard copy of the signature page is on file inUniversity Archives.
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ABSTRACT
The conventional Flash memory faces two critical obstacles in the future: density and
voltage scaling. Density is associated with scaling the gate length. The gate length cannot
be reduced beyond a point because it requires a commensurate gate stack, specifically,
tunnel oxide scaling for maintaining good gate control and short channel effects.
However, the gate-tunnel oxide (TO) reduction has a practical lower bound of ~ 7-9nm
(depending upon NAND or NOR flash architecture) due to leakage and data retention
constraints. Below this TO thickness, irrespective of how inter-poly dielectric (referred as
ONO) is scaled, the electric field across it during charge retention increases, leading to
unacceptable levels of tunneling current. The second major challenge with scaling is to
reduce the programming and erase operation voltages. The usual operation voltages for
these processes are much greater (15-18 Volts). With scaling, it is imperative for
operating voltages to reduce. Typically, read voltages are low, while erase and program
operations stress the charge pump requirements and dictate the maximum voltages. The
major impediment in erase voltage scaling is, once again, the inability to scale the gate
oxide. Recently, engineered tunnel barriers were proposed as solutions to scaling gate
oxide. It is postulated that engineered barriers offer faster program/erase yet maintain
excellent retention. However, a detailed characterization of engineered tunnel dielectrics
and a deeper understanding of the erase/program mechanism are sought to establish its
implementation.
In the first half of the thesis, we perform simulations to establish the feasibility of tunnel
barriers under Flash memory device constraints. We look at different higher-k materials
as a replacement for SiO2 and perform global optimization over different materials. This
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is first done under absence of traps in these materials. Later the assumptions are relaxed
and traps are incorporated in these materials. In the second part, we implement
engineered tunnel barriers based on the simulation results. However, it is observed that
presence of traps in these materials degrades performance. Retention loss and endurance
degradation are identified as two major problems, hindering implementation and scaling.
In the third and final part, we discuss solutions to these problems. Fluorine is well known
as a passivating agent for traps in high-k dielectrics. We incorporate fluorine in
engineered tunnel stacks and show electrical & physical characterization results to
emphasize its advantages. Finally, alternative tunnel barrier structures and materials are
discussed to continue scaling of gate dielectrics.
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ACKNOWLEDGEMENTS
My thesis would not be complete without thanking so many people I met during
my research at Stanford. This section may be the shortest but the most important part of
my thesis.
First of all, I would like to thank my advisor, Professor Krishna Saraswat for his
support and guidance throughout the course of my research. I appreciate the freedom he
provided and his encouragement which gave me the positive energy I needed for my
research. He is always an inspiration for me. I have learnt a lot from his vast knowledge
and experience. I feel extremely fortunate to work with the finest advisor that one could
possibly hope for.
I am also grateful to my co-advisor, Professor Paul McIntyre for being an
inspirational professor at Stanford and also for serving as a reader on my thesis
committee. I enjoyed all the interaction with him and his research group, especially
during his group meetings. I thank him for the insightful discussions and the useful
feedback he gave about my research.
I thank Professor Yi Cui for taking out time from his busy schedule to read my
dissertation. I would also like to thank Professor Jim Primbs for being the chair of my
defense committee. I am grateful to Professor Yoshio Nishi for being a part of my
defense committee and for providing me invaluable suggestions during our discussions.
A large portion of my experimental research was done at SEMATECH. My Ph.D
would be incomplete without thanking the people at SEMATECH. Working with them
was very fruitful and enjoyable. I am especially grateful to Dr. David Gilmer, Dr.
Gennadi Bersuker and Dr. Paul Kirsch. Their overwhelming support and help made my
experiments easy to be implemented. I am also thankful to Dr. Niti Goel, Dr. Pat Lysaght,
Dr. Prashant Majhi and Dr. Jimmy Price for useful discussions.
During my Ph.D., I was very fortunate to interact and collaborate with some great
intellectuals. Initially, I was introduced to this topic by Dr. Pawan Kapur and Dr. Eric
Pop. I worked closely with both of them and learnt a lot from them. I thank them for their
initial guidance and encouragement. Later, I was in touch with Dr. Krishna Parat (from
Intel Corp.) and Dr. Tejas Krishnamohan (from Intel Corp.). Their guidance was crucial
to my understanding of the subject. I thank them for their constant help and insightful
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discussions. I am also thankful to Dr. Luca Larcher and Dr. Andrea Padovani from the
University of Modena and Regio Emilia. A part of my simulations were done in
collaboration with them. I thank Dr. Andrea for his insightful discussions during the
course of our collaboration.
I also express my thanks to Irene Sweeney and Gail Chun-Creech for the efficient
administrative support. They were always available whenever I needed their help.
I would like to acknowledge Applied Materials Fellowship, SEMATECH
research grant, NMTRI and Intel grant for their financial support during my Ph.D.
I would also like to thank all my friends and colleagues in the Center of Integrated
Systems including Abhijit, Ali, Aneesh, Arunanshu, Crystal, Donghyun, Duygu, Eunji,
Gaurav, Gunhan, Jungyup, Hoon Cho, Hyun-Yong, Jason, Jin-Hong, Keya, Kyung Hoae,
Mihir, Raja, Scott, Shyam, Suyog, Woo-shik and Yeul. Special thanks to Duygu (abla)
for being so nice to me. We really had a good time in office and I cherish those moments.
I am also thankful to many friends from materials science with whom I spent my
initial years. Special thanks to Andy, Piyush, Shankar and Stefan.
There are no words in the dictionary to express my deepest gratitude to my
parents, my sister and my brother in law. Their continuous love, sacrifice, support,
blessings and encouragement have allowed me to pursue my ambitions.
Pansy- Special thanks to you for coming into my life and bringing the joy along. I
finally found my missing part and I can’t think myself without you.
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TABLE OF CONTENTS
Chapter 1.................................................................................................1
Introduction ............................................................................................1
1.1 Basics of flash memory................................................................................. …1
1.1.1 Flash memory operations............................................................................ 2
1.2 Motivation ........................................................................................................ 6
1.3 Tunnel dielectric scaling issues in flash memory ............................................... 7
1.3.1 P/E and retention tradeoff ........................................................................... 7
1.3.2 Issue of stress induced leakage current (SILC).......................................... 10
1.4 Tunnel barrier engineering .............................................................…………..11
1.5 Two approaches to tunnel barrier engineering……………………………….....12
1.5.1 Crested barrier engineering ....................................................................... 12
1.5.2 VARIOT type engineered tunnel barriers.................................................. 14
1.5.3 Comparison .............................................................................................. 17
1.6 Tuning the I-V curve...................................................................................... .18
1.7 High-k materials for engineered tunnel barriers............................................... 20
1.7.1 Material parameters to tune performance .................................................. 21
1.8 Recent literature review .................................................................................. 22
1.9 Thesis organization ......................................................................................... 25
1.10 References .................................................................................................... 26
Chapter 2...............................................................................................30
Simulations............................................................................................30
2.1 Flash constraints ............................................................................................. 31
2.2 Simulations in “No Trap” case ........................................................................ 31
2.2.1 Tunnel barrier engineering........................................................................ 32
2.2.2 Optimization methodology ....................................................................... 34
2.2.3 Results and discussions............................................................................. 35
2.2.4 Summary .................................................................................................. 39
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2.3 Simulations incorporating traps....................................................................... 39
2.3.1 Simulation method.................................................................................... 41
2.3.2 Samples and results .................................................................................. 43
2.4 Optimization with traps................................................................................... 46
2.5 Summary and limitations................................................................................. 49
2.6 References ...................................................................................................... 50
Chapter 3...............................................................................................53
Experimental Results............................................................................53
3.1 Process flow and experimental details ............................................................. 53
3.2 Electrical results for MOS capacitors and TANOS capacitors ......................... 55
3.2.1 Leakage characteristics ............................................................................. 55
3.2.2 TANOS capacitor results .......................................................................... 58
3.2.3 TANOS flash memory transistor results.................................................... 61
3.3 Summary of results ......................................................................................... 66
3.4 References ...................................................................................................... 67
Chapter 4...............................................................................................69
Fluorination...........................................................................................69
4.1 Proposed solutions .......................................................................................... 69
4.2 Motivation for fluorine incorporation as a defect passivant.............................. 70
4.3 Experimental design to incorporate fluorine .................................................... 70
4.4 Electrical results.............................................................................................. 72
4.5 Endurance and Retention................................................................................. 77
4.6 Physical characterization................................................................................. 82
4.7 Model for explaining fluorine’s role................................................................ 86
4.8 References ...................................................................................................... 88
Chapter 5...............................................................................................92
Novel Engineered Tunnel Barriers ......................................................92
5.1 Motivation and experimental design................................................................ 92
5.2 Electrical results and discussion ...................................................................... 95
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5.3 Summary ...................................................................................................... 100
5.4 References .................................................................................................... 100
Chapter 6.............................................................................................103
Conclusions ........................................................................................103
6.1 Key results .................................................................................................... 103
6.2 Future work .................................................................................................. 104
6.3 References .................................................................................................... 106
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LIST OF FIGURES
Chapter 1
Fig. 1.1: Device structure of a flash memory showing different layers.......…………..2
Fig. 1.2: A schematic showing the working mechanism of a flash memory. Drain current
(Id) vs. control gate voltage (Vcg) plot is illustrated. State “1” is achieved when there are
no electrons stored on the floating gate (FG). In presence of charge, state “0” is achieved
thus representing the two bits used. A shift in threshold voltage (Vth) marks the shift in
the Id-Vcg curve. Read voltage (Vread) is applied on control gate to read either of the states.
Difference in current levels between “1” and “0” is used to identify the state of the
memory device [1, 4].................................................................................................. 3
Fig. 1.3: Flash memory operations of program, erase and retention. In program the
control gate bias (Vcg >>0) is positive, in erase Vcg<<0 and in retention Vcg=0………5
Fig. 1.4: Flash memory device scaling history (source: Dr. A. Fazio, Intel Corp.)…...7
Fig. 1.5: (a) Schematic of band diagram during retention for a flash memory with thicker
tunnel oxide (~ 6-7 nm) (b) Similar schematic during retention for flash memory with
thinner tunnel oxide (< 4 nm)………………………………………………………….9
Fig. 1.6: (Left) figure shows ∆Vth shift during program and erase operation. Positive
shifts in threshold voltage reflect the program operation while negative shifts reflect the
erase operation. Scaling the thickness of tunnel dielectric leads to higher P/E memory
window (Right) figure shows the retention behavior for four different thicknesses of
tunnel oxide (TO) based flash memory. Poor retention is observed for thinner dielectric in
accordance with the schematic in Figure 1.5………………………………………….10
Fig. 1.7: Current density-electric field characteristics measured before and after charge
injection stress in MOS capacitors having 5.1 to 9.6-nm SiO2………………….........11
Fig. 1.8 Conduction band edge diagrams of various tunnel barriers: (a) conventional
tunnel barrier; (b) crested symmetric barrier; (c) asymmetric barrier; (d) crested,
symmetric layered barrier; and (e) asymmetric layered barrier. Dashed lines in panels (a)
and (b) show barrier tilting caused by applied voltage. u, u’, d, d’ represent the
conduction band offset (with respect to Si) of high-k, conduction band offset of SiO2
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(with respect to Si), physical thickness of high-k and physical thickness of SiO2
respectively…………………………………………………………………………..13
Fig. 1.9 Conduction band edge diagrams of three different tunnel barriers for low and
high fields respectively corresponding to cases of programming and retention. (a) SiO2
barrier; (b) crested barrier. W stands for ‘write’ or program operation, FG for floating
gate…………………………………………………………………………………...14
Fig. 1.10 Schematic showing engineered tunnel barriers for a nitride based flash memory
in two different implementations; symmetric and asymmetric. Material X represents a
given choice of high-k dielectric. Different layers in the stacks represent metal control
gate (TaN), blocking layer (Al2O3), storage layer (SiN) as discussed previously…...15
Fig. 1.11 Schematic comparing leakage current densities across engineered tunnel stacks
versus SiO2 dielectric stack (all schematics are for leakage across MOS capacitors). All
stacks have 5 nm EOT. The solid line represents the engineered tunnel stacks while the
dashed line represents that of SiO2 layer……….........................................................16
Fig.1.12 Simulated leakage current densities for engineered tunnel stack for different
high-k dielectrics [10]………………………………………………………………..17
Fig. 1.13 Control gate voltage (Vcg) vs. programming time required to achieve fixed
threshold voltage shift; and (b) gate current density due to electrons tunneling out of
floating gate electrode during data retention at Vcg = 0V as a function achieved during
programming[11]…………………………………………………………………….18
Fig. 1.14 Simulations showing J-V tuning by changing the thickness of bottom SiO2 for a
asymmetric tunnel stack (SiO2/HfO2) of fixed EOT [13]……………………………19
Fig. 1.15 Shows various high-k materials used and discussed extensively in literature.
The CB and VB offsets for these materials (with respect to Si) are also mentioned [14]. A
gamut of high-k materials exist and have been studied extensively for CMOS logic
devices. Fig. 1.15 shows a few of those materials with CB and VB offsets with respect to
Si……………………………………………………………………………………..21
Fig. 1.16 ONO engineered tunnel barriers offer better erase characteristics due to
enhanced hole injection from substrate to the storage layer (silicon nitride) [20]…..23
Fig. 1.17 a) Comparison of the experimental and simulated –FN erase of P+- poly gate
Band engineered (BE)-SONOS. Thinner bottom SiO2 shows faster erase speed. When
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bottom oxide is greater than 18 Angstrom, the –FN erase speed becomes very slow (b) F-
N programming characteristics for various bottom SiO2 thickness [21]……………..24
Fig. 1.18 Shows reduction in leakage by using OSO tunnel barrier when compared to
SiO2 barrier of similar EOT [24]……………………………………………………...25
Chapter 2
Fig. 2.1 Comparison between simulation and experimental leakage current results for a
5.6 nm and 8.8 nm SiO2 MOS capacitor. A good comparison is seen for most of the
leakage except at lower voltages. Aluminum metal is the gate used for all these MOS
capacitors……………………………............................................................................32
Fig 2.2 (a) Electron substrate injection in Regimes I-III as described in the text. (b)
Shows the simulated J-V characteristics of asymmetric stack (solid line, where the
thickness of SiO2 layer (Tox) = 2 nm), symmetric (dashed, Tox = 2 nm on either side), and
pure SiO2 (dash-dot) with 6 nm total EOT in both cases. The dotted line is for a thicker
Tox =3.5 nm in the asymmetric 6 nm EOT stack. The four horizontal dashed lines are
Flash constraints mentioned in the text……………………………………………….33
Fig. 2.3 (a) Vprog scaling with Tox for different asymmetric EOTs with HfO2 (note the
minima). The symbols represent the total EOT of the engineered tunnel barrier. Fig. 2.3b
shows the read disturb (top) and retention voltage (bottom) scaling with Tox for the 4, 6
and 8 nm EOT stacks. The top horizontal dashed lines correspond to 2.5 and 3.6 V read
disturb voltage; the bottom one corresponds to -1.5V retention. Symbols for different
EOTs are consistent across both figures………………………………………………35
Fig. 2.4 Optimal Vprog at each EOT for all asymmetric stacks and high-k materials. (a)
Imposes only the retention constraint, while (b) adds in the Vread = 2.5 V read disturb, and
considers the more restrictive 3.6 V in the inset. Symbols are used consistently across the
figures…………………………………………………………………………………37
Fig. 2.5 Change in Vprog for asymmetric barriers with different constraints: retention only
(no read disturb), and with different read disturb criteria Vread = 2.5 and 3.6 V. The values
plotted represent global minima, across all high-k materials considered here………..38
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Fig. 2.6 Schematic representation of the dielectric stack, showing some key parameters
used in simulations……………………………………………………………………41
Fig. 2.7 a) Experimental and simulated JLeak across type A and B capacitors (sample
description is given in table 3). Defect features assumed in simulations: Interface: σT =10-
13 cm2; Uniform ET distribution: 1.3-2.0 eV. Oxide: σT=10-14 cm2; Uniform ET
distribution: 1.6-2.2 eV. b) Experimental and simulated JLeak across type C and D
capacitors. Defect features assumed in simulations: Interface: σT =10-13 cm2; Uniform ET
distribution: 1.3-2.0 eV. Oxide: σT=10-14 cm2; Uniform ET distribution: 1.5-1.9
eV……………………………………………………………………………………...45
Fig. 2.8 JLEAK vs VG curve simulated considering interface (INT), Oxide Defects (OX)
and High-k defects (HK) in addition to Fowler-Nordheim tunneling (FN/DT) current
contribution……………………………………………………………………………45
Fig. 2.9 a) Compares VREAD for SiO2/Al2O3 engineered asymmetric tunnel stack for
with/without traps. The dashed line represents the read disturb constraint at 2.5 V b)
Compares VPROG for the same cases of with/without traps. In both (a) and (b), open
symbols represent simulations with no traps considered while filled symbols take in
account traps……………………………………………………………………..........48
Fig. 2.10 Plot showing Vmax (is maximum voltage applied on floating gate) vs EOT of
tunnel stacks for all materials considered. La2O3 turns out to be the best material for all
EOTs and for all stacks considered……………………………………………….......49
Chapter 3
Fig. 3.1 (a) Schematic of OHO engineered tunnel barrier based TANOS flash memory
(b) shows the general process flow for fabricating a TANOS MOScap or
transistor………………………………………………………………………………54
Fig. 3.2 TEM image of an OHO based TANO flash memory……………………......55
Fig.3.3. Gate leakage characteristics for a SiO2/Al2O3 MOS capacitor structure with two
different Al2O3 thicknesses (2 nm and 8 nm)…………………………………………56
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Fig.3.4. (a) Gate leakage characteristics for a SiO2/HfO2 MOS capacitor structure with
two different HfO2 thicknesses (4 nm and 10 nm) and fixed SiO2 (4 nm) (b) Gate leakage
characteristics for the same stack but with two different HfO2 thicknesses (4 nm and 10
nm) and for different bottom SiO2 layer thickness…………………………………...57
Fig.3.5. Electrical leakage characteristics of a SiO2/HfSiON tunnel stack showing
improved slope in gate leakage characteristics. Black solid lines show simulations for a
SiO2 tunnel stack of same EOT………………………………………………………58
Fig.3.6. Electrical leakage characteristics of a 2.5 nm SiO2/ 6.5 nm HfSiON tunnel stack
showing higher leakage at low voltages and non-steep J-V characteristics……….....58
Fig. 3.7 Cartoon showing CB and VB offsets for Si3N4, Al2O3 and SiO2. The ease of
programming and erase is strongly governed by these................................................60
Fig. 3.8 Program/Erase (P/E) window vs. gate voltage for standard SiO2 based TANOS
and its comparison with OHO and ONO based TANOS. Note that all stacks are of similar
EOT. All measurements are for TANOS capacitors. Positive shift in VFB corresponds to
program operation while the negative shift corresponds to erase…………………....60
Fig. 3.9 Charge loss during retention measurement (at 150 0C for 24 hours) for OHO,
ONO and SiO2. Use of engineered tunnel barriers is thus limited by faster retention
loss……………………………………………………………………………………61
Fig. 3.10 Delta Vth vs. program pulse time for different engineered tunnel stacks based
TANOS flash memory. A comparison can be seen with SiO2 based TANOS of similar
EOT at 17 V programming voltage………………………………………………….62
Fig. 3.11 Erase profile for OHO, OA, OAO, ONO and SiO2 based TANOS flash memory
for -17 V erase voltage………………………………………………………………63
Fig. 3.12 Endurance characteristics for ONO, OA and SiO2 stacks based TANOS flash
memory. The program/erase voltages are adjusted to produce similar P/E window. All
stacks show degradation……………………………………………………………..64
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Fig. 3.13 P/E for ONO, OA and SiO2 is shown on the left while retention (at 1500C for
24hrs) for the same stacks is shown on the right. All stacks have similar EOT…….65
Fig. 3.14 Retention as fractional charge lost from a 4V ∆Vth program after 24 hours at
150 0C (open bars) and Effective +/-17V P/E window in volts (grey bars) comparing OA,
OAO, ONO, OHO with SiO2 (with approximate tunnel oxide EOT listed). Over 400%
P/E window improvement realized using OA, and >300% improvement for ONO vs.
SiO2 [4]………………………………………………………………………………66
Chapter 4
Fig. 4.1 a) Schematic showing TANOS flash memory and position of implant. The
position of implant is referred with numbers 1, 2 or 3 b) shows the samples considered
for our experiments. Samples are compared with/without fluorine implant. The
thicknesses of these layers are mentioned in the bracket along side the stack. All samples
are assigned label as “S#”……………………………………………………………71
Fig. 4.2 a) SRIM simulations for 13KeV,1015/cm2 F implant in the poly-Si cap on top of
the gate. b) Shows the same for a 1KeV, 1015/cm2 implant in TiN gate for a SiO2/HfO2
based MOScap. Similar simulations were done for TANOS flash stacks to ascertain the
dose and energy of the F implant……………………………………………………72
Fig. 4.3 (Left) Plot showing voltage vs. stress time for constant current measurement (for
OHO and OA MOS capacitors). The table shows the estimated Qbd for these samples
with/without fluorine. The bottom right cartoon shows the schematic for the MOS
capacitor structure……………………………………………………………………74
Fig. 4.4 (Left) C-V sweeps from 0-17 V for an OHO TANOS capacitor with/without
fluorine incorporation. It can be clearly observed that Fii samples have a steeper C-V
slope suggesting passivation of interface defects. (right) Shows Dit measurements for
OHO transistors with/without fluorine. For both pre and post stress case, reduction in
interface defects is clearly observed…………………………………………………75
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Fig. 4.5 C-V hysteresis for three OHO TANOS capacitors for three different cases.
Samples S5 (fluorine implant in position 2), S6 (implant in position 3) and S7 (no
fluorine) have been compared for this plot. The hysteresis is observed at +/-17V
program/erase…………………………………………………………………………76
Fig. 4.6 a) Delta Vth shift during program operation (for 11V and 17V) for three cases of
S8 (implant in position 2), S9 (implant in position3) and S10 (no implant) are shown. A
comparison with conventional SiO2 based TANOS is also shown. b) Percent charge
erased from the flash memory as a function of erase pulse time at -17V erase voltage.
Note that all samples had similar initial Vth…………………………………………..77
Fig. 4.7 (left) Interface defect density (Dit) measurement for SiO2 TANOS (using charge
pumping) for three different electric fields. No Dit increase is seen. (right) Interface
defect density measurement under erase operation for different electric fields for the same
case of SiO2 TANOS…………………………………………………………………79
Fig. 4.8 (left) Endurance performance for OHO engineered tunnel stack based TANOS
flash memory. Three different cases of fluorine implant are considered for comparison.
Hole trapping is seen in no-Fii case which improves dramatically with fluorine implant.
(right) Shows endurance for SiO2 and OA based TANOS flash memory. Significant
difference is seen in endurance for SiO2 stack with/without fluorine………………..80
Fig. 4.9 (left) Retention characteristics (at 1500C for 24 hours) for OHO tunnel stacks
based TANOS for three different cases of fluorine implant. Instant charge loss behavior is
observed for the no fluorine case. (right) Instant charge loss behavior for no fluorine case
is studied as a function of retention temperature. It is observed that this behavior is
independent of temperature suggesting leakage through shallow traps in engineered
stacks………………………………………………………………………………….80
Fig. 4.10 Number of Interface states (Nit) as a function of retention time for OHO
TANOS. With fluorine, samples show lower Niti when compared to no fluorine
samples………………………………………………………………………………..81
xviii
Fig. 4.11 Backside SIMS profile for fluorine implanted OHO TANOS. Fluorine was
implanted in the bottom SiO2 of the engineered tunnel stack………………………..83
Fig. 4.12 (a) SIMS profile for fluorine implanted in bottom SiO2 of the engineered tunnel
stack of OHO TANOS. (b) SIMS profile for fluorine implanted in top SiO2 of the
engineered tunnel stack of OHO TANOS of similar EOT. In both cases, fluorine profile
is represented by solid black line……………………………………………………..83
Fig. 4.13 Synchrotron XPS measurements for OHO films with F implant in the bottom
SiO2. a) Shows O 1s spectra for Fii/ non-Fii OHO film. A clearer signature of HfO2 is
seen for non-Fii film. b) Shows shift in Hf 4f lines due to Fii relative to the control non-
Fii sample. (c) and (d) shows similar shifts in Hf 4d and Hf 3d core lines for Fii vs. non-
Fii samples. In all cases, the spectra shifts towards higher binding energy for the Fii
samples relative to non-Fii…………………………………………………………...85
Fig.4.14 a) Spectroscopic ellipsometry measurements show that Fii in HfO2 reduces
interfacial defect density. b) Shows the same effect in SiO2 with forming gas
anneal...........................................................................................................................86
Fig. 4.15 Model showing diffusion of fluorine through engineered tunnel layers and
passivation of interfaces and bulk traps. Table on the right shows bond enthalpies for
relevant bonds formed during fluorine diffusion [23]……………………………….88
Chapter 5
Fig. 5.1 Schematic of the novel tunnel barriers considered (a) SiO2/Si3N4/Al2O3 (ONA)
stack (b) SiO2/Si3N4/La2O3 (ONL) and (c) conventional SiO2 used in TANOS flash
memory………………………………………………………………………………94
Fig. 5.2 Pulse program for different engineered tunnel TANOS capacitor stacks ONL,
ONLN and SiO2. Change in flat band voltage (delta Vfb) vs. program pulse time is shown.
These have been measured at two different programming voltages of 15 V and 19
V……………………………………………………………………………………..96
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Fig. 5.3 C-V hysteresis curves for different engineered stacks ONL, ONLN and SiO2
based TANOS are shown. The C-V sweep is from -10 to 10 V. The initial, programmed
and erase C-Vs are plotted for each stack……………………………………………97
Fig. 5.4 (a) Shows program transients for ONA, ONAF TANOS flash memory transistors
for 11, 13 and 15 V program voltage. (b) Shows erase transients for the same stacks and
for 13, 15 and 19 V erase voltage……………………………………………………98
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LIST OF TABLES
Chapter 1
Table 1: Shows material parameters for different high-k materials. Most of these
parameters are taken from literature and are used in simulations [6,15, 16,
17,18]……......................................................................................................................22
Table 2: Flash operational constraints as provided by Dr. Krishna Parat, Intel
Corporation…………………………………………………………………………….31
Table 3 Main characteristics of the samples considered for simulations……………...43
Table 4: Summary of trap parameters for (A) bulk traps (B) interface traps for different
high-k materials………………………………………………………………………...47
Table 5: Novel engineered tunnel barriers with stack thicknesses. Both TANOS
capacitors and TANOS flash transistors were fabricated as shown above. All thicknesses
are in Angstroms………………………………………………………………………..95
Table 6 Retention characteristics for various engineered tunnel stacks at 1500C and 24
hours. It is important to note that initial Vth was similar for all stacks…………………99
1
Chapter 1
Introduction
In this chapter we will first describe the basics of a flash memory and then look at the
present problems with scaling of tunnel dielectric in these devices. We would also discuss
current research in this area and the solutions proposed to solve the scaling problems. We
end the chapter by discussing a specific solution in detail which would be the centerpiece
of this work.
1.1 Basics of flash memory
Flash memory is a non-volatile device that can be electrically erased and reprogrammed.
It is a technology that is primarily used in memory cards and flash drives for general
storage and transfer of data between computers and other digital products. Example of its
applications includes laptop computers, digital audio players, digital cameras and mobile
phones.
Fig. 1.1 shows the structure of a flash memory device. The device is exactly like a
standard MOSFET transistor but with an extra layer embedded which is called the
floating gate (FG) or the storage layer. This layer is used to store charge and retain it for a
long time even in absence of power (non-volatile). FG can be either heavily doped poly-
Si (in which case the flash memory is called floating gate-flash memory) or can be a
storage layer like silicon nitride (in which case the flash memory is called nitride based
2
flash memory). The blocking layer and the tunnel oxide flank the two sides of the FG
and are meant to prevent charge from leaking out either to the substrate (Si) or to the
control gate. All these layers are capped by the control gate (CG) or gate on the top.
Fig.1.1 Device structure of a flash memory showing different layers.
Conventionally, SiO2 is used as a tunnel oxide due to its excellent interface properties
with Si. On the other hand, SiO2-Si3N4-SiO2 (ONO) was conventionally used as a
blocking layer. However, with scaling of flash memory, high-k dielectrics namely Al2O3
is emerging as a possible replacement for ONO. CG used in flash memory is heavily
doped poly-Si.
A recent variation of the flash memory is called TANOS which stands for TaN-Al2O3-
Si3N4-SiO2-Si structure representing the control gate, blocking oxide, storage layer,
tunnel oxide and the substrate respectively in the order listed. In this structure, the control
gate used is a metal instead of conventional poly-Si and that the storage layer is silicon
nitride. We would be mostly looking at this structure in subsequent chapters.
1.1.1 Flash memory operations
3
We now look at different flash memory operations to understand the mechanism of a
flash memory. Fig.1.2 illustrates the basic mechanism of a flash memory.
Fig.1.2 A schematic showing the working mechanism of a flash memory. Drain current
(Id) vs. control gate voltage (Vcg) plot is illustrated. State “1” is achieved when there are
no electrons stored on the floating gate (FG). In presence of charge, state “0” is achieved
thus representing the two bits used. A shift in threshold voltage (Vth) marks the shift in
the Id-Vcg curve. Read voltage (Vread) is applied on control gate to read either of the states.
Difference in current levels between “1” and “0” is used to identify the state of the
memory device [1, 4].
When the charge is pushed on to the FG (called the ‘program’ operation), the threshold
voltage of the transistor which is defined as:
ox
Sfas
ffbthC
VqNVV
)2(22
+++=
φεφ …………………………….(1)
Where i
a
thfn
NV ln=φ for p-type substrate.......................………...(2)
4
Vfb is the flat band voltage,
Vs is the substrate bias,
Na is the acceptor doping concentration,
q is the electron charge,
Cox is the oxide capacitance
changes according to the formula above. More details about transistor operation and
threshold voltage can be found in [1, 2, 3].
This change in threshold voltage from its initial value is reflected by the shift in the drain
current (Id) – control voltage (Vcg) curve as shown in Fig. 1.2. However, when the charge
is ejected out of FG (called the ‘erase’ operation), the threshold voltage shifts back and
so does the Id-Vcg curve. These two different states of the transistor form state ‘1’ or state
‘0’ of the flash memory. Both program and erase operations are represented by change in
threshold voltage (∆Vth) vs. program/erase voltage. The difference between ∆Vth for
program and erase at a particular control gate voltage is termed as program/erase (P/E)
memory window.
Different operations of flash memory are illustrated in Fig. 1.3.
VCG >> 0 VCG << 0
PROGRAM ERASE
5
Fig. 1.3 Flash memory operations of program, erase and retention. In program the control
gate bias (Vcg >>0) is positive, in erase Vcg<<0 and in retention Vcg=0
In the program operation, electrons are pushed on the FG by applying a positive bias on
the control gate (Vcg), while, in the erase operation, the electrons are ejected out of FG by
applying a negative Vcg. During retention, the charge is retained on the FG. In this
situation, no bias is applied on the control gate. Retention loss in conventional memory
device is observed due to defects in the tunnel dielectric. In subsequent sections we
would discuss this in greater detail.
In read operation, a voltage Vread is applied on control gate which senses the drain
current. Depending upon whether the device is in state ‘0’ or state ‘1’ the drain current
varies; this is thus used to identify the state of the memory device. Another metric of
flash memory performance is endurance characteristics which is the plot of threshold
voltage (Vth) vs. program/erase (P/E) cycles. The memory device is programmed and
erased continuously for >104 times and the threshold voltage is monitored. This is done to
monitor the device reliability under electrical stress. It is often observed that the threshold
voltages drift upwards with P/E cycles (termed as ‘endurance degradation’) for both
program and erase operations. It is well known that such a drift occurs due to electron
trapping in the tunnel oxide [1, 4]. In severe degradation, the Vth of program and erase
operations merge and is termed as ‘window closure’.
VCG = 0
RETENTION
6
In addition to these operations, read and program disturbs are two mechanisms which can
corrupt a memory device. Since memory devices are arranged in an array, data stored on
one device can disturb the stored electron on other device during read or program and are
referred to as read or program disturb respectively. More details on these can be found in
[1, 4].
Having taken a look at the basics of the flash memory, we now move on to understand
the motivation of this work.
1.2 Motivation
Since the inception of the flash memory, there has been an explosive growth in its
market driven primarily by cellular phones and other types of consumer electronic
equipment. Moreover, it is expected that such a demand for memories with higher density
will only increase. From a device perspective, higher density has led to scaling of flash
memory devices. Fig. 1.4 shows the history of flash memory technology scaling from
1986 to 2006. Note that, devices have shrunk by a factor of 1000 during this period. In
2006, flash memory devices were being manufactured at the 65 nm technology node,
today; we are close to sub 30 nm flash memory technology node. In the past scaling of
these devices was much easier. However, as we scale devices beyond the 30 nm
technology node, scaling is soon expected to slow down in absence of solutions to
problems. Most of the scaling limits are now fundamental in nature mostly governed by
materials and device structures. Ergo, there is a need to seek novel materials and
structures.
7
Fig. 1.4 Flash memory device scaling history (source: Dr. A. Fazio, Intel Corp.).
1.3 Tunnel dielectric scaling issues in flash memory
One of the challenges to scale flash memory is the inability to scale down the tunnel
dielectrics. Conventionally, SiO2 (silicon dioxide) has been used as a tunnel dielectric
layer and currently a thickness around 6-7 nm is used in standard flash memory devices
[1]. However, there are two major problems with scaling of SiO2 below present thickness
levels. They are discussed below:
� Issue of program/erase (P/E) memory window and retention tradeoff
� Issue of stress induced leakage current (SILC)
1.3.1 P/E and retention tradeoff
Need Device Structure and Materials
8
As we scale down the tunnel dielectric, the probability of electrons tunneling in or out
increases exponentially. Below 4 nm it is observed that the direct tunneling component
dominates resulting in high charge leakage through tunnel dielectric. This is shown in
schematic in Fig. 1.5. When a thick tunnel oxide (~6-7 nm) is used, tunneling of electrons
in or out of floating gate (FG) occurs mostly by Fowler-Nordheim tunneling (F-N).
However, when a thinner tunnel dielectric (<= 4 nm) is used, direct tunneling dominates
leading to higher leakage. Thus, from a flash memory perspective this means that by
scaling the tunnel dielectric thickness, one can store more charge for the same program
voltage. Hence one can get a higher P/E memory window for the same P/E voltage. At
the same time, ejection of charge also becomes easier due to faster tunneling. This
explains the P/E memory window vs. retention tradeoff.
6-7 nm
Si Conduction band
Blocking layer
FloatingGate
Control GateSi Conduction band
Blocking layer
FloatingGate
Control Gate
Tunnel
Oxide
(A)
6-7 nm
Si Conduction band
Blocking layer
FloatingGate
Control GateSi Conduction band
Blocking layer
FloatingGate
Control Gate
Tunnel
Oxide
6-7 nm
Si Conduction band
Blocking layer
FloatingGate
Control GateSi Conduction band
Blocking layer
FloatingGate
Control Gate
Tunnel
Oxide
Si Conduction band
Blocking layer
FloatingGate
Control GateSi Conduction band
Blocking layer
FloatingGate
Control Gate
Tunnel
Oxide
(A)
9
Fig.1.5 (a) Schematic of band diagram during retention for a flash memory with thicker
tunnel oxide (~ 6-7 nm) (b) Similar schematic during retention for flash memory with
thinner tunnel oxide (< 4 nm).
In other words, we are able to achieve voltage scaling with the same stack materials.
However, the tradeoff lies in the retention characteristics. With increasing probability of
charge leakage, the retention is adversely affected resulting in the tradeoff. In Fig.1.6 the
tradeoff is shown for conventional SiO2 tunnel dielectric [2]. Experimental results of P/E
and retention are compared for 3 nm and 4 nm SiO2 based nitride flash memory. These
results confirm the P/E vs. retention tradeoff experimentally.
Si Conduction band
Blocking
layer
Floating
Gate
Control Gate
Tunnel Oxide
< 4 nm
(B)
Si Conduction band
Blocking
layer
Floating
Gate
Control Gate
Tunnel Oxide
< 4 nm
Si Conduction band
Blocking
layer
Floating
Gate
Control Gate
Tunnel Oxide
Si Conduction band
Blocking
layer
Floating
Gate
Control Gate
Tunnel Oxide
< 4 nm
(B)
10
Fig.1.6 (Left) figure shows ∆Vth shift during program and erase operation. Positive shifts
in threshold voltage reflect the program operation while negative shifts reflect the erase
operation. Scaling the thickness of tunnel dielectric leads to higher P/E memory window
(Right) figure shows the retention behavior for four different thicknesses of tunnel oxide
(TO) based flash memory. Poor retention is observed for thinner dielectric in accordance
with the schematic in Figure 1.5
1.3.2 Issue of Stress Induced Leakage Current (SILC)
Flash memory requires 15-20 V on control gate (CG) for operation. As tunnel dielectrics
get scaled, higher electrical field is applied for the same gate voltage. This generates
electrical stress resulting in generation of defects/ traps in the gate stack. It is well known
that defects in tunnel dielectrics increase trap assisted tunneling (TAT) affecting retention
adversely [3]. Further, when endurance is measured (plot of P/E threshold voltage (Vth)
0%
5%
10%
15%
20%
25%
-4
-3
-2
-1
0
1
2
3
4
5
6
10 12 14 16 18 20
% c
ha
rge
lo
ss
fro
m ~
5V
∆V
tp
rog
ram
150C150C--24hr retention24hr retention100100µµs s P/E P/E vsvs VgVg
Absolute (Vg)
∆V
tp
rog
ram
& e
rase
Thinner OxThinner Ox=faster P/E=faster P/E
30A SiO2
40A SiO2
4.5
Thinner Ox =Thinner Ox =poor retentionpoor retention
4.0
3.5
3.0
SiO2-TOThickness (nm)
0%
5%
10%
15%
20%
25%
-4
-3
-2
-1
0
1
2
3
4
5
6
10 12 14 16 18 20
% c
ha
rge
lo
ss
fro
m ~
5V
∆V
tp
rog
ram
150C150C--24hr retention24hr retention100100µµs s P/E P/E vsvs VgVg
Absolute (Vg)
∆V
tp
rog
ram
& e
rase
Thinner OxThinner Ox=faster P/E=faster P/E
30A SiO2
40A SiO2
4.5
Thinner Ox =Thinner Ox =poor retentionpoor retention
4.0
3.5
3.0
SiO2-TOThickness (nm)
11
shift vs. P/E cycles), window closure is often observed. Part of this behavior has been
attributed to interface defect generation [4]. Therefore scaling of the tunnel dielectric not
only affects retention adversely but also other performance metrics like endurance. Fig.
1.7 illustrates the issue of SILC. As seen in the figure, SILC increases dramatically for
thinner oxides especially at lower applied voltages.
Fig. 1.7 Current density-electric field characteristics measured before and after charge
injection stress in MOS capacitors having 5.1 to 9.6-nm SiO2.
1.4 Tunnel barrier engineering
The problem of tunnel dielectric scaling is relatively old. Researchers have searched for
novel materials for many years. However, it was only after the inception of high-k
dielectrics that tunnel dielectric scaling has looked promising. High-k dielectrics extend
scalability for same equivalent oxide thickness (EOT) by offering a thicker physical
tunnel stack. Using these materials, the concept of engineered tunnel barriers first
12
appeared in 1999 when Likharev et al. [5] introduced crested tunnel barriers. Fig. 1.8
shows a schematic of crested tunnel barriers. In these structures, two high-k layers
sandwich a SiO2 layer. It was shown that using these layers one can achieve faster
program/erase and better retention (due to thicker barrier for same EOT). Within few
years, the idea was extended [6] when VARIOT (acronymed as Variational Oxide
Thickness) was introduced in 2003. In this case, a high-k dielectric material is
sandwiched between two SiO2 layers. Fig. 1.9 illustrates the case of a VARIOT. In the
next section, we discuss both approaches in more detail.
1.5 Two approaches to tunnel barrier engineering
1. 5.1 Crested Barrier Engineering
In crested barriers, the potential barrier height peaks in the middle and gradually
decreases toward the conducting electrodes. Lihkarev et al. [5] demonstrated through
tunneling current simulations that such a composite stack (for e.g. Si3N4/AlN/Si3N4)
would enable far better performance than single-layer SiO2 (of similar EOT) stack in
terms of programming speed and data retention (Fig. 1.8).These improvements were
attributed to the higher slope of the simulated current-voltage (I-V) of the stack [6, 7],
which is superior when compared to SiO2 of same EOT. This can be better understood by
comparing the conduction band edge diagrams of Fig. 1.9 (a,b) [5]. The SiO2 barrier
height changes slowly with an applied field because the highest part of the barrier, closest
to the electron source, is only weakly affected by the applied voltage, as shown in Fig.
1.9a.
13
Fig. 1.8 Conduction band edge diagrams of various tunnel barriers: (a) conventional
tunnel barrier; (b) crested symmetric barrier; (c) asymmetric barrier; (d) crested,
symmetric layered barrier; and (e) asymmetric layered barrier. Dashed lines in panels (a)
and (b) show barrier tilting caused by applied voltage. u, u’, d, d’ represent the
conduction band offset (with respect to Si) of high-k, conduction band offset of SiO2
(with respect to Si), physical thickness of high-k and physical thickness of SiO2
respectively.
In the case of a barrier with a crested conduction band edge profile, the highest part in the
middle is pulled very quickly (barrier lowering in Fig. 1.9 b), which allows for faster
electron injection and thus the current to change between high and low fields. One
practical limitation of crested barrier is related to the fabrication process. Obtaining good
14
interface quality between the high-k and Si channel is difficult. Only a few reports
utilizing crested barrier have been published [8, 9].
Fig. 1.9 Conduction band edge diagrams of three different tunnel barriers for low and
high fields respectively corresponding to cases of programming and retention. (a) SiO2
barrier; (b) crested barrier. W stands for ‘write’ or program operation, FG for floating
gate.
1.5.2 VARIOT-type engineered tunnel barriers
In 2003, Govoreanu et al. [7] proposed a novel engineered tunnel barrier concept called
VARIOT, consisting of a low-k/high-k combination (asymmetric) or a low-k/ high-k /
low-k combination (symmetric) (as shown in Fig.1.10). It is interesting to note that the
crested barrier and the VARIOT have an entirely opposite order in terms of the band gap
and dielectric constant of dielectric stacks. Fig. 1.11 is a qualitative picture illustrating
why engineered barriers perform better than SiO2 for the same EOT. As can be seen, the
difference lies in the slopes of the I-V characteristics for these two stacks of the same
EOT. First note that both stacks have three different I-V regimes. The leakage at lower
voltage, which is governed mostly by direct tunneling across the stacks, is crucial for
good retention. Since engineered tunnel stacks offer a thicker physical barrier when
compared to a SiO2 layer of the same EOT, the leakage current remains low, leading to
15
better retention. At higher voltages, where programming or erase operations take place,
the current is mostly dominated by direct tunneling across SiO2.
Fig. 1.10 Schematic showing engineered tunnel barriers for a nitride based flash memory
in two different implementations; symmetric and asymmetric. Material X represents a
given choice of high-k dielectric. Different layers in the stacks represent metal control
gate (TaN), blocking layer (Al2O3), storage layer (SiN) as discussed previously.
These two regimes have similar slopes for both SiO2 as well as composite engineered
barriers. Corresponding band diagram for each regime for the engineered barriers have
been plotted in Fig 1.11. In the intermediate regime, the difference between the I-Vs of
the stacks can be noticed appreciably. For engineered barriers, the potential drop across
SiO2 modifies the field across the high-k leading to Fowler-Nordheim tunneling (F-N)
through it in the intermediate regime. Since it is well known that the slope of F-N regime
is steeper than direct tunneling regime, we get steeper I-V curve for engineered stacks.
From a flash perspective, because of I-V steepness, the programming voltage is reduced
for engineered tunnel barriers for the same level of program current density (see Fig 1.11).
Si(100)
SiO2
X
SiO2
SiN
Al2O3
TaN
Si(100)
SiO2
X
SiN
Al2O3
TaN
Si(100)
SiO2
SiN
Al2O3
TaN
Symmetric Asymmetric
O/X/O O/X
16
Hence, in principle, one can attain good program/erase and better retention using
engineered tunnel stacks.
Fig. 1.11 Schematic comparing leakage current densities across engineered tunnel stacks
versus SiO2 dielectric stack (all schematics are for leakage across MOS capacitors). All
stacks have 5 nm EOT. The solid line represents the engineered tunnel stacks while the
dashed line represents that of SiO2 layer.
Simulations of MOS capacitor showing steeper slope in J-V characteristics (as shown
qualitatively in Fig. 1.11) are shown in Fig. 1.12 [10] for engineered tunnel stacks with
different higher-k materials. It can be observed that in principle, steeper J-V slopes are
achievable for engineered tunnel stacks but require suitable thickness as mentioned
before.
17
Fig.1.12 Simulated leakage current densities for engineered tunnel stack for different
high-k dielectrics [10].
1.5.3 Comparison
The crested barrier and the VARIOT approaches have both been proven effective for
enhancing field sensitivity. The question is which is more effective? Driussi and Buckley
[11] presented a theoretical analysis of both crested barriers and VARIOT. The main
conclusion was that the VARIOT (low-k/high-k/low-k or low-k/high-k) dielectric stack
combination is a more appropriate candidate as a tunnel barrier for flash memory. As
shown in Fig. 1.13a, the VARIOT stack can potentially achieve smaller programming
times and/or smaller programming voltages than single oxide and the crested barrier (on
the assumption that charge transport in the high-k layer is not entirely inelastic [12]).
Figure 1.13b shows that VARIOT also has a better retention time than single layer of
oxide and the crested barrier structures [11]. In this work, we thus focus only on
engineered VARIOT type tunnel barriers.
18
Fig. 1.13 Control gate voltage (Vcg) vs. programming time required to achieve fixed
threshold voltage shift; and (b) gate current density due to electrons tunneling out of
floating gate electrode during data retention at Vcg = 0V as a function achieved during
programming[11].
1.6 Tuning the I-V Curve
Engineered tunnel barriers are helpful in tuning the current-voltage (I-V) leakage
characteristics. For a fixed EOT of tunnel stack and for a fixed high-k material, the
leakage characteristics can be tuned by varying the thickness of any layer. One such case
19
is demonstrated in Fig. 1.14. For 6 nm EOT of the asymmetric tunnel stack and for a
fixed high-k material (HfO2), the simulated leakage characteristics changes by varying
the bottom thickness of SiO2. As the bottom SiO2 goes from 1.5 nm to 2.7 nm to 4.5 nm
of bottom SiO2 for a constant EOT of the tunnel stack, the simulated leakage profile
changes [13]. The electric field drop across the high-k layer is modulated by the field
drop across the bottom SiO2 layer. With varying thickness of bottom oxide, the potential
drop across SiO2 changes resulting in modifying the drop across the high-k layer as well.
This results in different I-V characteristics. From a flash perspective, for a fixed
programming or erase current density the voltage required to achieve the same
programming/erase voltage can thus be modified by varying the thickness of the bottom
layer. Similarly, the retention characteristics can be modified by changing the gate
leakage at lower voltages.
Fig. 1.14 Simulations showing J-V tuning by changing the thickness of bottom SiO2 for a
asymmetric tunnel stack (SiO2/HfO2) of fixed EOT [13].
2 4 6 8 1010
-20
10-10
100
V (V)
J (A/cm
2)
Pure SiO2
1.5nm SiO2
2.7nm SiO2
4.5nm
Retention Dominated
Program Dominated
Read Disturb Dominated
2 4 6 8 1010
-20
10-10
100
V (V)
J (A/cm
2)
Pure SiO2
1.5nm SiO2
2.7nm SiO2
4.5nm
2 4 6 8 1010
-20
10-10
100
V (V)
J (A/cm
2)
Pure SiO2
1.5nm SiO2
2.7nm SiO2
4.5nm
Retention Dominated
Program Dominated
Read Disturb Dominated
20
1.7 High-k materials for engineered tunnel barriers
We have discussed till now that higher-k materials are required to scale the tunnel stack.
In this regard, we have also discussed that the primary aim is to maintain excellent
program/ erase characteristics yet maintaining at least the same level of retention.
Therefore the high-k material need to satisfy certain requirements to be able to be used in
scaled flash memory. Here are some of them:
• The material should have higher permittivity (when compared to SiO2) to
continue scaling beyond at least one technology node.
• The material should have suitable conduction band (CB) and valence band (VB)
(with respect to Si) offsets to ensure faster program/erase and yet maintain
excellent retention.
• The material should have minimal bulk traps to reduce trap assisted tunneling
(TAT) component in gate leakage. TAT can affect retention adversely and
therefore, we seek to minimize the contribution from traps.
• The material should be compatible with the current technology processes and
also be integrable with Si. The problem with incorporating novel materials is to
keep the cost low while maintaining the quality of the device. Therefore, it is
important that the novel material fits into the existing system and does not incur
additional costs. For example, dopant activation is a standard step in transistor
fabrication and requires high thermal budget (~1000 0C). A novel material must
be able to sustain that temperature without facing degradation in quality.
21
Fig. 1.15 Shows various high-k materials used and discussed extensively in literature.
The CB and VB offsets for these materials (with respect to Si) are also mentioned [14].
A gamut of high-k materials exist and have been studied extensively for CMOS logic
devices. Fig. 1.15 shows a few of those materials with CB and VB offsets with respect to
Si.
1.7.1 Material parameters used to tune performance
High-k materials play a crucial role in engineering the tunnel stack. The relevant material
parameters for a flash memory are its conduction/valence band offset, dielectric constant
and the tunneling effective mass of electrons. In table 1, we summarize these parameters
for different high-k materials used extensively in research. We also consider these
materials in simulations which we will discuss in Chapter 2.
22
Table 1. Shows material parameters for different high-k materials. Most of these
parameters are taken from literature and are used in simulations [6,15, 16, 17,18].
Each of these parameters influences flash memory performance in its own way. We
summarize the effect of each parameter as shown below:
• Higher permittivity (k) => higher physical thickness for same EOT => better
retention from a flash perspective
• Lower effective mass in high-k material => faster program/erase (P/E) (as
electrons can transport through the material rapidly) ; although heavier effective
mass => better retention (difficult for electrons to tunnel through the high-k
material)
• Lower CB and VB => better P/E but poor retention and vice versa.
1.8 Recent literature review
Since the inception of VARIOT type engineered tunnel barriers, a lot of research has
been done in this area. Initially, Houdt [19] verified the concept of steeper slope by using
High-K Materials
Effective Mass
of electrons
(m* /mo)
Dielectric Constant
CB Offset
(eV)
HfO2 0.2 19 1.5
ZrO2 0.2 25 1.4
La2O3 0.25 27 2.3
Al2O3 0.2 9.6 2.8
Y2O3 0.25 25 1.5
SiO2 0.43 3.9 2.8
High-K Materials
Effective Mass
of electrons
(m* /mo)
Dielectric Constant
CB Offset
(eV)
HfO2 0.2 19 1.5
ZrO2 0.2 25 1.4
La2O3 0.25 27 2.3
Al2O3 0.2 9.6 2.8
Y2O3 0.25 25 1.5
SiO2 0.43 3.9 2.8
23
engineered stacks with different high-k materials notably ZrO2. However, till then, the
feasibility of these engineered barriers in flash memory had not been established under
typical flash constraints. Verma et al. [13] established their feasibility under presence of
flash constraints. It was demonstrated that read disturb (discussed previously) is the
limiting constraint for most engineered barriers. More details would be discussed in the
next chapter. More recently, engineered barriers have been used in charge trap flash
memory (CTF) [20]. SiO2/Si3N4/SiO2 (ONO) was shown to be an excellent engineered
tunnel barrier to be used in CTF. SiO2 based CTF is known to suffer from problem of
poor erase due to its higher valence band offset (VB) with respect to silicon. On the other
hand, silicon nitride is known to have reasonable valence band offset (~2.4 eV) when
compared to SiO2 or other higher-k materials. This was shown to enhance hole injection
during erase operation [21] resulting in better performance. Fig. 1.16 illustrates the
advantage offered by ONO engineered tunnel stack.
Fig. 1.16 ONO engineered tunnel barriers offer better erase characteristics due to
enhanced hole injection from substrate to the storage layer (silicon nitride) [20]
24
It was also shown that bottom oxide scaling is crucial for better erase. For bottom oxides
thicker than 18 Å, the erase operation was inefficient as shown in Fig. 1.17. However,
stability was an issue with forming thinner SiO2 bottom layers.
Fig. 1.17 a) Comparison of the experimental and simulated –FN erase of P+- poly gate
Band engineered (BE)-SONOS. Thinner bottom SiO2 shows faster erase speed. When
bottom oxide is greater than 18 Angstrom, the –FN erase speed becomes very slow (b)
+FN programming characteristics for various bottom SiO2 thickness [21]
Alternatives to engineered tunnel barriers have also been investigated. Use of
either metal or semiconductor based nanocrystals help to retain charge even with a
thinner tunnel oxide. This is because of quantization leading to Coulomb blockade effect
[23]. Because of the thin Si layer between the two oxides a quantum well is formed;
hence energy states get quantized leading to reduction in the density of states inside the
well. As a result, only certain energy levels are allowed to be filled. In flash memory
context, this leads to poor program as only few states are available to be programmed.
However, at the same time, better retention can be achieved as electrons stored in
different states need different specific energies to be ejected out. Recently, Toshiba [24]
25
demonstrated that nitride or poly gate based flash memory can be scaled beyond 30 nm
technology node with a scaled SiO2 tunnel oxide (<= 4 nm thickness) by using Si
nanocrystals.
Samsung [25] demonstrated resonant tunneling effect by using a thin Si layer
between two SiO2 tunnel oxides in a nitride based flash memory. The resulting effect is
improvement of retention because of better charge retention. Fig. 1.18 shows
improvement in leakage current specifically at low voltages due to incorporation of a thin
layer of Si between two SiO2 tunnel layers.
Fig. 1.18 Shows reduction in leakage by using OSO tunnel barrier when compared to
SiO2 barrier of similar EOT [24].
In summary, alternatives do exist to engineered tunnel barriers. However, more work
need to be done to implement either of these alternatives in scaled flash memory.
1.9 Thesis Organization
26
The objective of this work is to develop various advanced technologies to
engineer the tunnel barrier to be used in flash memory. Two main issues targeted at the
device level are:
- Endurance (Vth shift vs program/erase (P/E) cycles) improvement
- Retention vs. P/E tradeoff
This dissertation is organized in 6 chapters. Chapter 2 presents results on
simulations for engineered tunnel stacks. First we establish the feasibility of engineered
barriers under flash memory constraints with ideal high-k material (no traps). We then
introduce traps in a random fashion and then examine the impact of traps on performance
of flash memory. Chapter 3 illustrates experimental results for engineered tunnel stacks
based flash memory. We discuss those results for several different high-k materials. We
also talk about issues faced in these stacks and ways to improve it. In Chapter 4 we
discuss fluorine incorporation as a way to solve some of the problems in engineered
tunnel stacks. Emphasis is on retention and endurance problems which are impediments
to scaling of tunnel dielectrics. We show how fluorine incorporation helps in reduction
of leakage at lower voltages and also reduces interface state defect generation. Chapter 5
is devoted to looking at alternative tunnel barrier structures to enhance scaling beyond
one technology node. Finally we summarize the results in Chapter 6 and talk about future
work in brief.
1.10 References
[1] P. Pavan, R. Bez, E. Zanoni, “Flash Memory Cells—An Overview”, Proc. of IEEE,
Vol. 85, No. 8, 1997
27
[2] D. C. Gilmer, N. Goel, H. Park, C. Park, S. Verma, G. Bersuker, P. Lysaght, H.-H.
Tseng, P. D. Kirsch, K. C. Saraswat, R. Jammy, “Engineering the Complete MANOS-
type NVM Stack for Best in Class Retention Performance”, IEEE International Electron
Devices Meeting, 2009
[3] S. M. Sze, Physics of Semiconductor Devices, John Wiley and Sons, Inc, New York,
1981
[4] R. Bez, E. Camerlenghi, A. Modelli, A. Visconti, “Introduction to Flash Memory”,
Proc. of IEEE, Vol. 91, No. 4, April 2003
[5] K. K. Lihkarev, “Layered tunnel barriers for nonvolatile memory devices” Appl. Phys.
Lett., vol. 73, no. 15, pp. 2137-2139, Oct. 1998.
[6] M. Specht, M. Städele, and F. Hofmann, “Simulation of high-K tunnel barriers for
non-volatile floating gate memories,” Proc. ESSDERC Conference, pp. 599-602, 2002.
[7] B. Govoreanu, P. Blomme, M. Rosmeulen, J. Van Houdt, and K. De Meyer,
“VARIOT: a novel multilayer tunnel barrier concept for low-voltage nonvolatile memory
devices,” IEEE Electron Device Lett., vol. 24, no. 2, pp. 99-101, Feb. 2003
[8] S. J. Baik, S. Choi, U-In Chung, and J. T. Moon, “Engineering on tunnel barrier and
dot surface in Si nanocrystal memories,” Solid-State Elect., vol. 48, pp. 1475-1481, 2004.
[9] J. D. Casperson, L. D. Bell and H. A. Atwater, “Materials issues for layered tunnel
barrier structures,” J. Appl. Phys., vol. 92, no. 1, pp. 261-267, 2002.
[10] J. Jung, W. Cho, “Tunnel Barrier Engineering for Non-Volatile Memory”, Journal
of Semiconductor Tech. and Sci. , Vol.8, No.1, March, 2008
28
[11] F. Driussi, S. Marcuzzi, P. Palestri, and L. Selmi, “Gate current in stacked dielectrics
for advanced FLASH EEPROM cells”, Proceedings of ESSDERC, Grenoble, France, pp.
317-320, 2005.
[12] J. Buckley, “Engineering of conduction band crested barriers or dielectric constant
crested barriers in view of their application to floating gate non-volatile memory
devices,” Silicon Nanoelectronics Workshop, 2004.
[13] S. Verma, E. Pop, P. Kapur, K. Parat, K. C. Saraswat, “Operational Voltage Reduction
of Flash Memory Using High-κ Composite Tunnel Barriers”, IEEE Electron Device
Letters, Vol. 29, No. 3, March 2008.
[14] Courtesy Eric Pop, now professor at University of Illinois, Urbana-Champaign
(UIUC)[previously at Intel Corporation].
[15] W. J. Zhu, T. P. Ma, T. Tamagawa, J. Kim, Y. Di, “Current Transport in
Metal/HfO2/Si Structure”, IEEE Electron Devices Letters, Vol. 23, No. 2, February 2002.
[16] C. L. Hinkle, C. Fulton, R. J. Nemanich, G. Lucovsky, “A novel approach for
determining effective tunneling mass of electrons in HfO2 and other high-k alternative
gate dielectrics for advanced CMOS devices”, Microelectronic Engineering, Vol. 72,
Issue 1-4, May 2004
[17] B. Govereanu, P. Blomme, K. Henson, J. V. Houdt, K. D. Meyer, “An Investigation
of the Electron Tunneling Leakage Current through UItrathin Oxides/High-k Gate Stacks
at Inversion Conditions”, IEEE International Conference on Simulation of Semiconductor
Processes and Devices (SISPAD), Leuven, Belgium, 2003
29
[18] G. D. Wilk, R. M. Wallace, T. M. Anthony, “High-k gate dielectrics: Current status
and materials properties considerations”, Journal of Applied Physics, Vol. 89, No. 10, pp.
5243-5275 (2001).
[19] J. V. Houdt, “High-k materials for nonvolatile memory applications”, IEEE 43rd
Annual International Reliability Physics Symposium, San Jose, 2005
[20] H. T. Lue, S. Y. Wang, E. Lai, Y. Shih, S. C. Lai, L. W. Zhang, K. C. Chen, J. Ku,
K. Y. Hseih, R. Liu, C. Y. Liu, “BE-SONOS: A bandgap engineered SONOS with
excellent performance and reliability”, IEEE International Electron Devices Meeting, pp.
547-550, 2005
[21] H. T. Lue, S. Y. Wang, Y. H. Hsiao, E. H. Lai, L. W. Yang, T. Yang, K. C. Chen, K.
Y. Hseih, R. Liu, Y. L. Chih, “Reliability Model of Bandgap Engineered SONOS (BE-
SONOS)”,IEEE International Electron Devices Meeting, pp.1-4, 2006
[22] A. Furnemont, M. Rosmullen, A. Cacciato, L. Breuil, K. De.Meyer, H. Maes, J. V.
Houdt, “Physical Understanding of SANOS Disrturbs and VARIOT Engineered Barrier
as a Solution”, Non-Volatile Semiconductor Memory Workshop, pp. 94-95, 2007.
[23] http://edu.ioffe.ru/register/?doc=galperin/l13pdf1.tex
[24] R. Ohba, Y. Mitani, N. Sugiyama, S. Fujita, “25 nm Planar Bulk SONOS-type
Memory with Double Tunnel Junction”, IEEE International Electron Devices Meeting,
2006
[24] S. Kim, S. J. Baik, Z. Huo, Y. J. Noh, C. Kim, J. H. Han, I. S. Yoo, U. I. Chung, T.
Moon, B. Ryu, “Robust Multi-Bit Programmable Flash Memory Using a Resonant
Tunnel Barrier”, IEEE International Electron Devices Meeting, 2005
30
Chapter 2
Simulations
Lack of voltage scaling in conventional flash memory presents a serious bottleneck in the
future [1]. With continuous CMOS supply voltage (Vdd) reduction, the discrepancy
between Vdd (~1 V) and flash operating voltage (NAND programming voltage (Vprog)
~17 V) is further exacerbated. Large charge pumps, consuming precious area resources,
are needed to bridge this gap. Thus, it is imperative to explore flash structural
modifications, yielding lower operating voltages.
As discussed in Chapter 1, our approach is to modify the tunnel barrier from SiO2 to a
composite stack of different materials. High-k dielectrics with a thicker physical barrier
for the same equivalent oxide thickness (EOT) [2] serve as ideal alternate materials.
Related past work has explored crested composite barriers [3] and an approach using a
smaller barrier material (high-k) between two large barrier materials (SiO2) [4, 5]. Most
of these have been discussed in detail in Chapter 1. However, these works have not
addressed a system-constrained, top-down approach to optimize the design space for
minimum Vprog and EOT. In this chapter, we quantify these trends with retention, read and
program disturb criteria; thus, filtering the choice of materials and the geometry of the
stack. This study yields flash memory compliant optimum composite stacks which
minimize Vprog. However, high-k materials are known to be defect prone. As a result,
31
performance metrics are affected by presence of traps. In the first part, we will discuss
optimization in absence of traps and later incorporate traps in the bulk and at interfaces.
2.1 Flash Constraints
Before we look at optimization of engineered tunnel stacks, we need to consider flash
operation constraints which limit our choice of high-k material, thickness and the type of
stack.
Table 2 Flash operational constraints as provided by Dr. Krishna Parat, Intel
Corporation.
Shown in table 2 are flash operational constraints. These constraints are taken into
consideration during our optimization. More on these constraints is discussed in the text.
2.2 Simulations in ‘No Traps’ Case
< 4*10-6 at
roughly VPROG/2
Tolerable program
disturb density (A/cm2)
>104 Program/
erase Cycles
Endurance
< 10-16 at -1.5VTolerable retention current density(A/cm2)
Tolerable read disturb current density (A/cm2)
< ~4*10-11 at around 3.6 V
< 4*10-6 at
roughly VPROG/2
Tolerable program
disturb density (A/cm2)
>104 Program/
erase Cycles
Endurance
< 10-16 at -1.5VTolerable retention current density(A/cm2)
Tolerable read disturb current density (A/cm2)
< ~4*10-11 at around 3.6 V
32
We consider the case where the high-k material is ideal and has no traps. This will help
establish the feasibility of engineered tunnel stacks and serve as benchmark. The gate
leakage current is first simulated using the Harrison model or the transmission matrix
approach [6]. Fig. 2.1 shows a comparison of leakage current through a SiO2 stack for
experimental and simulation results. A good match can be seen for most range of the
voltage variation. Leakage current data at lower voltages is attributed to traps and
therefore do not produce a good match to simulation predictions.
Fig. 2.1 Comparison between simulation and experimental leakage current results for a
5.6 nm and 8.8 nm SiO2 MOS capacitor. A good comparison is seen for most of the
leakage except at lower voltages. Aluminum metal is the gate used for all these MOS
capacitors.
2.2.1 Tunnel barrier engineering
5.6nm EOTLeaky
Gate Injection
Substrate Injection
-15 -10 -5 0 5 1010
-10
10-5
100
105
V (V)
J (
A/c
m2) 5.6nm pure SiO2
8.85nm pure SiO2
Substrate InjectionGate Injection
8.85nm pureSiO2
5.6nm EOTLeaky
Gate Injection
Substrate Injection
-15 -10 -5 0 5 1010
-10
10-5
100
105
V (V)
J (
A/c
m2) 5.6nm pure SiO2
8.85nm pure SiO2
Substrate InjectionGate Injection5.6nm EOT
Leaky
Gate Injection
Substrate Injection
-15 -10 -5 0 5 1010
-10
10-5
100
105
V (V)
J (
A/c
m2) 5.6nm pure SiO2
8.85nm pure SiO2
Substrate InjectionGate Injection
8.85nm pureSiO2
33
In simulations, we focus on an alternate approach using either a low-k/high-k/low-k
(symmetric) or a low-k/high-k (asymmetric) stack. Such a composite barrier is capable of
yielding steeper current-voltage (J-V) characteristics, resulting in a lower current at low
voltage (retention) and a higher current at higher voltage (program). Thus, programming
voltage (Vprog) can be reduced while meeting retention specifications.
Fig 2.2 (a) Electron substrate injection in Regimes I-III as described in the text. (b)
Shows the simulated J-V characteristics of asymmetric stack (solid line, where the
thickness of SiO2 layer (Tox) = 2 nm), symmetric (dashed, Tox = 2 nm on either side), and
pure SiO2 (dash-dot) with 6 nm total EOT in both cases. The dotted line is for a thicker
Tox =3.5 nm in the asymmetric 6 nm EOT stack. The four horizontal dashed lines are
Flash constraints mentioned in the text.
Fig. 2.2a elucidates the operation of the asymmetric composite barrier. As the gate bias
increases, three distinct regimes of electron substrate injection are observed. Regime I
corresponds to direct tunneling through both low-k and high-k layers; in regime II,
electrons tunnel directly into high-k conduction band (fast Fowler-Nordheim (FN)
transport); regime III consists of direct tunneling through the low-k barrier. Fig. 1b shows
34
that the composite barrier yields a higher non-linearity in J-V compared to the SiO2
dielectric alone, because in regime II the current increases due to both higher electric
field (E-Field) and high-k FN barrier lowering. By comparison, the barrier height of the
SiO2 tunnel dielectric is fixed. Ergo, in principle, composite tunnel stacks can achieve
steeper J-V when compared to SiO2 tunnel oxide of same equivalent oxide thickness
(EOT).
For a given asymmetric stack EOT, a thicker SiO2 layer (Tox) yields steeper J-Vs in
regime II, but the transition to the less steep regime III occurs at lower bias (Fig. 2.2b).
As Tox increases, Vprog reduces when programming occurs in regime II; however at higher
Tox, programming occurs in regime III, where the J-V slope is lower. This results in an
optimum Tox minimizing Vprog (Fig. 2.3a).
2.2.2 Optimization Methodology
We first choose the high-k material. For this material set, we fix the total EOT (high-k +
SiO2) and vary Tox. For each Tox, we calculate the J-V characteristics using the transfer
matrix formulation [6]. From this, we obtain Vprog at the programming current density
(Jprog = 3 × 10-2 A/cm2, typical for NAND Flash, see table for flash constraints). By
repeating this for different EOTs, we get a family of Vprog vs. Tox curves, each exhibiting
a minimum Vprog (Fig. 2.3a). Next, we impose the retention; read and program disturb
conditions (Table 2 and Fig. 2.3b). This limits the permissible Tox range (domain) for
each EOT, which may not include the optimum Tox. Combining the domain selection
with the Vprog vs. Tox curve, we obtain the optimum Vprog for each EOT (Fig. 2.4). The
curve also reveals the minimum possible EOT below which there is no Tox satisfying the
35
Flash constraints. We repeat the process for different high-k materials to get the lowest
possible Vprog as well as 1) the best material set, 2) the lowest EOT, and 3) the optimum
SiO2 thickness for that EOT. We simulate both asymmetric and symmetric composite
barriers, considering five EOTs (4–8 nm). For each EOT, Tox is varied from 1 nm up to
the EOT (asymmetric), and up to EOT/2 (symmetric barrier). The high-k thickness is
changed accordingly. Table 1 (in Chapter 1) lists the simulated high-ks and their typical
parameters [7].
Fig. 2.3 (a) Vprog scaling with Tox for different asymmetric EOTs with HfO2 (note the
minima). The symbols represent the total EOT of the engineered tunnel barrier. Fig. 2.3b
shows the read disturb (top) and retention voltage (bottom) scaling with Tox for the 4, 6
and 8 nm EOT stacks. The top horizontal dashed lines correspond to 2.5 and 3.6 V read
disturb voltage; the bottom one corresponds to -1.5V retention. Symbols for different
EOTs are consistent across both figures.
2.2.3 Results and Discussion
36
In addition to higher non-linearity compared to SiO2 tunnel barrier, Fig 2.2b also shows
that the J-V corresponding to the symmetric stack is shifted right compared to its
asymmetric counterpart (later onset of fast FN tunneling). Thus, for a given programming
current density (Jprog), the asymmetric stack will have a lower Vprog. However, the read
disturb condition for the asymmetric case will be more easily violated. Hence, for a
realistic flash memory operation, the superiority of the asymmetric stack over the other is
highly constraint dependent.
Two read voltage constraints on the floating gate (FG) are considered: Vread = 3.6 V
(modern industry standard), and 2.5 V (ITRS projections [8]). To prevent memory
contamination, the maximum tolerable injection current densities during a single read,
program, and retention are 7 × 10-11 A/cm2, 7 × 10-6 A/cm2 (at Vprog/2), and 2 × 10-16
A/cm2 (at Vret = 1.5 V, 10 year criteria), respectively (as also described in Table 2). Fig.
2.3b shows the maximum allowed retention (Vret) and read voltages (Vread) at the floating
gate as a function of Tox, so as to not exceed the maximum retention and read disturb
currents. It also shows dashed lines corresponding to Vret and Vread. Only the part of the
curve (i.e., the Tox domain) above Vread dashed lines and below Vret meet the read disturb
and the retention criteria respectively. We transfer this domain selection back to Fig.
2.3a, to choose the minimum Vprog in that domain for every EOT.
Fig. 2.4 shows the minimum Vprog as a function of EOT for all high-k materials
considered here. In particular, Fig. 2.4a narrows the selection based only on the retention
criteria (no read disturb). The composite stacks with HfO2, ZrO2, Y2O3 yield the lowest
Vprog (~2.9 V), at EOTs as low as 4 nm. These voltages should be divided by the gate
coupling ratio (GCR~0.6) to obtain the control gate bias. Although La2O3 has the highest
37
dielectric constant, its stack fails to provide low Vprog due its higher band offset (closer to
SiO2). The impact of adding the read disturb (Vread = 2.5 V) is to further restrict the Tox
domain (Fig. 2.4b). Two trends ensue for the stacks with HfO2, ZrO2 or Y2O3. First, a
higher minimum EOT is noted. Second, the minimum Vprog for lower EOT increases
because the global minimum for these EOTs (Fig. 2.3a) does not fall within the allowed
Tox domain. The read disturb condition has the least impact on the La2O3 stack owing to
its higher band offset. This results in a lower J at Vread, allowing it to satisfy the read
disturb condition more easily. For the more stringent read voltage condition of 3.6 V
(inset Fig. 3b), HfO2, ZrO2 and Y2O3 satisfy the read disturb criteria only down to 7 nm
EOT. La2O3 yields results with EOTs as low as 4 nm and corresponding Vprog of ~5.1 V
(at FG). The program disturb constraint was found to be less stringent than read disturb.
Similar results were obtained for symmetric stacks.
Fig. 2.4 Optimal Vprog at each EOT for all asymmetric stacks and high-k materials. (a)
Imposes only the retention constraint, while (b) adds in the Vread = 2.5 V read disturb, and
38
considers the more restrictive 3.6 V in the inset. Symbols are used consistently across the
figures.
Fig. 2.5 summarizes all optimizations of the asymmetric stack with retention only, and
with the two different read disturb constraints. Clearly read disturb is more constraining
than the retention criteria and results in a higher Vprog. Further, a comparison between
asymmetric and symmetric stacks (not shown) revealed that at both low (~4 nm) and high
EOTs (7–8 nm) the asymmetric stack performs better. However, at intermediate EOTs
(5–6 nm) and with more stringent read disturb the symmetric barrier performs better. We
find that HfO2 enables the lowest Vprog of 3.95 V at an EOT of 5 nm (for a Vread = 2.5 V),
while La2O3 gives the lowest Vprog of 5.1 V at an EOT of 4 nm (for Vread = 3.6 V).
Fig. 2.5 Change in Vprog for asymmetric barriers with different constraints: retention only
(no read disturb), and with different read disturb criteria Vread = 2.5 and 3.6 V. The values
plotted represent global minima, across all high-k materials considered here.
39
2.2.4 Summary
We performed the optimization of a composite tunnel barrier with respect to SiO2
thickness and EOT to obtain the minimum Vprog under typical Flash constraints
(retention, read and program disturb). This was done for five high-k materials under both
symmetric and asymmetric stack configurations. We find that read disturb is the most
constraining factor, partly restricting the advantage offered by the composite barrier. A
stringent read disturb limits the use of HfO2, ZrO2 or Y2O3 in such composite barriers,
while La2O3 appears more promising from the point of view of scalability. Vprog of 4–5 V
on FG may be possible with the composite stack, a decrease of 40 % from the tunnel
barrier based on pure SiO2 alone.
2.3 Simulations Incorporating Traps1
As mentioned, engineered tunnel barriers are typically comprised of symmetric (low-
k/high-k/low-k) or asymmetric (low-k/high-k) stacks. Theoretically, they allow
improving flash memory retention compared to conventional tunnel oxide [11],
guaranteeing the same Program/Erase (P/E) performances. Unfortunately, high-k
materials feature very high bulk defect and interface state densities, and their theoretical
1 In collaboration with Prof. Luca Larcher and Dr. Andrea Padovani, Università di
Modena e Reggio Emilia
40
advantages in retention improvement have to be weighted against their degraded parasitic
trap-assisted leakage currents that lead to the undesired reduction of the threshold
voltage. This aspect is very important in the assessment of real chances of high-k stacks
to replace conventional SiO2 tunnel layers. Simulations are indispensable in this context,
especially in accounting for the statistical distribution of leakage current related to
random defect generation, that cannot be investigated using experimental methods only,
as extensive reliability measurements on large flash memory array are very time-
consuming and costly [9]. To incorporate traps, a Monte-Carlo (MC) simulator based on
a multi-phonon trap-assisted conduction mechanism [10] is used to calculate tunnel
currents across the high-k dielectric stacks. Upon obtaining the tunnel current, flash
memory operational constraints (like in the case of ‘no traps’) are imposed to verify the
real feasibility of high-k tunnel dielectrics in flash memory applications. In recent years,
the modeling of tunneling currents across SiO2/high-k dielectric stacks has been only
marginally addressed [11]-[14]. Most of the proposed models calculate only direct and
Fowler-Nordheim (FN) tunneling currents [11]-[12], whereas the few studies that
modeled also the trap-assisted transport across the dielectric stack neglect oxide and
interface traps [13]-[14], which are found to be dominant especially for substrate
injection. Fig. 2.6 shows the idea behind incorporating traps. Defects are considered in a
random fashion throughout the stack.
41
Fig. 2.6 Schematic representation of the dielectric stack, showing some key parameters
used in simulations. N,σ, E represent the trap density, capture cross section and the
energy of the traps in SiO2, high-k and at the interface respectively.
2.3.1 Simulation Method [10]
To simulate the leakage current flowing through generic SiO2/high-k dielectric stacks, an
extension to the statistical Monte Carlo simulator (used in [15]) has been considered. The
conduction mechanism considered for the leakage current calculation is the multi-Phonon
Trap-Assisted Tunneling (PTAT) [10]. Compared to the simpler SiO2 case, several issues
related to the presence of a composite dielectric stack have to be accounted for, such as
the calculation of the electric field in different materials and of the tunneling probability
between traps located in different dielectrics. The Monte Carlo simulator developed is
comprised of three main parts.
42
1. Electric field calculation: The electric fields within oxide (FOX) and high-k (FHK)
dielectric layers are calculated by taking into account charge quantization effects [20].
The amount of charge trapped in high-k and oxide bulks and at the SiO2 / high-k interface
has been estimated from capacitance-voltage (C-V) measurements. This charge has been
accounted for in the field calculation.
2. Random generation of defects: Defects are randomly generated within oxide and high-
k dielectric and at their interface, according to device geometry and defect statistics.
Defect densities (NT), cross sections (σT), and energy distributions (ET) have been
considered for different defects, as sketched in Fig. 2.6. For each of these features, one
can select fixed as well as random values generated considering various statistical
distributions. This is very important to simulate the leakage current through thin gate
stacks (EOT≈1-2nm), as experimental evidences of non-uniform spatial distribution of
defects have been reported already [16].
3. Leakage current density (JLEAK) calculation: Once traps have been generated, JLEAK is
calculated by summing both direct (JTUNN) and defect-assisted (JPTAT) tunneling
contributions. As traps are randomly generated, the model automatically accounts for the
presence of multi-trap conductive paths formed by two or more traps aligned in space and
energy [10], enabling statistical simulations of leakage currents. The total current is given
by the sum of current contributions due to single- and multiple-trap conductive paths. The
tunnel probability is calculated using the WKB method and the model simply accounts
43
for the energy barrier reduction induced by positively charged traps. Thermal emission
(TE) and Poole-Frenkel (PF) mechanisms are also included, since they could play an
important role at low fields, i.e. in retention conditions. To conclude, repeating
simulations assuming the same defect characteristics allows calculating JLEAK
distributions at different fields. The parameters used for the simulation of SiO2/HfO2 and
SiO2/HfSiON stacks are reported in Table 1. For the TaN gate, we considered a 4.6 eV
work function [17].
2.3.2 Samples and Results
Samples used in this work are pMOS (n-type Si (100) substrate) capacitors. The dielectric
stacks comprised of a silicon dioxide layer and a Hf-based high-k layer have been
considered. The generic band diagram of the structure is sketched in Fig. 2.6. Table 3
reports thicknesses of oxide (tOX) and high-k (tHK) layers, the equivalent dielectric
thickness (EOT), and the oxide (NOX) and SiO2/high-k interface (NINT) defect densities
we considered in simulations.
Table 3 Main characteristics of the samples considered for simulations.
To verify the accuracy of the simulator, experimental leakage currents were reproduced
which were measured on relatively large area capacitors (compared to typical state-of-
44
the-art flash memory cell size). This way, features of bulk and interface defects were
derived and were used to calculate JLEAK distributions in retention and read disturb
conditions. Figs. 2.7 (a) and (b) show JLEAK -VG curves simulated and measured on
pMOS capacitors with different SiO2/HfO2 and SiO2/HfSiON dielectric stacks (see Table
3.) As shown, the agreement between measurements and simulations is excellent.
Noticeably, simulations are performed considering only oxide and SiO2/high-k interface
defect contributions (see values in Table 1), whereas HfO2 and HfSiON bulk traps were
not considered because they negligibly affect JLEAK curves when electrons are injected
from the substrate, at least for the dielectric thicknesses considered here.
(A)
45
(B)
Fig. 2.7 a) Experimental and simulated JLeak across type A and B capacitors (sample
description is given in table 3). Defect features assumed in simulations: Interface: σT =10-
13 cm2; Uniform ET distribution: 1.3-2.0 eV. Oxide: σT=10-14 cm2; Uniform ET
distribution: 1.6-2.2 eV. b) Experimental and simulated JLeak across type C and D
capacitors. Defect features assumed in simulations: Interface: σT =10-13 cm2; Uniform ET
distribution: 1.3-2.0 eV. Oxide: σT=10-14 cm2; Uniform ET distribution: 1.5-1.9 eV
Fig. 2.8 JLEAK vs VG curve simulated considering interface (INT), Oxide Defects (OX)
and High-k defects (HK) in addition to Fowler-Nordheim tunneling (FN/DT) current
contribution.
Interface traps are found to be critical especially at low VG, i.e. in retention conditions,
whereas bulk oxide traps dominate JLEAK conduction mechanism at relatively higher
voltages, i.e. in the program/erase regime. This is clearly shown in Fig. 2.8, where roles
played by interface, oxide and high-k defects are highlighted. Interface traps on the other
hand play a crucial role at intermediate voltages thus affecting read disturb. Similar
46
simulations were repeated for various high-k based tunnel stacks. Finally we summarize
the material trap parameters for various high-k materials studied. Table 4 shows NT
(density of traps), ET (energy level of traps) and σT (capture cross section of traps) for
both bulk and interface traps for high-k materials.
2.4 Optimization with traps
In this section, we perform similar optimization as performed for the case of ‘no traps’
(described earlier). The aim of the simulation is establish the best choice of material,
thickness and stack preference as was done earlier.
(A)
(B)
NT [cm-3] ET [eV] σT [cm2]
SiO2 5⋅⋅⋅⋅1016 2.3-2.9 10-14
HfO2 5⋅⋅⋅⋅1019 1.2-1.3 10-14
Al2O3 1⋅⋅⋅⋅1019 1.6-1.7 10-14
Si3N4 2⋅⋅⋅⋅1019 1.5-1.7 10-14
NT [cm-3] ET [eV] σT [cm2]
SiO2 5⋅⋅⋅⋅1016 2.3-2.9 10-14
HfO2 5⋅⋅⋅⋅1019 1.2-1.3 10-14
Al2O3 1⋅⋅⋅⋅1019 1.6-1.7 10-14
Si3N4 2⋅⋅⋅⋅1019 1.5-1.7 10-14
NT [cm-2] ET [eV] σT [cm2]
SiO2/HfO2 1⋅⋅⋅⋅1012 1.5-2.0 10-13
SiO2/Al2O3 1⋅⋅⋅⋅1012 1.0-1.8 10-13
SiO2/Si3N4 1⋅⋅⋅⋅1012 1.0-2.0 10-13
NT [cm-2] ET [eV] σT [cm2]
SiO2/HfO2 1⋅⋅⋅⋅1012 1.5-2.0 10-13
SiO2/Al2O3 1⋅⋅⋅⋅1012 1.0-1.8 10-13
SiO2/Si3N4 1⋅⋅⋅⋅1012 1.0-2.0 10-13
47
Table 4: Summary of trap parameters for (A) bulk traps (B) interface traps for different
high-k materials.
The leakage current is simulated using the Monte Carlo simulator as mentioned before. A
statistical distribution of leakage current is obtained and thereafter, the mean of such a
distribution is looked to ascertain performance metrics like retention, disturbs etc. Fig.
2.9 shows the impact of traps on read disturb and on program voltage for a SiO2/Al2O3
asymmetric stack. The results are demonstrated for different EOTs of the engineered
tunnel stack. As can be observed, presence of traps in general decreases the program
voltage which implies voltage scaling. However, read disturb is adversely affected by
presence of traps and as one can note, only few stack layers satisfy standard flash
constraints at -2.5 V.
(A)
0
2
4
6
8
0 2 4 6 8
VR
EA
D[V
]
TOX [nm]
EOT [nm] 4 EOT [nm] 6 EOT [nm] 8
Empty symbols: no traps
Filled symbols: with traps
NT,OX = 2·1017 cm3
NT,INT = 1.5·1012 cm2
NT,HK = 2·1019 cm3
VREAD constraint
(JLEAK= [email protected])
48
(B)
Fig. 2.9 a) Compares VREAD for SiO2/Al2O3 engineered asymmetric tunnel stack for
with/without traps. The dashed line represents the read disturb constraint at 2.5 V b)
Compares VPROG for the same cases of with/without traps. In both (a) and (b), open
symbols represent simulations with no traps considered while filled symbols take in
account traps.
Similar simulations are performed for other materials and other asymmetric stacks and
finally the optimization is performed for all stacks in consideration. The final results are
illustrated in Fig. 2.10. It turns out that among all materials considered, La2O3 is the best
material providing minimum operational voltage. Even in presence of traps, La2O3 based
tunnel stack satisfies all the flash memory constraints and provides a comparative
advantage over conventional SiO2 in terms of operating voltages.
3
5
7
9
11
0 2 4 6 8
VP
RO
G[V
]
TOX [nm]
EOT [nm] 4 EOT [nm] 5 EOT [nm] 6 EOT [nm] 7 EOT [nm] 8
Empty symbols: no traps
Filled symbols: with traps
NT,OX = 2·1017 cm3
NT,INT = 1.5·1012 cm2
NT,HK = 2·1019 cm3
49
6
6.5
7
7.5
8
8.5
9
9.5
4.5 5.5 6.5 7.5 8.5EOT (nm)
Vm
ax(V
)
Fig. 2.10 Plot showing Vmax (is maximum voltage applied on floating gate) vs EOT of
tunnel stacks for all materials considered. La2O3 turns out to be the best material for all
EOTs and for all stacks considered.
Feasibility of engineered tunnel stacks is hence established even in presence of traps. For
each stack and material, operational flash constraints (as discussed earlier) were imposed
in presence of traps and then the optimization was performed. As seen, it is possible to
achieve a Vmax (is the maximum voltage applied on floating gate) of around 7 V for a 4.5
nm EOT of tunnel stack with bulk and interface traps. This is equivalent to around 14 V
on control gate (with gate coupling ratio of ~0.5) which is still an improvement over 17-
18 V applied as of today.
2.5 Summary and Limitations
La2O3
50
We examined the feasibility of engineered tunnel stacks with /without presence of
defects. Under both cases, we could establish that engineered tunnel stacks do enhance
voltage scaling even under operational constraints. Following are the key results:
• La2O3 is the best high-k material (among all materials considered) to work
providing advantage over conventional SiO2 dielectric. This is true for both
with/without traps in the dielectric.
• Symmetric barriers are preferred over asymmetric barriers as they offer advantage
in voltage scaling.
• Bottom SiO2 thickness should be around 2 nm (20 Å) for optimal performance of
the stack.
• Presence of traps adversely affects read disturb and retention while reducing
program/erase voltage for same pulse time.
Even though our simulations give us a definite trend, there are certain limitations to it.
The model does not account for intermixing of different high-k layers (diffusivity of
atoms at higher temperatures) and also assumes a sharp interface. Further, process
treatments are not taken into account as well. As a result, one should consider these
results as a trend and take it with a grain of salt.
2.6 References
[1]. R. Bez, E. Camerlenghi, A. Modelli and A. Visconti, “Introduction to Flash
Memory,” Proc. IEEE, vol. 91, pp. 489-502, 2003.
51
[2]. J. Robertson, “High Dielectric Constant gate oxides for metal oxide Si Transistors,”
Rep. Prog. Phys., vol. 69, pp. 327-396, 2006.
[3]. K. K. Likharev, “Layered tunnel barriers for non volatile memory devices,” Appl.
Phys. Lett., vol. 73, pp. 2137-2139, 1998.
[4]. B. Govoreanu, P. Blomme, M. Rosmeulen, J. Van Houdt and K. De Meyer,
“VARIOT: a novel multilayer tunnel barrier concept for low-voltage nonvolatile memory
devices,” IEEE Electron Dev. Lett., vol. 24, pp. 99-101, 2003.
[5]. J. Van Houdt, “High-k materials for nonvolatile memory applications,” 43rd Annual
IEEE IRPS, pp. 234-239, San Jose, 2005.
[6]. Y. Ando and T. Itoh, “Calculation of transmission tunneling current across arbitrary
potential barriers,” J. Appl. Phys., vol. 61, pp. 1497-1502, 1987.
[7]. C.L. Hinkle, C. Fulton, R. J. Nemanich and G. Lucovsky, “A novel approach for
determining the effective tunneling mass of electrons in HfO2 and other high-- alternative
gate dielectrics for advances CMOS devices” Micro. Eng., vol. 72, pp. 257-262, 2004.
[8]. International Technology Roadmap for Semiconductors (ITRS) 2005, “Emerging
Research Devices,” http://public.itrs.net
[9]. L. Larcher, and P. Pavan, “Statistical simulations to inspect and predict data retention
and program disturbs in Flash memories,” IEDM Tech. Dig., 2003, pp. 165-168.
[10]. L. Larcher, “Statistical Simulation of Leakage Currents in MOS and Flash Memory
Devices with a New Multiphonon Trap-Asisted Tunneling Model”, IEEE Trans. On Elec.
Devices, Vol. 50, No. 5, May 2003.
52
[11]. B. Govoreanu, P. Blomme, M. Rosmeulen, J. V. Houdt, and K. De. Meyer, “A
model for tunneling current in multi-layer tunnel dielectrics,” Solid State Electron., Vol.
47, No. 6, pp. 1045-1053, June 2006.
[12] F. Sacconi, J. M. Jancu, M. Povolotskyi, and A. Di Carlo, “Full-Band tunneling in
high-k oxide MOS structures,” IEEE Trans. Electron Devices, Vol. 54, No. 12, pp. 3168-
3176, December 2007.
[13] A. Campera, G. Iannacone, and F. Crupi, “Modeling of tunneling currents in Hf-
based gate stacks as a function of temperature and extraction of material parameters,”
IEEE Trans. Electron Devices, Vol. 54, No. 1, pp. 83-89, January 2007.
[14] O. Blank et al., “A model for multistep trap-assisted tunneling in high-k dielectrics,”
J. Appl. Phys., Vol. 97, No. 4, p. 044147, April 2005.
[15]. A. Padovani, L. Larcher, A. Chimenton, and P. Pavan, “Monte-Carlo simulations of
Flash memory array retention” in Proc. of the IEEE VLSI-TSA, 2007, pp. 156-157.
[16]. C. D. Young et al., “Electron trap generation in high-k gate stacks by constant
voltage stress,” IEEE Trans. Device Mater. Rel., Vol. 6, No. 2, pp. 123-131, June 2006
[17]. H.-C. Wen et al., “Comparison of effective work function extraction methods using
capacitance and current measurement techniques” IEEE Electron Device Lett., Vol. 27,
No. 7, pp. 598-601, July 2006.
53
Chapter 3
Experimental Results
In Chapter 2, we performed simulations to establish the feasibility of engineered
dielectric (tunnel) stacks. We were able to get definite trends which can guide us to
design our experiments. In this chapter we will look into experimental designs and also
show some experimental results which are important to understanding engineered tunnel
stacks. The chapter would be broken down into following segments. We will first discuss
the process flow to fabricate MOS capacitors and flash memory transistors for our study.
We will then describe the electrical measurements we are interested in and then
demonstrate key results. We will finally show some practical issues with implementation
of engineered tunnel stacks and propose alternative solutions. In our work, we mainly
concentrate on nitride based TANOS (TaN-Al2O3-Si3N4-SiO2-Si) flash memory.
3.1 Process flow and experimental details
Fig. 3.1 (a) is a schematic showing the device structure of a nitride based TANOS (TaN-
Al2O3-Si3N4-SiO2-HfSiO-SiO2-Si) flash memory, where SiO2-HfSiO-SiO2 represents
engineered tunnel barrier. In Fig. 3.1(b) we show the generalized process flow for
fabricating a MOS capacitor or transistor. TANOS flash n channel MOSFETs were
formed using 40 Å SiO2 as an experimental control. Various band engineered flash
memory structures with symmetric OXO (SiO2/high-K/SiO2) or asymmetric OX
54
(SiO2/high-k) layers were also fabricated into a TANOS type device using Hf(Si)O2,
Al2O3, or Si3N4 as the high-K and labeled as OHO, OAO, ONO or OA respectively. In
future the acronyms would be used for convenience referring to different engineered
tunnel stacks. All devices used the same fabrication steps for the 6nm Si3N4 charge
storage layer, 11nm Al2O3 blocking layer, and TaN electrode. Dopant activation was
done with a 1020°C-spike anneal.
Fig. 3.1 (a) Schematic of OHO engineered tunnel barrier based TANOS flash memory
(b) shows the general process flow for fabricating a TANOS MOScap or transistor
The high-k layers used in engineered tunnel barriers are deposited using ALD (Atomic
Layer Deposition) at a low temperature (~350°C). Once the device is fabricated, TEM
(Transmission Electron Microscopy) is performed to check for the target thickness. As
mentioned in Chapter 2, the target thickness for bottom SiO2 is around 2 nm for optimal
performance. Fig. 3.2 shows the TEM image of the flash memory device confirming our
General process flow:• Tunnel-oxide (SiO2 only, or band-
engineered tunnel barrier stack) grown
• 7nm Si3N4 charge trapping layer deposition
• 12 nm Al2O3 Blocking layer deposition
• TaN electrode deposition
• Implant & 1020 C activation for nMOSFET
• Forming gas anneal to finish
� nMOSFET and nMOS capacitor Silicon(100)
SiO2
HfSiO
SiO2
60 A Si3N4
110A Al2O3
TaN electrode
Silicon(100)
SiO2
HfSiO
SiO2
60 A Si3N4
110A Al2O3
TaN electrode
(A) (B)
55
target thickness for different layers. Note that bottom SiO2 thickness is close to target
value of ~2 nm.
Fig. 3.2 TEM image of an OHO based TANO flash memory.
3.2 Electrical Results for MOS capacitors and TANOS
capacitors
We now look at electrical results obtained for simple MOS capacitors and TANOS
capacitors for different high-k based engineered tunnel stack systematically.
3.2.1 Leakage Characteristics
First we look at leakage characteristics of simple MOS capacitor structures to see for the
steepness in current density-voltage (J-V) curve as confirmed by theoretical simulations.
Fig.3.3 shows the leakage characteristics for SiO2/Al2O3 MOS capacitor (with TaN metal
gate) for 2 different thicknesses of Al2O3 (2 nm and 8 nm). There are 2 major
10 nm10 nmImg: 'E4629 080929015_7031306_18_898 FET_rot_s_s.Ed.dm3' MAG: 195kX
Poly
TaN
AlOx
SiOx
SiNx
HfSiOx
SiOx
Si substrate
9.9 nm
11 nm
5.6nm4.1 nm
3.6 nm1.9 nm
10 nm10 nmImg: 'E4629 080929015_7031306_18_898 FET_rot_s_s.Ed.dm3' MAG: 195kX
Poly
TaN
AlOx
SiOx
SiNx
HfSiOx
SiOx
Si substrate
9.9 nm
11 nm
5.6nm4.1 nm
3.6 nm1.9 nm
56
observations which can be seen clearly. First note that J-V curve can be tuned with
varying thicknesses of SiO2 as well as high-k (Al2O3) material.
Fig.3.3 Gate leakage characteristics for a SiO2/Al2O3 MOS capacitor structure with two
different Al2O3 thicknesses (2 nm and 8 nm).
Further, for a thicker Al2O3 the leakage is lower at lower voltages as can be seen in both
figures. For thinner Al2O3, however, it is easier to transition into different tunneling
regimes (as mentioned in Chapter 2) with varying the gate voltage. This is understandable
as the field drop across the tunnel stack (for the same voltage) is more significant for
thinner EOTs. In either case, the steepness in J-V is not seen when compared with SiO2
MOS capacitors of similar EOT. This is primarily attributed to traps in bulk or at
interfaces in tunnel stack. Also, none of the samples shown have sufficiently lower
leakage (at lower voltages) to meet the standard retention constraint in flash memory. The
situation is similar for other high-k materials as well. Fig. 3.4 summarizes leakage
currents for SiO2/HfO2 tunnel stack which also shows higher leakage at lower voltages
pertaining to poor retention. However, when HfO2 is nitrided (to HfSiON), it shows
0 1 2 3 4 5
10-8
10-6
10-4
10-2
100
V (V)
J (A/cm
2)
D=252um, Al2O3=2nm
Tox=1nm
2nm
3nm
4nm
0 1 2 3 4 5
10-8
10-6
10-4
10-2
100
V (V)
J (A/cm
2)
D=252um, Al2O3=8nm
Tox=1nm
2nm
3nm
4nm
57
steeper J-V when compared to SiO2 of similar EOT [1]. This can be seen in Fig. 3.5. It is
well known that nitridation of Hf based high-k results in passivation of bulk traps [2].
Fig.3.4 (a) Gate leakage characteristics for a SiO2/HfO2 MOS capacitor structure with
two different HfO2 thicknesses (4 nm and 10 nm) and fixed SiO2 (4 nm) (b) Gate leakage
characteristics for the same stack but with two different HfO2 thicknesses (4 nm and 10
nm) and for different bottom SiO2 layer thickness.
0 2 4 6 8 1010
-8
10-6
10-4
10-2
100
V (V)J (A/cm
2)
TaCN gate, D=50um
Tox=2nm
4nm
6nm
8nm
HfO2=4nm
HfO2=10nm
0 2 4 6 8 1010
-8
10-6
10-4
10-2
100
V (V)
J (A
/cm
2)
TaCN gate, TOX
=4nm
D=50um
80um
252um
HfO2=4nm
HfO2=10nm
0 2 4 6 810
-10
10-8
10-6
10-4
10-2
100
102
V (V)
J (A
/cm
2)
Experimental
Control SiO2
Experimental
SiO2/HfSiONx
Asymmetric Stack
Simulated J-V curves
0 2 4 6 810
-10
10-8
10-6
10-4
10-2
100
102
V (V)
J (A
/cm
2)
Experimental
Control SiO2
Experimental
SiO2/HfSiONx
Asymmetric Stack
Simulated J-V curves
(A) (B)
58
Fig.3.5 Electrical leakage characteristics of a SiO2/HfSiON tunnel stack showing
improved slope in gate leakage characteristics. Black solid lines show simulations for a
SiO2 tunnel stack of same EOT.
Hence we attribute the improvement in J-V slope to defect passivation. However, when
other thicknesses are tried for same SiO2/HfSiON stack we do not see steepness (Fig. 3.6)
in the slope suggesting the importance of layer thickness which governs steepness as well.
Fig.3.6 Electrical leakage characteristics of a 2.5 nm SiO2/ 6.5 nm HfSiON tunnel stack
showing higher leakage at low voltages and non-steep J-V characteristics.
Hence, passivation of defects together with the right thicknesses is crucial for designing
an ideal engineered tunnel stack.
3.2.2 TANOS capacitors results
0 2 4 6 810
-10
10-5
100
V (V)
J (A/cm
2) Experimental
Simulation
of SiO2 stack
Of same EOT
0 2 4 6 810
-10
10-5
100
V (V)
J (A/cm
2) Experimental
0 2 4 6 810
-10
10-5
100
V (V)
J (A/cm
2) Experimental
Simulation
of SiO2 stack
Of same EOT
59
We now shift our focus to TANOS capacitors where we can directly see the impact of
engineered tunnel barriers on performance metrics like program/erase, retention. We
would also compare results for different high-k materials and also impose flash
constraints to see whether they can be implemented in reality.
Program/Erase and Retention
As mentioned earlier, program/erase in engineered tunnel stacks depend upon conduction
(CB) and valence band offset (VB). In Fig. 3.7 we show a cartoon showing the impact of
CB and VB. As we know, for HfO2, Si3N4 and SiO2 the CB offsets are in order
SiO2>Si3N4>HfO2 while the VB offsets follow SiO2> HfO2 > Si3N4. As per our
discussion in Chapter 1 and 2, we expect the programming efficiency to increase with
decreasing CB (easier electron injection) while the erase efficiency should also increase
with decreasing VB (easier hole injection). This is confirmed by experimental
program/erase (P/E) hysteresis measurement as shown in Fig. 3.8. Here we plot the flat
band voltage (VFB) shift vs. gate voltage for all these cases mentioned above. The
positive shift in VFB corresponds to program operation while the negative shift
corresponds to erase.
EraseErase
Si3N4∆Ev=-2.6V
Al2O3∆Ev=+.4V
Si
EraseErase
Si3N4∆Ev=-2.6V
Al2O3∆Ev=+.4V
Si
EraseErase
Si3N4∆Ev=-2.6V
Al2O3∆Ev=+.4V
Si
EraseErase
Si3N4∆Ev=-2.6V
Al2O3∆Ev=+.4V
Si
-1.1VAl
ProgramProgram
Si3N4∆Ec=
2O3∆Ec=-0.7V
Si
ProgramProgram
Si3N4∆Ec=
2O3∆Ec=-0.7V
Si
-1.1VAl
ProgramProgram
Si3N4∆Ec=
2O3∆Ec=-0.7V
Si
ProgramProgram
Si3N4∆Ec=
2O3∆Ec=-0.7V
Si
-1.1VAl
ProgramProgram
Si3N4∆Ec=
2O3∆Ec=-0.7V
Si
ProgramProgram
Si3N4∆Ec=
2O3∆Ec=-0.7V
Si
ProgramProgram
Si3N4∆Ec=
2O3∆Ec=-0.7V
Si
ProgramProgram
Si3N4∆Ec=
2O3∆Ec=-0.7V
Si
Program Erase
60
Fig. 3.7 Cartoon showing CB and VB offsets for Si3N4, Al2O3 and SiO2. The ease of
programming and erase is strongly governed by these.
Fig. 3.8 Program/Erase (P/E) window vs. gate voltage for standard SiO2 based TANOS
and its comparison with OHO and ONO based TANOS. Note that all stacks are of similar
EOT. All measurements are for TANOS capacitors. Positive shift in VFB corresponds to
program operation while the negative shift corresponds to erase.
P/E measurements confirm that engineered tunnel barriers do provide better program and
erase for the same gate voltage when compared to SiO2 of similar EOT. However, the
larger P/E window comes at the cost of poor retention as can be seen for ONO TANOS,
and is even worse for OHO (as seen in Fig. 3.9). Hence, the P/E vs. retention tradeoff
does exist for engineered barriers as well. Even though we are able to attain higher P/E
0 5 10 15 20-10
-5
0
5
10
12.4V
11.5 V
OHO 2nm/2nm/2nm CETox~4.7nm
ONO 1.5nm/1.5nm/1.5nm CETox~4.0nm
TANOS SiO2 Tox~4.0nm
∆V
fb=
Vfb-V
fb(n
eutr
al)
Absolute Value Program / Erase (V)
6.1V
61
window, we lose that benefit due to worse retention. Larger retention loss in OHO or
ONO may be attributed to traps in Hf(Si)O2 or Si3N4 dielectrics[3]. Also, experimentally
we can see that the layer thicknesses and band offsets are important levers to modulate
P/E.
Fig. 3.9 Charge loss during retention measurement (at 150 0C for 24 hours) for OHO,
ONO and SiO2. Use of engineered tunnel barriers is thus limited by faster retention loss.
3.2.3 TANOS flash memory transistor results
We fabricated flash memory transistors with OHO, OA, OAO, ONO engineered tunnel
stacks. We would like to compare the performance of all these stacks with SiO2 based
TANOS flash memory. Again we first compare program/erase performance for all these
stacks. Fig. 3.10 shows the Vth (threshold voltage shift) vs. program pulse time for all
stacks mentioned above.
0.1 1 10 100 1000 10000-100
-80
-60
-40
-20
0
%
Vfb
Ch
an
ge
Retention Time (s)
% Change OHO (CETox~4.7nm)
% Change ONO (CETox~4.0nm)
% Change TANOS (CETox~4.0nm)
62
Fig. 3.10 Delta Vth vs. program pulse time for different engineered tunnel stacks based
TANOS flash memory. A comparison can be seen with SiO2 based TANOS of similar
EOT at 17 V programming voltage.
We can observe that compared to SiO2; OA and OAO based flash memory show greater
threshold voltage shift (Vth) for the same program voltage and pulse time. Further, OHO
and ONO might have lesser Vth shift owing to trapping of electrons in them (this would
be confirmed later). Similarly the erase profile for all the same stacks can be seen in Fig.
3.11.
0
1
2
3
4
5
6
7
8
9
10
1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00
OA (36A EOT)
OAO (66A EOT)
SiO2 only (40A EOT)
OHO (40A EOT)
ONO (40A EOT)
ΔΔ ΔΔV
thp
rog
ram
(V
pr-
Vn
ati
ve)
Pulse time for 17V program voltage
0
1
2
3
4
5
6
7
8
9
10
1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00
OA (36A EOT)
OAO (66A EOT)
SiO2 only (40A EOT)
OHO (40A EOT)
ONO (40A EOT)
0
1
2
3
4
5
6
7
8
9
10
1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00
OA (36A EOT)
OAO (66A EOT)
SiO2 only (40A EOT)
OHO (40A EOT)
0
1
2
3
4
5
6
7
8
9
10
1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00
OA (36A EOT)
OAO (66A EOT)
SiO2 only (40A EOT)
OHO (40A EOT)
ONO (40A EOT)
ΔΔ ΔΔV
thp
rog
ram
(V
pr-
Vn
ati
ve)
Pulse time for 17V program voltage
63
Fig. 3.11 Erase profile for OHO, OA, OAO, ONO and SiO2 based TANOS flash memory
for -17 V erase voltage.
Once again we find that engineered barriers especially ONO (with lower VB offset) has
much better erase than SiO2 for similar EOT. This confirms that engineered barriers offer
better P/E over SiO2 tunnel oxide of same EOT. We also compare the endurance
characteristics for similar stacks. Endurance is the plot of Vth shift Vs. P/E cycles. The
plot is shown in Fig. 3.12. As discussed earlier, one of the major problems with scaling of
SiO2 is the issue of SILC (which occurs due to electrical stress). In the figure all the
stacks show degradation with P/E cycles. This implies that SILC is still an issue even
with engineered tunnel barriers. However, since P/E memory window is larger for
Pulse time for 17V Erase voltage
-180%
-160%
-140%
-120%
-100%
-80%
-60%
-40%
-20%
0%
1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01
OA (36A EOT)
OAO (66A EOT)
SiO2 only (40A EOT)
OHO (40A EOT)
ONO (40A EOT)% E
rase
fr
om
~6
V ∆∆ ∆∆
Vth
pro
gra
m
Pulse time for 17V Erase voltage
-180%
-160%
-140%
-120%
-100%
-80%
-60%
-40%
-20%
0%
1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01
OA (36A EOT)
OAO (66A EOT)
SiO2 only (40A EOT)
OHO (40A EOT)
ONO (40A EOT)% E
rase
fr
om
~6
V ∆∆ ∆∆
Vth
pro
gra
m
64
engineered stacks, window closure (merging of program and erase Vth) after 104 cycles is
not a big concern for these stacks.
Fig. 3.12 Endurance characteristics for ONO, OA and SiO2 stacks based TANOS flash
memory. The program/erase voltages are adjusted to produce similar P/E window. All
stacks show degradation.
We also examine the P/E vs. retention tradeoff which is a major impediment to tunnel
oxide memory scaling (discussed in detail in Chapter 1). Fig. 3.13 shows the P/E vs.
retention tradeoff for the stacks considered. Retention is measured for 24 hrs at 1500C
after programming the device. We see clearly that even though P/E offered by these
engineered stacks is superior to SiO2 of similar EOT, retention is poorer owing to defects
in these stacks. Hence the major problem of P/E vs. retention tradeoff does exist for
engineered tunnel stacks as well.
1.5
2
2.5
3
3.5
4
4.5
1 10 102 103 104
Cycles
Vth
(V)
1.5
2
2.5
3
3.5
4
4.5
1 10 102 103 104
Cycles
Vth
(V)
1.5
2
2.5
3
3.5
4
4.5
1 10 102 103 104
Cycles
Vth
(V)
65
Fig. 3.13 P/E for ONO, OA and SiO2 is shown on the left while retention (at 1500C for
24hrs) for the same tunnel oxide (TO) stacks is shown on the right. All stacks have
similar EOT.
We also show a comparison of retention measurements for different samples. Fig. 3.14
shows the bar graph of percentage charge lost for different high-k materials based flash
memory [4]. One can clearly see that when compared to engineered tunnel stacks, SiO2 of
a comparable EOT has much better retention at 1500C. Thus, we need to seek alternative
solutions to improve retention in these stacks.
1.E-1-200%
-150%
-100%
-50%
0%
1.E-6 1.E-5 1.E-4 1.E-3 1.E-2
Time (s)
% E
ras
e
1.E-1-200%
-150%
-100%
-50%
0%
1.E-6 1.E-5 1.E-4 1.E-3 1.E-2
Time (s)
% E
ras
e
-200%
-150%
-100%
-50%
0%
1.E-6 1.E-5 1.E-4 1.E-3 1.E-2
Time (s)
% E
ras
e1.E0
0
2
4
6
8
10
SiO2 only (40A EOT)
ONO (40A EOT)
OA (36A EOT)
1.E-6 1.E-5 1.E-4 1.E-3 1.E-2 1.E-1
Time (s)ΔΔ ΔΔ
Vth
pro
gra
m1.E0
0
2
4
6
8
10
SiO2 only (40A EOT)
ONO (40A EOT)
OA (36A EOT)
1.E-6 1.E-5 1.E-4 1.E-3 1.E-2 1.E-1
Time (s)ΔΔ ΔΔ
Vth
pro
gra
m
0
2
4
6
8
10
SiO2 only (40A EOT)
ONO (40A EOT)
OA (36A EOT)
1.E-6 1.E-5 1.E-4 1.E-3 1.E-2 1.E-1
Time (s)
0
2
4
6
8
10
SiO2 only (40A EOT)
ONO (40A EOT)
OA (36A EOT)0
2
4
6
8
10
SiO2 only (40A EOT)
ONO (40A EOT)
OA (36A EOT)
1.E-6 1.E-5 1.E-4 1.E-3 1.E-2 1.E-1
Time (s)ΔΔ ΔΔ
Vth
pro
gra
m
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
1
% C
ha
rge L
ost fr
om
~6
V ∆
Vt
SiO
2-T
O
ON
O B
E-T
O
OA
BE
-TO
TO-type0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
1
% C
ha
rge L
ost fr
om
~6
V ∆
Vt
SiO
2-T
O
ON
O
TO
OA
TO
TO-type0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
10%
2%
4%
6%
8%
10%
12%
14%
16%
18%
1
% C
ha
rge L
ost fr
om
~6
V ∆
Vt
SiO
2-T
O
ON
O B
E-T
O
OA
BE
-TO
TO-type0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
10%
2%
4%
6%
8%
10%
12%
14%
16%
18%
1
% C
ha
rge L
ost fr
om
~6
V ∆
Vt
SiO
2-T
O
ON
O
TO
OA
TO
TO-type
66
Fig. 3.14 Retention as fractional charge lost from a 4V ∆Vth program after 24 hours at
150 0C (open bars) and Effective +/-17V P/E window in volts (grey bars) comparing OA,
OAO, ONO, OHO with SiO2 (with approximate tunnel oxide EOT listed). Over 400%
P/E window improvement realized using OA, and >300% improvement for ONO vs.
SiO2 [4].
3.3 Summary of Results
In this section, we summarize the key results. Following are the major ones:
• MOS capacitor results show that high leakage at lower voltages is a big concern
for implementing engineered tunnel barrier based flash memory.
• High leakage is attributed to traps at the interfaces and in the bulk.
• Experiments for MOS capacitors and transistors were performed for SiO2, OA,
OAO, OHO and ONO.
67
• OA and OAO engineered tunnel stacks show higher delta Vth (for both program
and erase) compared to SiO2 stack for similar EOT.
• Endurance results for engineered barriers show both P/E degradation with cycles
>104. This strongly suggests that SILC still exists for engineered barriers as well.
• P/E vs. retention tradeoff was also investigated. Experimental results show great
P/E but poor retention confirming the tradeoff discussed earlier.
In next chapter, we will look at solutions to both SILC and P/E vs. retention tradeoff. We
will then look into experimental design and setup.
3.4 References
[1] S Verma, E Pop, P Kapur, P Majhi, K Parat, K. C. Saraswat, “Feasibility Study of
Composite Dielectric Tunnel Barriers for Flash Memory”, IEEE Device Research
Conference, South Bend, Indiana, 2007
[2] M. H. Zhang, F. Zhu, H. S. Kim, I. J. Ok, and J. C. LeeFluorine “ Passivation in Gate
Stacks of Poly-Si/TaN/HfO2 (and HfSiON/HfO2)/Si through Gate Ion Implantation”,
IEEE Electron Device Letters, vol. 28, N0. 3, March 2007.
[3] S.Verma, G. Bersuker, D. Gilmer, A. Padovani, H. Park, A. Nainani, D. Heh, J.
Huang, K. Parat, J. Jiang, P. D. Kirsch, L. Larcher, H. H. Tseng, K. C. Saraswat and R.
Jammy, “A Novel Fluorine Incorporated Band engineered (BE) Tunnel (SiO2/ HfSiO /
SiO2) TANOS with excellent Program/Erase and Endurance to 105 cycles”, IEEE
International Memory Workshop, Monterey, 2009
68
[4] D. C. Gilmer, N. Goel, S. Verma, H. Park, C. Park, G. Bersuker, P. D. Kirsch, K.C.
Saraswat and R. Jammy, “Band Engineered Tunnel Oxides for Improved TANOS-type
Flash Program/Erase with Good Retention and 100K Cycle Endurance:, IEEE VLSI
Symposium-Tech, Systems and Applications, Taiwan, 2009
69
Chapter 4
Fluorination
As discussed in previous chapters, both SILC and P/E vs. retention tradeoff are
impediments to implementation and scaling of engineered tunnel barriers. In this chapter
we propose two distinct solutions and look at one of the specific solution in detail. In the
next chapter, we look at the other solution.
4.1 Proposed solutions
There are two ways to fix the problem of high leakage and SILC in engineered tunnel
barriers. They are:
� Passivation of defects/traps in high-k dielectric resulting in lower leakage and
improved flash memory performance characteristics
� Designing novel tunnel barrier structure and incorporating novel materials to
implement scaling.
In this chapter we will focus on the first solution and look into how passivation of defects
indeed improves performance. For this purpose, fluorine is incorporated in the engineered
tunnel stack for the first time.
70
4.2 Motivation for incorporating fluorine as a defect
passivant
There are several reasons why fluorine is an attractive candidate for passivating
interface traps. First of all, fluorine is known to be the most electronegative (~4.0
Pauling) and thus a reactive element in the periodic table [1]. This means that it may
form a strong bond with any defective bond in the high-k stack. Also, fluorine has a
smaller ionic radius (~50 pm) compared to other reactive elements in the same column of
the periodic table such as Cl (~100 pm) or Br (~115 pm) [2], which may enable itself to
diffuse easily through high-k stacks and effectively passivate defective bonds. In
addition, fluorine is not a completely new element in the semiconductor community. It
has been shown by several research groups that the introduction of fluorine at the SiO2/Si
interface improves reliability in the standard poly-Si gate/SiO2(SiON)/Si system [3,4].
Finally, fluorine is particularly promising in high-k dielectric stacks with metal gates,
because it may not suffer from the known problems of excess fluorine in SiO2/Si with
poly Si gate, such as enhanced boron penetration through SiO2 from P+ poly-silicon gate
to substrate [5] and an increase in the physical thickness of SiO2 [6]. More recently,
fluorine has been shown to passivate defect in HfO2 and other high-k dielectrics as well
[7,8, 9,10,11].
4.3 Experimental design to incorporate fluorine
71
MOS-capacitors were fabricated with both SiO2/HfO2/SiO2 (OHO) and SiO2/Al2O3 (O/A)
dielectric stacks. The TANOS capacitor stacks (Fig. 4.1) were fabricated using OHO
tunnel stacks with a conventional SiN (~6nm) charge trap layer, Al2O3 (~11nm) blocking
layer and TaN metal gate. Fluorine ion implantation (Fii) was performed at different
stages of processing. The place of fluorine implant is referred as position 1, 2 or 3 in the
figure. Position 1 refers to fluorine implant in the Si substrate, position 2 refers to implant
in the bottom SiO2 (as shown in the figure) while position 3 illustrates implant in the top
SiO2 of the engineered tunnel barrier. Dopant activation was done with a 1020°C spike
anneal and the process was finished with 400°C forming gas anneal (FGA). In the table
(see Fig. 4.1), we also show the gamut of engineered tunnel barriers considered for our
experiments. Also mentioned, are the thicknesses of these layers. In most cases, the
thickness of bottom SiO2 was kept to be around ~2 nm for optimal performance.
Fig. 4.1 a) Schematic showing TANOS flash memory and position of implant. The
position of implant is referred with numbers 1, 2 or 3 b) shows the samples considered
for our experiments. Samples are compared with/without fluorine implant. The
Silicon(100)
SiO2
HfSiO
SiO2
60 A Si3N4
110A Al2O3
TaN electrode
[1]
[3]
[2]
F
FF
Silicon(100)
SiO2
HfSiO
SiO2
60 A Si3N4
110A Al2O3
TaN electrode
[1]
[3]
[2]
F
FF
No Implant20 A SiO2/35 A HfSiO/ 40 A SiO
2 (S10)(S10)
[3]20 A SiO2/35 A HfSiO/ 40 A SiO
2 (S9)(S9)
[2]20 A SiO2/35 A HfSiO/ 40 A SiO2 (S8)(S8)
TANOS Transistors
No Implant20 A SiO2/30 A HfO2/ 20 A SiO2 (S7)(S7)
[3]20 A SiO2/30 A HfO2/ 20 A SiO2 (S6)(S6)
[2]20 A SiO2/ 30 A HfO2/ 20 A SiO2 (S5)(S5)
TANOS MOSCAP
[1] / No implant20A SiO2/15A HfO2/ 20A SiO2 (S3/ S4)(S3/ S4)
[1]/ No implant20 A SiO2/35 A Al2O3 (S1/S2)(S1/S2)
MOSCAP
Fluorine Incorporation
position in BE-tunnel stack
Dielectric Stack
(thicknesses in Angstroms)
No Implant20 A SiO2/35 A HfSiO/ 40 A SiO
2 (S10)(S10)
[3]20 A SiO2/35 A HfSiO/ 40 A SiO
2 (S9)(S9)
[2]20 A SiO2/35 A HfSiO/ 40 A SiO2 (S8)(S8)
TANOS Transistors
No Implant20 A SiO2/30 A HfO2/ 20 A SiO2 (S7)(S7)
[3]20 A SiO2/30 A HfO2/ 20 A SiO2 (S6)(S6)
[2]20 A SiO2/ 30 A HfO2/ 20 A SiO2 (S5)(S5)
TANOS MOSCAP
[1] / No implant20A SiO2/15A HfO2/ 20A SiO2 (S3/ S4)(S3/ S4)
[1]/ No implant20 A SiO2/35 A Al2O3 (S1/S2)(S1/S2)
MOSCAP
Fluorine Incorporation
position in BE-tunnel stack
Dielectric Stack
(thicknesses in Angstroms)
72
thicknesses of these layers are mentioned in the bracket along side the stack. All samples
are assigned label as “S#”
The dose and energy of fluorine implant was ascertained after SRIM simulations [12].
Figure 4.2 shows a representative case of SRIM simulations [12] which helped in
deciding the dose and the energy of the F implant. We found that 1KeV implant with a
dose of 1015/cm2 was ideal for such thicknesses. The target of the implant was Si/SiO2
interface. Following the implant and after deposition of other layers a thermal anneal was
performed to activate the dopants. This resulted in diffusion of F atoms across the entire
stack (will be shown later).
Fig. 4.2 a) SRIM simulations for 13KeV,1015/cm2 F implant in the poly-Si cap on top of
the gate. b) Shows the same for a 1KeV, 1015/cm2 implant in TiN gate for a SiO2/HfO2
based MOScap. Similar simulations were done for TANOS flash stacks to ascertain the
dose and energy of the F implant.
4.4 Electrical Results
73
Constant current measurements were performed to see the impact of Fii incorporation on
breakdown of the OHO and OA dielectric stacks in MOS capacitors. The Fii OHO and
Fii OA stacks, with total charge to breakdown (Qbd) of ~1000 and ~600 C/cm2
respectively, both show higher immunity to breakdown vs. non-Fii stacks with Qbd of
~100 and ~200 C/cm2 respectively. The constant current applied was of ~105 A/cm2. In
Fig. 4.3 we can see the voltage vs. stress time plot for a constant current measurement.
When compared to Fii samples, no-Fii OA and OHO samples show lower charge to
breakdown. In case of OHO samples, the difference between with/without fluorine are
roughly an order suggesting greater immunity against breakdown for Fii samples. OA
samples with fluorine also show higher Qbd but the difference is limited to roughly three
times. As discussed earlier, flash memory uses high voltage (~17 V) on the control gate,
hence a greater immunity to charge breakdown is crucial for better reliability of the
device. A sample of more than 30 observations was collected to roughly estimate these
numbers.
O/H/O
O/A+Fii
+Fii
O/H/O
O/A+Fii
+Fii
~200~600SiO2 /Al2O3
SiO2 /HfO2/ SiO2
Qbd (C/cm2)
~100~1000
No FiiFii
~200~600SiO2 /Al2O3
SiO2 /HfO2/ SiO2
Qbd (C/cm2)
~100~1000
No FiiFii
Si(100)
SiO2
HfO2SiO2
TaN
Si(100)
SiO2
HfO2SiO2
TaN
Si(100)
SiO2
Al2O3
TaN
Si(100)
SiO2
Al2O3
TaN
74
Fig. 4.3 (Left) Plot showing voltage vs. stress time for constant current measurement (for
OHO and OA MOS capacitors). The table shows the estimated Qbd for these samples
with/without fluorine. The bottom right cartoon shows the schematic for the MOS
capacitor structure.
We now move to TANOS capacitors and look at capacitance-voltage (C-V)
measurements to see the impact of fluorine. The normalized C-V curves for a voltage
sweep of 0-17V for with/without fluorine OHO TANOS capacitor samples are shown in
Fig. 4.4. As can be seen clearly the Fii sample shows a steeper C-V slope when compared
to no Fii OHO sample. This may be attributed to passivation of defects either in the bulk
or at the interface. To confirm defect passivation with fluorine implant, Dit measurements
were performed using charge pumping under a negative stress of -17V similar to flash
operating voltage. The results shown in the table in Fig. 4.4 confirm lower interface
defects at Si/SiO2 interface. Further, we see reduced interface states for Fii samples for
both pre and post stress case. In addition, in Fig. 4.5 we look at an additional case where
fluorine is implanted in the top SiO2 of the engineered tunnel barrier (position 3, sample
S6). Here we compare the C-V hysteresis (representing program/erase) for all three cases.
Once again, the Fii samples show a steeper, accumulation C-V slope vs. non-Fii.
However, for the case where fluorine is implanted in the bottom SiO2 (position 2,
samples S5), we achieve the steepest accumulation C-V slope (S5 vs. S6). However,
reduced Cox and a flat band shift for Fii sample (S5) suggests that Fii introduces negative
charges in the tunnel stack while also impacting the k value (dielectric constant) of
bottom SiO2.
75
Fig. 4.4 (Left) C-V sweeps from 0-17 V for an OHO TANOS capacitor with/without
fluorine incorporation. It can be clearly observed that Fii samples have a steeper C-V
slope suggesting passivation of interface defects. (right) Shows Dit measurements for
OHO transistors with/without fluorine. For both pre and post stress case, reduction in
interface defects is clearly observed.
This improved C-V behavior for Fii at high bias (+/- 17V) is not readily observed at low
bias (+/- 5V) suggesting Fii passivation prevented defect generation at Si/SiO2 interface
during stress. TANOS transistors were also fabricated with/without Fii incorporated
OHO tunnel stack. Again samples S8 (fluorine implant in bottom SiO2, position 2), S9
(implant in top SiO2, position 3), S10 (no implant) are compared. Excellent P/E
characteristics with larger P/E window at similar electric fields for Fii samples (S8, S9)
vs. non-Fii (S10) are shown in Fig.4.6 (a) and Fig. 4.6(b) respectively. However, initial
programming for non-Fii OHO (S10) occurs more rapidly suggesting filling up of
shallow traps in the high-k dielectric [13], while Fii seems to passivate those shallow
defects resulting in lower initial Vth shift.
0.35
0.45
0.55
0.65
0.75
0.85
0.95
1.05
0 3 6 9 12 15Voltage (V)
Norm
alized C
apacitan
ce(F
)
No Fluorine
Fluorine
IncreasingFluorine Impact
17 V
0.35
0.45
0.55
0.65
0.75
0.85
0.95
1.05
0 3 6 9 12 15Voltage (V)
Norm
alized C
apacitan
ce(F
)
No Fluorine
Fluorine
IncreasingFluorine Impact
17 V
Post
Stress
Pre-Stress
Dit
(cm2eV-1)
-17V stress
(5000s)
2.4e113.6e10
2.4e125e10
No-FiiFii
Post
Stress
Pre-Stress
Dit
(cm2eV-1)
-17V stress
(5000s)
2.4e113.6e10
2.4e125e10
No-FiiFii
76
Fig. 4.5 C-V hysteresis for three OHO TANOS capacitors for three different cases.
Samples S5 (fluorine implant in position 2), S6 (implant in position 3) and S7 (no
fluorine) have been compared for this plot. The hysteresis is observed at +/-17V
program/erase.
Cox
lowering
20
25
30
35
40
45
50
55
-20 -10 0 10 20Voltage (V)
Ca
pa
cit
an
ce (
pF
)
O/H/O(S5) Fii
O/H/O(S6) Fii
O/H/O(S7)No-Fii
+Fii
Erase
Program
Cox loweringCox
lowering
20
25
30
35
40
45
50
55
-20 -10 0 10 20Voltage (V)
Ca
pa
cit
an
ce (
pF
)
O/H/O(S5) Fii
O/H/O(S6) Fii
O/H/O(S7)No-Fii
+Fii
Erase
Program
Cox lowering
11 V
17V
0
1
2
3
4
5
6
7
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1Program Pulse Time (s)
Delt
a V
th(V
)
20 A SiO2/ 35 A HfSiO/ 40 A SiO2 (Fii, S8)20 A SiO2/ 35 A HfSiO/ 40 A SiO2 (Fii, S9)20 A SiO2/ 35 A HfSiO/ 40 A SiO2 (No-Fii, S10)41 A SiO2
11 V
17V
11 V
17V
0
1
2
3
4
5
6
7
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1Program Pulse Time (s)
Delt
a V
th(V
)
20 A SiO2/ 35 A HfSiO/ 40 A SiO2 (Fii, S8)20 A SiO2/ 35 A HfSiO/ 40 A SiO2 (Fii, S9)20 A SiO2/ 35 A HfSiO/ 40 A SiO2 (No-Fii, S10)41 A SiO2
11 V
17V
11 V
17V
0
1
2
3
4
5
6
7
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1Program Pulse Time (s)
Delt
a V
th(V
)
20 A SiO2/ 35 A HfSiO/ 40 A SiO2 (Fii, S8)20 A SiO2/ 35 A HfSiO/ 40 A SiO2 (Fii, S9)20 A SiO2/ 35 A HfSiO/ 40 A SiO2 (No-Fii, S10)41 A SiO2
11 V
17V
11 V
17V
(A)
77
Fig. 4.6 a) Delta Vth shift during program operation (for 11V and 17V) for three cases of
S8 (implant in position 2), S9 (implant in position3) and S10 (no implant) are shown. . A
comparison with conventional SiO2 based TANOS is also shown. b) Percent charge
erased from the flash memory as a function of erase pulse time at -17V erase voltage.
Note that all samples had similar initial Vth.
Further, a lower dielectric constant of bottom SiO2 in Fii sample (S8) results in higher
electric field drop across bottom SiO2 causing higher electron injection and hence
improved programming (and erase) for the same total field across the sample. Erase
behavior for OHO samples are also better than standard SiO2 due to a more favorable
band engineered tunnel structure.
4.5 Endurance and Retention
SILC and retention loss are severe problems for engineered tunnel barriers. However,
before we look into performance of fluorine incorporated stacks, we need to understand
endurance in greater detail. As mentioned before, endurance is the Vth shift vs. program /
-200%
-170%
-140%
-110%
-80%
-50%
-20%
10%
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1Pulse Time (s)
Era
se
(%
)
20A SiO2/ 35A HfSiO/ 40A SiO2 (Fii, S8)
20A SiO2/ 35A HfSiO/ 40A SiO2 (Fii, S9)
20A SiO2/ 35A HfSiO/ 40A SiO2 (No-Fii, S10)
41A SiO2-200%
-170%
-140%
-110%
-80%
-50%
-20%
10%
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1Pulse Time (s)
Era
se
(%
)
20A SiO2/ 35A HfSiO/ 40A SiO2 (Fii, S8)
20A SiO2/ 35A HfSiO/ 40A SiO2 (Fii, S9)
20A SiO2/ 35A HfSiO/ 40A SiO2 (No-Fii, S10)
41A SiO2
(B)
78
erase (P/E) cycles for specific program/erase voltages and pulse times. It is well known
that during endurance for P/E cycles greater than 104, the program and erase Vth merge
(also known as window closure). Part of the reason for this is known to be defect
generation at Si/SiO2 interface [14]. However, it is not clear whether this defect
generation process occurs during erase or program operation. This understanding is
critical to understand the defect generation mechanism. In Fig. 4.7 we measure Dit by
charge pumping method under both program and erase operation. This is done for
different electric fields (or different program/erase voltages) for SiO2 based TANOS flash
memory. We can clearly see that no interface defects are seen to be generated during
program operation. However, for the same case, Dit generation is seen under erase
operation. According to anode hole injection model [15], holes are responsible for
degradation during negative bias (on the gate). Since erase operation is primarily hole
injection from substrate we think that holes play a crucial role in defect generation and
interface degradation. We now look at endurance performance for fluorine incorporated
engineered tunnel barriers. We observe excellent endurance (to 105 cycles) is for Fii
OHO samples (vs. non-Fii) as seen in Fig. 4.8(a).
10
-710
-610
-510
-410
-310
-20
4
8
12
16
20
24
28
Time [sec]
10.5MV/cm
12.0MV/cm
13.5MV/cm
Dit
[[ [[1
01
0/e
Vcm
2]] ]]
nFET
Dit generation during program
10-7
10-6
10-5
10-4
10-3
10-2
10-1
100
101
0
4
8
12
16
20
24
28 nFET
pCAP
Dit
[[ [[1
01
0/e
Vc
m2]] ]]
Time [sec]
-10.5MV/cm
-11.8MV/cm
-13.2MV/cm
Dit generation during erase
79
Fig. 4.7 (Left) Interface defect density (Dit) measurement for SiO2 TANOS (using charge
pumping) for three different electric fields. No Dit increase is seen. (right) Interface
defect density measurement under erase operation for different electric fields for the same
case of SiO2 TANOS.
For two different cases of fluorine implant, sample S8 (implant in bottom SiO2, position
2) and sample S9 (implant in top SiO2, position 3), we find that endurance is better for
bottom SiO2 implanted stack. Fii OHO samples may show greater resistance to hole
trapping and hence improved endurance vs. non-Fii. The Si-F bond is 2x stronger vs. Si-
H explaining hole degradation immunity for Fii samples [3]. However, in absence of
fluorine, hole trapping is observed for OHO TANOS resulting in poor endurance.
Fluorine was also incorporated for other stacks as well. Fig. 4.8 (b) shows the endurance
performance for SiO2 and OA stacks. With Fii, SiO2 stacks show much better endurance
when compared to the case with no Fii. OA stacks do not show appreciable difference
for with/without fluorine. In essence, fluorine does improve endurance by reducing
defects at interface.
-1
0
1
2
3
4
5
1 100 10000Cycles
Vth
(V)
Fii- Bottom SiO2 Fii-Top SiO2 No Fii
0
1
2
3
4
5
6
7
8
9
1 10 102 103 104 105
Cycles
Vth
(V)
45 A SiO2 (Fii)40.6 A SiO2 (No-Fii)O/A (Fii)O/A(No-Fii)
SiO2
O/A
Fii
Fii
Fii
SiO2
O/A
Fii
Fii
Fii
0
1
2
3
4
5
6
7
8
9
1 10 102 103 104 105
Cycles
Vth
(V)
45 A SiO2 (Fii)40.6 A SiO2 (No-Fii)O/A (Fii)O/A(No-Fii)
SiO2
O/A
Fii
Fii
Fii
SiO2
O/A
Fii
Fii
Fii
80
Fig. 4.8 (Left) Endurance performance for OHO engineered tunnel stack based TANOS
flash memory. Three different cases of fluorine implant are considered for comparison.
Hole trapping is seen in no-Fii case which improves dramatically with fluorine implant.
(right) Shows endurance for SiO2 and OA based TANOS flash memory. Significant
difference is seen in endurance for SiO2 stack with/without fluorine.
Impact of fluorine on retention was also considered. This was studied for OHO
engineered tunnel stack. Again with/with fluorine cases were considered for comparison.
Fig. 4.9 (Left) Retention characteristics (at 1500C for 24 hours) for OHO tunnel stacks
based TANOS for three different cases of fluorine implant. Instant charge loss behavior is
observed for the no fluorine case. (right) Instant charge loss behavior for no fluorine case
is studied as a function of retention temperature. It is observed that this behavior is
independent of temperature suggesting leakage through shallow traps in engineered
stacks.
Fig. 4.9 shows the retention characteristics at 1500C of OHO engineered tunnel stack
with/without fluorine. Retention is measured after programming these stacks for a change
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
1 10 100 1000 10000Time (s)
Vth
(V
)
25 C (O/H/O No Fii)
50 C (O/H/O No Fii)
75 C (O/H/O No Fii)
100 C (O/H/O No Fii)
150 C (O/H/O No Fii)
0
1
2
3
4
5
6
1 10 100 1000 10000 100000Time (s)
Vth
(V
)
Fii-Top SiO2
No FiiFii-Bottom SiO2
81
in Vth of 5V. With absence of fluorine, an instant charge loss behavior is seen. When
fluorine is incorporated this behavior is not observed suggesting passivation of defects.
To understand this charge loss behavior, retention was studied as a function of different
temperatures. We observe that this charge loss behavior is temperature independent (Fig.
4.9) and possibly due to shallow bulk traps in the engineered tunnel stack. This also
supports the fast programming behavior in Fig. 4.6(a) for non-Fii OHO TANOS which
was attributed to shallow traps. Thus, Fii passivates these shallow traps during retention.
Fig. 4.10 Number of Interface states (Nit) as a function of retention time for OHO
TANOS. With fluorine, samples show lower Niti when compared to no fluorine samples.
Furthermore, fluorine (Fig. 4.10) is also seen to reduce number of interface
defects (Nit) during retention. This observation confirms the results of [16]. We measured
Nit by charge pumping measurements (as a function of retention time) for OHO TANOS.
Samples with/without fluorine were used for comparison. Results show reduced Nit for
fluorine incorporated samples.
1E+10
2E+10
3E+10
4E+10
5E+10
6E+10
7E+10
8E+10
9E+10
1 10 100 1000 10000Retention Time (s)
Nit
(#/c
m2)
20A SiO2/35A HfSiO/ 40A SiO2 (Fii, S8)
20A SiO2/35A HfSiO/ 40A SiO2 (No-Fii, S10)
1E+10
2E+10
3E+10
4E+10
5E+10
6E+10
7E+10
8E+10
9E+10
1 10 100 1000 10000Retention Time (s)
Nit
(#/c
m2)
20A SiO2/35A HfSiO/ 40A SiO2 (Fii, S8)
20A SiO2/35A HfSiO/ 40A SiO2 (No-Fii, S10)
1E+10
2E+10
3E+10
4E+10
5E+10
6E+10
7E+10
8E+10
9E+10
1 10 100 1000 10000Retention Time (s)
Nit
(#/c
m2)
20A SiO2/35A HfSiO/ 40A SiO2 (Fii, S8)
20A SiO2/35A HfSiO/ 40A SiO2 (No-Fii, S10)
1E+10
2E+10
3E+10
4E+10
5E+10
6E+10
7E+10
8E+10
9E+10
1 10 100 1000 10000Retention Time (s)
Nit
(#/c
m2)
20A SiO2/35A HfSiO/ 40A SiO2 (Fii, S8)
20A SiO2/35A HfSiO/ 40A SiO2 (No-Fii, S10)
82
4.6 Physical Characterization
Having seen the positive impact of fluorine on retention and endurance, we now want to
understand where fluorine diffuses to and what role does it play? We look at several
physical characterization techniques as mentioned below in detail:
Secondary Ion Mass Spectroscopy (SIMS):
We look at SIMS to locate the presence of fluorine. Fig. 4.11 shows the SIMS profile of
different elements including fluorine after implant in bottom SiO2 (position 2) of the
engineered tunnel stack of OHO TANOS. Fluorine is seen to peak near the bottom
Si/SiO2 interface suggesting its role in passivating interface traps. Another peak of
fluorine is also observed at top SiO2/Si3N4 interface. It is well known that fluorine does
not diffuse through silicon nitride easily [17] and hence piles up at that interface. We also
compare SIMS profile of two different cases, one where fluorine is implanted in top SiO2
of the engineered tunnel stack (position 3) and other where fluorine is implanted in
bottom SiO2 of the engineered tunnel layer (position 2). This is shown in Fig. 4.12.
HfSiOSiSi \SiO2 SiO2\SiN
Hf
F
Si
O
Si+N
1E+16
1E+17
1E+18
1E+19
1E+20
1E+21
1E+22
65 85
Depth (nm)
F C
oncentr
ation
(ato
ms/c
m3)
F18O29SiSi+NHf+O2
BACK-SIDE SIMS
Si/SiO2 Top SiO2/SiNHfSiOSiSi \SiO2 SiO2\SiN
Hf
F
Si
O
Si+N
1E+16
1E+17
1E+18
1E+19
1E+20
1E+21
1E+22
65 85
Depth (nm)
F C
oncentr
ation
(ato
ms/c
m3)
F18O29SiSi+NHf+O2
BACK-SIDE SIMS
Si/SiO2 Top SiO2/SiN
83
Fig. 4.11 Backside SIMS profile for fluorine implanted OHO TANOS. Fluorine was
implanted in the bottom SiO2 of the engineered tunnel stack.
Fig. 4.12 (a) SIMS profile for fluorine implanted in bottom SiO2 of the engineered tunnel
stack of OHO TANOS. (b) SIMS profile for fluorine implanted in top SiO2 of the
engineered tunnel stack of OHO TANOS of similar EOT. In both cases, fluorine profile
is represented by solid black line.
There are two important observations worth noting:
• When fluorine is implanted in bottom SiO2 it peaks close to Si/bottom SiO2
interface while when implanted in top SiO2 of the engineered tunnel stack, it
peaks close to top SiO2/SiN interface. In both SIMS, it is observed that fluorine
has two distinct peaks corresponding to Si/bottom SiO2 and top SiO2/SiN
interface.
• Concentration of fluorine is much higher at Si/bottom SiO2 interface when
fluorine is implanted in bottom SiO2. With higher concentration of fluorine, better
(A) Implant in Bottom SiO2 (B) Implant in Top SiO2(A) Implant in Bottom SiO2 (B) Implant in Top SiO2
84
passivation is possible. This is consistent with better endurance performance
observed for the OHO TANOS where fluorine was implanted in bottom SiO2 of
the engineered tunnel stack.
XPS (X-ray Photoelectron Spectroscopy):
To understand the role of fluorine in HfO2, synchrotron XPS measurements were
performed across the OHO film (these measurements were done at Brookhaven National
Lab in collaboration with SEMATECH). First note in Fig. 4.13(a), O 1s spectra for non-
Fii OHO shows a clearer signature of stoichiometric HfO2 in contrast to the Fii film. This
O 1s XPS spectra difference for Fii HfO2 could be attributed to fluorine occupying
oxygen vacancies to form bonds with Hf metal [11]. The entire HfO2 film was probed by
looking at different Hf spectra lines. Hf 4f lines (which mostly reflect the chemical
behavior of the bulk HfO2 film) show a shift towards higher binding energy (lower
kinetic energy) (Fig. 4.13(b)). This shift is consistent with earlier reported results [18]
and is attributed to HfO2 defect passivation by fluorine. Similar shifts were also seen for
core lines (Fig. 4.13(c,d)) Hf 4d and Hf 3d (and mostly reflect the chemical behavior of
upper surface of the HfO2 film). All these shifts are consistent with fluorine incorporation
leading to higher binding energy or stronger bonds. These shifts indicate F migration into
the HfO2 layer during the device thermal processing and modifying the Hf bonding
environment.
Spectroscopic Ellipsometry:
To understand the role of fluorine at Si/SiO2 interface, spectroscopic ellipsometry
measurements were performed [19]. Specifically, we investigated an optically active
85
feature that is associated with oxygen vacancy defects at the Si/SiO2 interface [20]. This
intrinsic interfacial defect feature is located at 2.9 eV in the absorption spectra (ε2) and
demonstrates sensitivity towards changes in the Si/SiO2 interface defect density with a
corresponding change in its amplitude. Notice that ε2 is the imaginary part of the
dielectric function. Fig. 4.14(a) illustrates a reduction of the 2.9 eV peak’s amplitude with
Fii, suggesting that the density of oxygen vacancy related defects at the Si/SiO2 interface
has been minimized. Similar reduction of this optically active feature is obtained for
hydrogen passivation of dangling bonds by forming gas anneal as observed in Fig.
4.14(b).
Fig. 4.13 Synchrotron XPS measurements for OHO films with F implant in the bottom
SiO2. a) Shows O 1s spectra for Fii/ non-Fii OHO film. A clearer signature of HfO2 is
532 536 540 5440
3000
6000
9000
Inte
nsity (
a.u
.)
Kinetic Energy (eV)
NoFluorine
FluorineHf 3d5/2
Surface
SensitiveHf-F
1664 1668 16720
30000
60000
90000
Inte
nsity (
a.u
.)
Kinetic Energy (eV)
NoFluorine
FluorineO 1s
SiO2
HfO2
Hf-F
1664 1668 16720
30000
60000
90000
Inte
nsity (
a.u
.)
Kinetic Energy (eV)
NoFluorine
FluorineO 1s
Hf-F
2176 2180 2184
0
3000
6000
Inte
nsity (
a.u
.)
Kinetic Energy (eV)
NoFluorine
FluorineHf 4f
Bulk Sensitive
Hf-F
86
seen for non-Fii film. b) Shows shift in Hf 4f lines due to Fii relative to the control non-
Fii sample. (c) and (d) shows similar shifts in Hf 4d and Hf 3d core lines for Fii vs. non-
Fii samples. In all cases, the spectra shifts towards higher binding energy for the Fii
samples relative to non-Fii.
Fig.4.14 a) Spectroscopic ellipsometry measurements show that Fii in HfO2 reduces
interfacial defect density. b) Shows the same effect in SiO2 with forming gas anneal.
4.7 Model for explaining fluorine’s role
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
2 2.5 3 3.5 4 4.5 5
Photon Energy (eV)
εε εε22 22
SiO2 SiO2+FGA(B)
Interfacial
Defect
Feature
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
2 2.5 3 3.5 4 4.5 5
Photon Energy (eV)
εε εε22 22
SiO2 SiO2+FGA(B)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
2 2.5 3 3.5 4 4.5 5
Photon Energy (eV)
εε εε22 22
SiO2 SiO2+FGA(B)
Interfacial
Defect
Feature
0
0.05
0.1
0.15
0.2
0.25
2.5 3 3.5 4 4.5Photon Energy (eV)
εε εε22 22
HfO2 HfO2 + F Implant
Interfacial
Defect FeatureSi substrate
Related feature
(A)
0
0.05
0.1
0.15
0.2
0.25
2.5 3 3.5 4 4.5Photon Energy (eV)
εε εε22 22
HfO2 HfO2 + F Implant
Interfacial
Defect FeatureSi substrate
Related feature
0
0.05
0.1
0.15
0.2
0.25
2.5 3 3.5 4 4.5Photon Energy (eV)
εε εε22 22
HfO2 HfO2 + F Implant
Interfacial
Defect FeatureSi substrate
Related feature
(A)
87
After looking at both electrical and physical characterization results, we now propose a
model to explain the role of fluorine (Fig. 4.15).
When fluorine is implanted, it diffuses everywhere after forming gas anneal. Fluorine is
well known to segregate at interfaces [21] and is also observed to peak at interfaces (as
confirmed by SIMS measurement). During diffusion of fluorine, we think it forms bonds
with Si at interfaces and with Hf in the bulk of high-k materials (see Fig. 4.15). This is
confirmed by various electrical and physical characterization results. As observed,
fluorine improves Si/bottom SiO2 interface and reduces interface defect density (as
confirmed by Spectroscopic ellipsometry measurements and charge pumping
measurements as well). Further, Si-F bonds are 2X stronger than Si-H bonds (see table in
Fig. 4.15). As a result, stronger bonds are expected to provide immunity against hole
degradation during electrical stress. This is reflected and confirmed by improved
endurance results. Further, we observe improvement in retention due to passivation of
shallow traps in bulk HfO2. This was also suggested by XPS results where the shift in Hf
spectra towards higher binding energy reflected stronger bond formation in the bulk.
Fluorine might also passivate SiO2/HfO2 interface (as suggested by [22]), however it is
difficult to verify it using experimental results.
In a nutshell, fluorine diffuses in and passivates both Si/SiO2 defects and bulk high-k
traps as well. As a result, we observe improvement in both retention and endurance.
88
Fig. 4.15 Model showing diffusion of fluorine through engineered tunnel layers and
passivation of interfaces and bulk traps. Table on the right shows bond enthalpies for
relevant bonds formed during fluorine diffusion [23].
4.8 References
[1] L Pauling, The Nature of The Chemical Bond, 3rd ed., Cornell Univ. Press. Ithaca,
NY, 1960.
[2] www.webelements.com
[3] P. Wright and K. C. Saraswat, "The Effect of Fluorine in Silicon Dioxide Gate
Dielectric," IEEE Transactions on Electron Devices, vol. 36, pp. 879~905, 1989.
[4] T. B. Hook, E. Adler, F. Guarin, J. Lukaitis, N. Rovedo, and K. Schruefer, “The
effects of fluorine on parametrics and reliability in a 0.18-µm 3.5/6.8 nm dual gate oxide
CMOS technology”, IEEE Trans. Elect. Dev. 48, vol. 48,1346 (2001).
HfO2
Hf-F
F-Si
Hf-F
F-Si
Hf-F
F-Si
F-Si
F-Si
F
F
SiO2
HfO2
Hf-F
F-Si
Hf-F
F-Si
Hf-F
F-Si
F-Si
F-Si
F
F
SiO2
Bond
Enthalpy*
Bonds
355Hf-H
650Hf-F
553Si-F
299Si-H
Bond
Enthalpy*
Bonds
355Hf-H
650Hf-F
553Si-F
299Si-H
89
[5] M. Cao, P. V. Voorde, M. Cox and W. Greene, “Boron diffusion and penetration in
ultrathin oxide with poly-Si gate”,IEEE Elect. Dev. Lett. 19, 291 (1998).
[6] Y. Mitani, H. Satake, Y. Nakasaki, and A. Toriumi, “Improvement of charge-to-
breakdown distribution by fluorine incorporation into thin gate oxides”, IEEE Trans.
Elect. Dev. 50, 2221 (2003).
[7] Kang-ill Seo, Raghavasimhan Sreenivasan, Paul C. McIntyre, and Krishna C.
Saraswat, “Improvement in High-k (HfO2/SiO2) Reliability by Incorporation of
Fluorine”, IEEE Electron Devices Meeting (IEDM), 2005
[8] H.-H. Tseng, P.J. Tobin, E. A. Hebert, S. Kalpat, L. Fonseca, Z. X. Jiang, J. K.
Schaeffer, R. I. Hegde, D. H. Triyoso, D. C. Gilmer, W. J. Taylor, C. C. Capasso, O.
Adetutu, D. Sing, J. Conner, E. Luckowski, B. W. Chan, A. Haggag, S. Backer, R. Noble,
M. Jahanbani, Y. H. Chiu, B. E. White, “Defect passivation with fluorine in a TaCx high-
k gate stack for enhanced device threshold voltage stability and performance”, IEEE
Electron Devices Meeting (IEDM), Technical Digest, pp. 713-716, 2005.
[9] R. Xie, M. Yu, M. Y. Lai, L. Chan and C. Zhu, “High-k gate stack on germanium
substrate with fluorine incorporation”, Appl. Phys. Lett. 92, 163505 (2008)
[10] M. H. Zhang, F. Zhu, T. Lee, H. S. Kim, I. J. Ok, G. Thareja, L. Yu and Jack C. Lee,
“Fluorine passivation in poly-Si/TaN/HfO2 through ion implantation”, Appl. Phys. Lett.,
89, 142909 (2006)
90
[11] W. Chen, Q. Q. Sun, S-J. Ding, D. W. Zhang and L-K. Wang, “First principles
calculations of oxygen vacancy passivation by fluorine in hafnium oxide”, Appl. Phys.
Lett. 89, 152904 (2006)
[12] www.srim.org
[13] C.Sandhya, U. Ganguly, K.K. Singh, P.K. Singh, C. Olsen, S. M. Seutter, R. Hung,
G. Conti, K. Ahmed, N. Krishna, J. Vasia, and S. Mahapatra,“Nitride engineering and the
effect of interfaces on charge trap flash performance and reliability“, IEEE 46th Annual
International Reliability Physics Symposium, Phoenix, 2008
[14] R. Bez, E. Camerlenghi, A. Modelli, A. Visconti, “Introduction to Flash Memory”,
Proc. of IEEE, Vol. 91, No. 4, April 2003
[15] D. J. DiMaria and J. H. Stathis, “Anode hole injection, defect generation, and
breakdown in ultrathin silicon dioxide films”, J. Appl. Phys. 89, 5015 (2001)
[16] H.K.Park, G.Bersuker, P.D.Kirsch, IEEE Non-volatile memory technology
symposium (NVMTS) 2008
[17] M. Inoue, S. Tsujikawa, M. Mizutani, K. Nomura, T. Hayashi, K. Shiga, J. Yugami,
J. Tsuchimoto, Y. Ohno, and M. Yoneda, “Fluorine incorporation into HfSiON dielectric
for Vth control and its impact on reliability for poly-Si gate pFET”, IEEE IEDM, Tech.
Dig. 2005
[18] X. Yu, X. Shenhua, N. Zhaoyuan, C. Jun , L. Xinhua, X. Suliu, H. Song, D. Wei and
C. Shanhua, “Infrared and Optical Properties of Amorphous Fluorinated Hydrocarbon
91
Films Deposited with the Method of ECR Plasma “, Plasma Sci. Technol. 6 2337,
2004
[19] D.K.Schroder, Semiconductor Material and Device Characterization, 2nd
Edition,
2004
[20] J. Price, P. S. Lysaght, S. C. Song, H -J. Li and A. C. Diebold, “Identification of sub-
band-gap absorption features at the HfO2/ Si(100) interface via spectroscopic
ellipsometry”, Appl. Phys. Lett. 91, 061925 (2007)
[21] Y. Ono, M. Tabe, Y. Sakakibara, “Segregation and defect termination of fluorine at
SiO2/Si interfaces”, Appl. Phys. Lett.,62, 03-695, 1993
[22] J.H. Ha, K. Seo, P.C. McIntyre, K.C. Saraswat, and K. Cho, "Fluorine Incorporation
at HfO2/SiO2 Interfaces in High-k Metal-Oxide-Semiconductor Gate Stacks: Local
Electronic Structure," Appl. Phys. Lett. 90, 112911-1-3 (2007).
[23] J. A. Kerr, CRC Handbook of chemistry and physics 1999-2000.
92
Chapter 5
Novel Engineered Tunnel Barriers
In Chapter 4 we looked at fluorine incorporation as one possible solution to improve
retention loss and endurance degradation in engineered tunnel barrier based flash
memory. In this chapter we will look at the other alternative for fabricating novel tunnel
barrier structures. We will also look at how to scale engineered tunnel barriers beyond the
current technology and delve into some specific issues.
5.1 Motivation and Experimental Design
The motivation to experiment on novel tunnel stacks arises from three specific reasons:
• Till now, we have dealt with engineered tunnel barriers of type SiO2/high-k
(asymmetric) or SiO2/high-k /SiO2 (symmetric). As can be seen, in symmetric
tunnel barriers we deposit SiO2 as the top layer of the engineered stack. This layer
is mostly deposited using LPCVD and is not of high quality as is the furnace
grown bottom SiO2. Further, with respect to scaling of engineered tunnel stacks,
top SiO2 consumes equivalent oxide thickness (EOT) budget and, therefore, need
to be replaced by a higher-k dielectric.
93
• Retention loss is a major problem for tunnel barrier engineering. We found that
most of the high-k materials (HfO2, Si3N4, Al2O3 etc) are defect prone resulting in
poor retention. Therefore we need to try other novel high-k materials as well.
From simulations, we found La based high-k dielectric to be a suitable candidate
for implementing engineered tunnel barriers. This was true even for the case when
traps were considered in the tunnel stack. In practice, however, use of La2O3 is
limited due to its hygroscopic nature and fast mixing with other layers [1]. With
certain processing tricks, we could try to incorporate La-based high-k dielectrics
and see if performance can be enhanced
• The SiO2/Si3N4/SiO2 (ONO) tunnel stack has received much attention in recent
years [2, 3]. Erase in conventional SiO2 based TANOS flash memory is
problematic due to higher conduction band (CB) and valence band (VB) offsets
which SiO2 offers and deep storage trap levels in silicon nitride [4,5]. Using Si3N4
in engineered tunnel stack offers much lower VB offset leading to enhanced hole
injection from the substrate resulting in better erase. Given the advantage which
Si3N4 offers, we have kept the first two layers i.e. bottom SiO2 and Si3N4 fixed.
We only replace the top layer i.e. top SiO2 with a novel high-k material.
We now look at experimental design for implementing these novel stacks. Fig. 5.1
shows a schematic of the tunnel stacks we have considered.
94
Fig. 5.1 Schematic of the novel tunnel barriers considered (a) SiO2/Si3N4/Al2O3 (ONA)
stack (b) SiO2/Si3N4/La2O3 (ONL) and (c) conventional SiO2 used in TANOS flash
memory
The thicknesses of different layers used in our experiment are shown in table 5. In
addition to the ONL stack, we have also fabricated SiO2/Si3N4/nitrided La2O3 (i.e. LaON)
stack and is acronymed as ONLN. For the case of ONA, we fabricated an additional stack
where fluorine (Fii) was implanted in the bottom SiO2 layer of the engineered tunnel
stack. This stack has been given the acronym ONAF. For convenience, we will use
acronyms instead of the full stack description.
Silicon(100)
SiO2
SiNLa2O3 or LaON
Si3N4
Silicon(100)
SiO2
SiN
Al2O3
Si3N4
Al2O3
TaN electrode
Silicon(100)
SiO2
Si3N4
Al2O3
TaN electrode
Si3N4
Silicon(100)
SiO2
Si3N4
Al2O3
TaN electrode
Al2O3
TaN electrode
Silicon(100)
SiO2
SiNLa2O3 or LaON
Si3N4
Silicon(100)
SiO2
SiN
Al2O3
Si3N4
Al2O3
TaN electrode
Silicon(100)
SiO2
Si3N4
Al2O3
TaN electrode
Silicon(100)
SiO2
Si3N4
Al2O3
TaN electrode
Si3N4
Silicon(100)
SiO2
Si3N4
Al2O3
TaN electrode
Silicon(100)
SiO2
Si3N4
Al2O3
TaN electrode
Al2O3
TaN electrode
(B)(A) (C)(B)(A) (C)
TANOS flash Transistors
TANOS flash Capacitors
20 SiO2/15 SiN/ 30 LaON (ONLN)
40 SiO2(O)
20 SiO2/15 SiN/ 30 La2O3(ONL)
20 SiO2/15 SiN/ 25 Al2O3 (Fii) (ONAF)
20 SiO2/15 SiN/ 25 Al2O3 (ONA)
Engineered Tunnel Stacks (in A)
TANOS flash Transistors
TANOS flash Capacitors
20 SiO2/15 SiN/ 30 LaON (ONLN)
40 SiO2(O)
20 SiO2/15 SiN/ 30 La2O3(ONL)
20 SiO2/15 SiN/ 25 Al2O3 (Fii) (ONAF)
20 SiO2/15 SiN/ 25 Al2O3 (ONA)
Engineered Tunnel Stacks (in A)
95
Table 5 Novel engineered tunnel barriers with stack thicknesses. Both TANOS
capacitors and TANOS flash transistors were fabricated as shown above. All thicknesses
are in Angstroms.
Note that the bottom SiO2 thickness is around 2 nm while the Si3N4 is kept thin (~1.5 nm)
to avoid trapping in engineered tunnel stacks. All stacks have similar EOT.
5.2 Electrical results and discussion
We now examine at electrical results for these novel engineered tunnel stacks to gauge
their performance. We first look at ONL and ONLN TANOS capacitor stacks. Fig. 5.2
shows the pulse program characteristics of these stacks for two different voltages (15 V
and 19 V). A comparison is then made with SiO2 TANOS of similar EOT.
0
1
2
3
4
5
6
7
8
9
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00Pulse Time
Delt
a V
fb p
rog
ram
(V
)
ONLN_15V ONLN_19V ONL_15V
ONL_19V O_15V O_19V
Initial
Filling of Shallow
Traps
0
1
2
3
4
5
6
7
8
9
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00Pulse Time
Delt
a V
fb p
rog
ram
(V
)
ONLN_15V ONLN_19V ONL_15V
ONL_19V O_15V O_19V
Initial
Filling of Shallow
Traps
96
Fig. 5.2 Pulse program for different engineered tunnel TANOS capacitor stacks ONL,
ONLN and SiO2. Change in flat band voltage (delta Vfb) vs. program pulse time is shown.
These have been measured at two different programming voltages of 15 V and 19 V.
For the case of ONL, fast programming is observed initially which is attributed to filling
of shallow traps. However, later the shift in Vfb saturates with increasing program pulse
time. This might be because of electron trapping in engineered tunnel stacks resulting in
Vfb saturation. However, when La2O3 is nitrided, the programming behavior changes
dramatically. No fast trapping is seen; further no saturation in Vfb is observed with
increasing program pulse time. It is well known that nitridation of metal oxides helps in
trap passivation [6]; further nitridation in La2O3 reduces intermixing of layers resulting in
sharper interface [7]. Also, when performance is compared with SiO2, ONLN stack
shows higher Vfb shift for most program pulse time. We now look at the capacitance-
voltage (C-V) hysteresis to investigate the erase operation. Fig.5.3 plots C-V curves for
the same stacks.
0.55
0.65
0.75
0.85
0.95
1.05
1.15
-10 -5 0 5 10Sweep Voltage (V)
No
rmali
zed
Cap
acit
an
ce
(C
/Cm
ax)
O(program) O (erase) ONL (program)
ONL (erase) ONLN (program) ONLN (erase)
O (initial) ONL (initial) ONLN (initial)
Erase
ProgramInitial
0.55
0.65
0.75
0.85
0.95
1.05
1.15
-10 -5 0 5 10Sweep Voltage (V)
No
rmali
zed
Cap
acit
an
ce
(C
/Cm
ax)
O(program) O (erase) ONL (program)
ONL (erase) ONLN (program) ONLN (erase)
O (initial) ONL (initial) ONLN (initial)
Erase
ProgramInitial
0.55
0.65
0.75
0.85
0.95
1.05
1.15
-10 -5 0 5 10Sweep Voltage (V)
No
rmali
zed
Cap
acit
an
ce
(C
/Cm
ax)
O(program) O (erase) ONL (program)
ONL (erase) ONLN (program) ONLN (erase)
O (initial) ONL (initial) ONLN (initial)
Erase
ProgramInitial
97
Fig. 5.3 C-V hysteresis curves for different engineered stacks ONL, ONLN and SiO2
based TANOS are shown. The C-V sweep is from -10 to 10 V. The initial, programmed
and erase C-Vs are plotted for each stack.
We can see that for both ONL and ONLN stack, the program/ erase (P/E) window is
larger when compared to SiO2 TANOS of similar EOT. Erase for SiO2 TANOS capacitor
is a major problem resulting in smaller program/erase (P/E) window. This is due to
higher CB and VB offsets of SiO2; as a result stored electrons require much higher erase
voltage to be ejected out.
In summary, both ONL and ONLN offer better P/E window when compared to SiO2
stack. Also between ONL and ONLN, ONL shows faster programming initially but then
it saturates quickly. This phenomenon in not seen for nitrided La2O3 tunnel stack which
can be attributed to defect passivation.
Other engineered tunnel stacks ONA and ONAF also offer larger P/E window over SiO2
tunnel stacks. Fig. 5.4 shows P/E of ONA and ONAF TANOS flash transistors.
0.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
Program Pulse Time (s)
Pro
gra
m D
elt
a V
th(V
)
ONA_11V ONA_13V
ONA_15V ONAF_11V
ONAF_13V ONAF_15V
(A)
98
Fig. 5.4 (a) Shows program transients for ONA, ONAF TANOS flash memory transistors
for 11, 13 and 15 V program voltage. (b) Shows erase transients for the same stacks and
for 13, 15 and 19 V erase voltage.
As observed, ONA stack shows faster programming initially but then saturates rapidly
later. This is once again attributed to filling of shallow traps. Fii ONA however, does not
show this behavior suggesting trap passivation. These results are consistent with fluorine
incorporation in OHO TANOS described in Chapter 4. Similar behavior was also seen for
with/without nitridation for the ONL stack. Erase is also seen to be better for ONAF
stack.
One reason why we investigated these novel tunnel barriers was because of our emphasis
to improve retention. We now look at retention loss for these novel engineered stacks. In
table 6 we compare the retention for all engineered tunnel stacks known in literature to
date. We look at our work and compare it with other significant works directly.
-2.00
-1.80
-1.60
-1.40
-1.20
-1.00
-0.80
-0.60
-0.40
-0.20
0.00
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00
Pulse Time (s)
Era
se D
elt
a V
th (
V)
ONAF_13V ONAF_15V
ONAF_19V ONA_13V
ONA_15V ONA_19V
(B)
99
Table 6 Retention characteristics for various engineered tunnel stacks at 1500C and 24
hours. It is importan t to note that initial Vth was similar for all stacks.
Devices were programmed to change in threshold voltage (Vth) of 5V and retention was
measured for 24hrs at 1500C. Initial Vth values were similar for all engineered tunnel
stacks.
Following can be concluded from table above:
• ONL stack shows a huge retention loss of around 36.2% while the ONLN
(nitrided La2O3) stack loses just 12% charge. This might be attributed to defect
passivation in lanthanum oxide during nitridation. Further, this is the best
retention obtained to date for all engineered tunnel stacks known in literature.
This result is also better than the retention loss in ONO (of ~14%) as obtained by
[1]. Also, note that EOT for ONLN stacks are ~36 Å. In comparison, SiO2 (~40 Å
thick) TANOS loses around 10% charge.
10~4040 SiO2[8, (C)]
26.75/18.20~39/~39ONA/ONA-Fii(20/15/25) (A)
36.2/12.4~36/~36ONL/ONLN(20/15/30) (B)
~50/35
~30
14.3
Percentage Charge Loss (%) (after 24 hrs & 150C)
~66OHO/OHO-Fii(20/30/40)[9]
~36
~40
EOT of Tunnel Stack (in A)
OA(25/25)[8]
ONO(15/15/15) [2]
Engineered Tunnel Stacks (in Angstroms) in TANOS Flash Memory
10~4040 SiO2[8, (C)]
26.75/18.20~39/~39ONA/ONA-Fii(20/15/25) (A)
36.2/12.4~36/~36ONL/ONLN(20/15/30) (B)
~50/35
~30
14.3
Percentage Charge Loss (%) (after 24 hrs & 150C)
~66OHO/OHO-Fii(20/30/40)[9]
~36
~40
EOT of Tunnel Stack (in A)
OA(25/25)[8]
ONO(15/15/15) [2]
Engineered Tunnel Stacks (in Angstroms) in TANOS Flash Memory
100
• ONA stacks (~39 Å) thick also show poor retention with charge loss of ~26 %.
However, when fluorine is implanted, retention improves dramatically to 18%
charge loss. Once again, we find that fluorine passivates defects leading to
improved retention. Fluorine is also shown to improve retention in OHO TANOS
(~35 % charge loss vs. 50% charge loss with no fluorine).
• Other engineered tunnel stacks OA (~30 %) show poor retention when compared
with ONLN or SiO2 tunnel stack.
We could not measure endurance for TANOS flash capacitors (ONL/ONLN stacks).
Endurance for ONA and ONAF were similar to OA stacks (described in Chapter 3). As
mentioned before, since P/E window is larger for engineered tunnel stacks, window
closure is not a major concern for these stacks.
5.3 Summary
In summary, we are able to demonstrate some novel engineered tunnel barriers. Best in
class retention was obtained for SiO2/Si3N4/ nitrided-La2O3 tunnel stack. Using high-k
dielectric as the top layer in engineered tunnel stacks can help in scaling. Further, we also
showed that fluorine incorporation does improve retention for ONA stacks as well.
5.4 References
[1] X. Wu, D. Landheer, G. I. Sproule, T. Quance, M. J. Graham, G. A. Botton,
“Characterization of gadolinium and lanthanum oxide films on Si (100)”, J. Vac. Sci.
Technol. A Volume 20, Issue 3, pp. 1141-1144 (May 2002)
101
[2] H. T. Lue, S. Y. Wang, E. Lai, Y. Shih, S. C. Lai, L. W. Zhang, K. C. Chen, J. Ku, K.
Y. Hseih, R. Liu, C. Y. Liu, “BE-SONOS: A bandgap engineered SONOS with excellent
performance and reliability”, IEEE International Electron Devices Meeting, pp. 547-550,
2005
[3] H. T. Lue, S. Y. Wang, Y. H. Hsiao, E. H. Lai, L. W. Yang, T. Yang, K. C. Chen, K.
Y. Hseih, R. Liu, Y. L. Chih, “Reliability Model of Bandgap Engineered SONOS (BE-
SONOS)”,IEEE International Electron Devices Meeting, pp.1-4, 2006
[4] C. Sandhya, U. Ganguly, K.K. Singh, P.K. Singh, R. Hung, C. Olsen, S. M. Seutter,
G. Conti, K. Ahmed, N. Krishna, J. Vasi, and S. Mahapatra, “Nitride engineering and the
effect of interfaces on Charge Trap Flash performance”, IEEE Intl. Reliability Physics
Symposium (IRPS) 2008
[5] Y. Yang and M. H. White, “Charge retention of scaled SONOS nonvolatile memory
devices at elevated temperatures”, Solid State Electronics, Vol. 44, Issue 6, 1 June 2000,
Pages 949-958
[6] P. Jamet, S. Dimitrijev and P. Tanner, “Effects of nitridation in gate oxides grown on
4H-SiC”, J. Appl. Phys. 90, 5058 (2001)
[7] T. Gougousi, M. J. Kelly, D. B. Terry and G. N. Parsons, “Properties of La-silicate
high-K dielectric films formed by oxidation of La on silicon”, J. Appl. Phys. 93, 1691
(2003)
102
[8] D. C. Gilmer, N. Goel, S. Verma, H. Park, C. Park, G. Bersuker, P. D. Kirsch, K.C.
Saraswat and R. Jammy, “Band Engineered Tunnel Oxides for Improved TANOS-type
Flash Program/Erase with Good Retention and 100K Cycle Endurance:, IEEE VLSI
Symposium-Tech, Systems and Applications, Taiwan, 2009
[9] S.Verma, G. Bersuker, D. Gilmer, A. Padovani, H. Park, A. Nainani, D. Heh, J.
Huang, K. Parat, J. Jiang, P. D. Kirsch, L. Larcher, H. H. Tseng, K. C. Saraswat and R.
Jammy, “A Novel Fluorine Incorporated Band engineered (BE) Tunnel (SiO2/ HfSiO /
SiO2) TANOS with excellent Program/Erase and Endurance to 105 cycles”, IEEE
International Memory Workshop, Monterey, 2009
103
Chapter 6
Conclusions
In previous chapters we looked at engineered tunnel barriers as a way to scale the current
tunnel dielectric for flash memory. We investigated the properties of these tunnel stacks
in simulations and in experiments as well. In this chapter, we summarize our work, draw
key conclusions and suggest future directions to this work.
6.1 Key results
We summarize the key results in the following section. In a nutshell, the following key
results are:
� Feasibility of engineered tunnel barriers was established under flash memory
device constraints
– This was established both under ideal situations as well as in presence of
traps in high-k material
– Simulations show that La2O3 is the best tunnel layer both in absence or
presence of traps
– Symmetric Barriers are preferred over asymmetric stacks
– Thickness of bottom SiO2 should be ~2 nm for optimal performance
104
� Engineered tunnel barriers do suffer from P/E vs. retention tradeoff as well as
from SILC thus limiting their practical implementation. This was demonstrated
for wide range of high-k materials like Al2O3, HfO2 and Si3N4.
� To solve these problems, for the first time, fluorine is introduced in tunnel stacks
and is shown to improve both retention and endurance in different tunnel stacks
– Endurance measurements showed that best performance is achieved by
incorporating fluorine in bottom SiO2.
– Improvement in endurance is attributed to reduction is interface defect
states (Dit) at Si/SiO2 interface as confirmed by Dit measurements
– Improvement in retention is also demonstrated and is shown to be due to
passivation of shallow bulk traps
� Novel devices structures are proposed as solutions to scale engineered barriers
– Best in class retention for engineered tunnel barrier is achieved using
SiO2/Si3N4/nitrided La2O3 tunnel stack.
– Scaling of engineered tunnel barriers can be achieved by replacing the top
SiO2 layer by a higher-k material.
6.2 Future work
In this section, we will look at the future direction of this research field. We have already
looked at some of the limitations of engineered tunnel barriers. Even though solutions
have been proposed and demonstrated, use of engineered tunnel barriers in industry will
105
take more work. Here are some of the key innovations which can bring implementation
of engineered tunnel barriers closer to reality:
� Material innovation: Finding novel high-k materials with excellent properties (as
discussed earlier) would make implementation of engineered tunnel barriers easy.
Tailoring electrical properties of these materials is crucial to suit the requirements
of scaled flash memory.
� Process innovation: Just like fluorination other process innovations are required
to continue scaling of engineered tunnel barriers. Most importantly, finding
passivant for high-k materials is crucial to engineer the right material. Further,
depositing high-k material directly on Si is a challenge which has been addressed
recently [1]. This would be directly useful in fabricating crested tunnel barriers.
� Device innovation: Following are some of the device innovations which can help
scale the current tunnel dielectric:
• Novel tunnel barrier structures are important to continue scaling of current
tunnel dielectric.
• Recently, nanocrystals incorporated in SiO2 (tunnel oxide) have been used
as discrete storage sites in flash memory. They have been shown to trap
electrons efficiently due to coulomb blockade. As a result, retention loss
improves dramatically even with scaled SiO2 [2]. However, program/erase
(P/E) window is limited by discrete trapping sites and lower density of
nanocrystals. Still, the idea serves are a promising alternative to
engineered tunnel barriers. However, if both nanocrystals and engineered
106
tunnel barriers are used simultaneously, P/E can be improved while
maintaining excellent retention. This needs to be explored further
experimentally.
• As discussed before, lower effective tunneling mass fastens P/E while
heavier effective mass improves retention. Using different substrates (like
Ge) or using Si substrates of different orientation can help change the
effective tunneling mass and may affect performance of engineered tunnel
barriers.
6.3 References
[1] J. Huang, D. Heh, P. Sivasubramani, P. D. Kirsch, G. Bersuker, D. C. Gilmer, M. A.
Quevedo-Lopez, M. M. Hussain, P. Majhi, P. Lysaght, H. Park, M. Cruz, V. Diaz, P. U.
Hung, J. Price, H.-H. Tseng, R. Jammy, “Gate first high-k/metal gate stacks with zero
SiOx interface achieving EOT=0.59nm for 16nm application”, IEEE VLSI Tech. Symp.
pp. 34-35, 2009
[2] R. Ohba, Y. Mitani, N. Sugiyama, S. Fuhjita, “10 nm bulk-planar SONOS-type
memory with double tunnel junction and sub-10 nm scaling utilizing source to drain
direct tunnel sub-threshold”. IEEE International Electron Devices Meeting, 2008