tunnel fet c-v modeling€¦ · c-v. characteristics on inverter circuit delay by using the our...

© 2017 Toshiba Corporation

Tunnel FET C-V modeling:- Impact of TFET C-V characteristics

on inverter circuit performance

Chika Tanaka, Tetsufumi Tanamoto, and Masato KoyamaCorporate R&D Center, Toshiba Corporation

MOS-AK Workshop, 2017, Leuven

© 2017 Toshiba Corporation 2

1. Backgroundi. Device and Circuit Characteristics of TFETii. Capacitance-Voltage characteristics of TFETiii. Impact of TFET CV characteristics on circuit performance

2. Modeling & Simulation methodi. Implementation of C-V threshold voltage (VthCV) on BSIM4 parameterii. Targeted Id-Vg and Cg-Vg characteristicsiii. VthCV optimization and simulated circuit

3. Simulation resultsi. Influence of VthCV modulation on inverter delayii. Vdd dependence on ∆tdelay with Mirror effect

4. Summary

Outline


Device and Circuit Characteristics of TFET

Steep S.S.

TFETs Vdd=1.2VLow Ion

65nm CMOS Vdd=1.2V

Low Vdd operation

TFETs Vdd=0.5V 65nm CMOS Vdd=0.5V

Circuit Simulation (Ring Osc.)

Tunnel Field Effect Transistor (TFET) vs. Conventional CMOS

TFET Steep Sub-threshold Slope Low Ion dew to band-to-band tunneling

→Advantage of low-Vdd and low-power device


Capacitance-Voltage characteristics of TFET

𝑉𝑉P =𝐶𝐶M

𝐶𝐶M + 𝐶𝐶L

S

Vd=0V、Vg=0V G D

Vd=1V、Vg=0V

Cgs: depletion cap.

S

G D

Cgd: response of minority carrier

IEEE TED, 56, 9 (2009) 2092.

Asymmetry of Cgs and Cgd by depletioncapacitance of source side tunnel junction

Vp increases as the increase of drain sidemirror capacitance

CM：mirror cap.(=Cgdp+Cgdn)For TFT, CM~2Cgg

For MOSFET, CM~Cgg

CL：load cap.(cap. for next stage)

Peak voltage for overshoot (VP)

Cgs: depletion cap.

Cgd: response of minority carrier and depletion cap.


NMOS NLTFET NSJL

Cgd

Cgb

Cgg

Cgs

CgdCgb

Cgg

Cgs

CEFF is function of Cgg: CEFF ~ CM+CL(Cgg)…Circuit delay (tdelay) is influenced by both CM and CL

2D TCAD simulation results

Impact of TFET CV characteristics on circuit performance

Cgb

Cgs

Cgg

Cgd

When Vd is applied,(1) Vth

CV=f(Vd) …Cgg effectively decreases (2) Cgd>>Cgs …CM increasing

Modeled by voltage dependence on Vth for CV (VthCV)

𝒕𝒕delay ∝𝑪𝑪EFF � 𝑽𝑽dd

𝟐𝟐𝑰𝑰on





4. Summary

Outline


D

Equivalent circuit for N-TFET

Investigate the influence of effective Cgg decrease on inverter circuit delay by CV threshold modulation

Vg [V]

Cgg

[a.u

.]

VOFFCV(Vd):on

0.0 0.4 0.8 1.2 0.0 0.4 0.8 1.2Vg [V]

Cgg

[a.u

.]Vd=0Vd=1

Vd=0

Vd=1

Implementation of VthCV(Vd) on BSIM4 parameterVOFFCV(Vd):off

BSIM4-based CV model:Implementation of Vd dependence on VthCV

”VOFFCV”→VOFFCV(Vd)=f(Vd)


Targeted Id-Vg and Cg-Vg characteristicsGate

Source Drain

BoronAs

GateSource Drain

BoronAs

Lg=120nm, Tox=2nm, Ns=1E16 cm-3

Vd=0.5V Vd=0.7V Vd=1.0V

Vg [V]-0.5 0.0 0.5 1.0 1.5

Vg [V]-0.5 0.0 0.5 1.0 1.5

Vg [V]-0.5 0.0 0.5 1.0 1.5

Cap

acita

nce

[fF]

0.0

0.5

1.0

1.5

2.0

2.5

Cgg

Cgd

Cgs

Cgg

Cgd

Cgs Cgs

Cgd

Cgg

Cap

acita

nce

[fF]

0.0

0.5

1.0

1.5

2.0

2.5

Cap

acita

nce

[fF]

0.0

0.5

1.0

1.5

2.0

2.5

Vd=1.0VVd=0.7VVd=0.5V

Vg [V]-0.5 0.0 0.5 1.0 1.5

1E-6

1E-81E-10

1E-121E-141E-16

I d[A

/mm

]

Drain voltage (Vd) dependent on Vth for C-V


VthCV optimization and simulated test circuit

VthCV optimization result

Simulated circuit configuration

VOFFCV=f(Vd, voffcv1, voffcv2) Split parameters “VOFFCV” to have Vd

dependence Extract to be optimized with each Vd

for “voffcv1” and “voffcv2”

2-stages inverter(output: Vout1)

CL=2・Cgg

CM=Cgdp+Cgdn





4. Summary

Outline


𝒕𝒕delay ∝𝑪𝑪EFF � 𝑽𝑽dd

𝟐𝟐𝑰𝑰on

Influence of VthCV modulation on inverter delay

time [nsec.]0 20 40 60

V out

1[V

]

-0.5

0.0

VthCV with Vd dependenceVdd=1.0V

0.5

1.0

1.5

∆tdelay shows the effective gatecapacitance reduction.

Vdd [V]0.4 0.6 0.8 1.0 1.2

0.0

0.5

1.0

1.5

2.0

2.5

∆t d

elay

[nse

c.] Vdd∝Cgg

CEFF~CM + CL

Effect of CL reduction

If load capacitance (CL) becomes small, inverter delay reduced.

Inverter Delay (tdelay)

VthCV w/o Vd dependence∆tdelay

∆tdelay = | trise(with Vd depend.) – trise(w/o Vd depend.) |


Vdd dependence on ∆tdelay with Mirror effect

CM = Cgdp + Cgdn

CEFF~ CM + CL

𝝉𝝉delay ∝𝑪𝑪EFF � 𝑽𝑽dd

𝟐𝟐𝑰𝑰on

0.3

∆tdelay increasesby Cgg reduction

0.5 0.7 0.9 1.1

Vdd [V]

1.0

0.6 0.8 1.0 1.2

0.8

0.6

0.40.4

Vdd [V]

0.01.0 Even when considering Miller effect, the effect

that the effective Cgg reduction is large.Increase in ∆tdelay becomes prominent as low Vdd.

2.03.04.05.06.0

Correctionby Mirror effect

Nor

mal

ized

∆t d

elay

Nor

mal

ized

∆t d

elay

∆tdelay decreases by Mirror effect


Summary

AcknowledgementsThis work was supported by JST CREST Grant Number JPMJCR1332, Japan.We thank K. Adachi, A. Hokazono, M. Fujimatsu, and S. Kawanaka for discussions andsupports.

i. Implementation of the effective Cgg reduction on SPICE model was made by parameterizing the BSIM4 C-V parameter.Re-parameterizing of BSIM4 C-V parameter is reasonable approach to analyze the non-Si CMOS circuit performance.

ii. We investigated the influence of TFET C-V characteristics on inverter circuit delay by using the our proposed (optimized) model.Although the delay increases with the influence of overshoot due to the increase in CM, the effect of decreasing CL is prominent due to the reduction in effective gate capacitance, and then the inverter delay is smaller than the case where TFET C-V characteristics is not considered.

tunnel fet c-v modeling€¦ · c-v. characteristics on inverter circuit delay by using the our...

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