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Tutorial 14

MODULE 10

1

Question 1

Modify the time slice scheduling program to have non-

pre-emptive priority, FAIR Scheduling

2

E.g. Context State of machine

PRESENT DB 0

Priority DB ?

RGAX DW ?

RGBX DW ?

RGCX DW ?

RGSP DW ?

RGBP DW ?

RGSI DW ?

RGDI DW ?

RGFLAG DW ?

RGIP DW ?

RGCS DW ?

RGDS DW ?

RGES DW ?

RGSS DW ?

DUMMY2 DW ? 32

bytes

3

Int60 – add a new procedure to queue

INT60 PROC FAR USES DS AX DX SI

MOV AX,0MOV DS,AX

STI

MOV SI,500H

X2: CMP SI,660H

JZ END1

CMP [SI],0

JZ X1

ADD SI,32

JMP X2

BX-IP DX -CS

Find a location in

queue where thread

is not present

4

Int60 – add a new procedure to queue

X1: MOV BYTE PTR[SI],0FFH

MOV BYTEPTR[SI+1],Priority

MOV WORD PTR [SI+18], 200H

MOV [SI+20],BX ;save IP

MOV [SI+22],DX ;save CS

MOV [SI+28],SS ;save SS

MOV AX,SI

AND AX,3FFH

SHL AX,3

ADD AX,7000H

MOV [SI+10],AX ;Save SP

5

Time Slice programINT12 PROC FAR USES DS AX DX SI

MOV AX,0

MOV DS,AX

MOV SI,[4FEH]

CALL SAVES

INT12A:MOV DI,SI

ADD SI,32

MOV DL,0

M3: CMP SI,660H

JNE M1

MOV SI,500H

M1: CMP [SI], 0FFH

JE MA

MB: ADD SI,32

JMP M3

MA: CMP [SI+1],DL

JBE M2

CMP SI,DI

JNE MC

INC DL

CMP DL, maxpriority

JNE MC

MOV DL,0

MC: JMP MB

M2: TIMER START

MOV [4FEH ],SI

JMP LOADS

6

Cache Access Time

tmain – access time for main memory

tL1 – access time for primary cache

h1 – hit ratio of primary cache

tL2 – access time for primary cache

h2 – hit ratio of secondary cache but not primary

If system has only L1 cache

tav ?

If system has L1 and L2 cache

tav?

tav = h1tL1 + (1-h1)tmain

tav = h1tL1 + h2tL2 + (1-h1 -h2)tmain

7

Problem 1

Assume that the system has a two-level cache:

The level-1 cache has a hit rate of 90% and the level-2

cache has a hit rate of 97%.

The level 1 cache access time is 4 ns, the level 2 cache

access time is 15ns and access time of main memory is 80

ns.

What is the average memory access time?

8

Solution

h1 – 0.9

h2 - 0.1 x 0.97

tav = h1tL1 + h2tL2 + (1-h1 -h2)tmain

tav = 0.9 x 4ns + 0.097 x 15ns + (1-0.9-0.097) 80ns

5.295 ns

9

Problem 2

If we want an average memory access time of 6.5ns,

Cache access time is 5 ns

Main memory access is 80 ns.

What cache hit rate must we achieve?

10

Solution

tav = h1tL1 + (1-h1)tmain

tav – 6.5ns

tL1 – 5ns

tmain – 80ns

6.5 ns = h1 * 5ns + 80ns – h1 * 80ns

h1 = 0.98

98 %

11

Problem 3

The following data is present in memory of size 16

locations

12

0000 F8

0001 56

0010 3A

0011 79

0100 67

0101 8D

0110 9B

0111 78

1000 91

1001 AD

1010 BC

1011 78

1100 96

1101 70

1110 00

1111 FF

Problem 3

If the data is read by the processor in the following order

from the addresses

0000

0001

0100

1000

Show the contents of the cache for direct-mapped; four

line cache with each read operation.

13

Solution

Main Memory Address – 4 bits

Cache – 4 line

Address – 2 bits

Block No. – 2bits Tag 2- bits

00 01

14

Solution

15

Block Tag Data

00

01

10

11

Solution – After 1st read

16

Block Tag Data

00 00 F8

01

10

11

Cold Miss

Solution – After 2nd read

17

Block Tag Data

00 00 F8

01 00 56

10

11

Cold Miss

Solution – After 3rd read

18

Block Tag Data

00 00 F8

01 00 56

10

11

Conflict Miss


19

Block Tag Data

00 01 67

01 00 56

10

11

Conflict Miss

Solution – After 4th read

20

Block Tag Data

00 01 67

01 00 56

10

11

Conflict Miss


21

Block Tag Data

00 10 91

01 00 56

10

11

Conflict Miss

Problem 3a

Repeat the problem if the cache for 2 way set associative,

two line cache after every read operation.

22

Solution

Main Memory Address – 4 bits

Cache – 4 line

Address – 1 bit

Block No. – 1 bit Tag 3- bits

0 001

23

Solution

24

Block Tag Data Tag Data

0

1

Set 0 Set 1


25


0 000 F8

1

Set 0 Set 1

Cold Miss


26


0 000 F8

1

Set 0 Set 1

Cold Miss

Solution – After 2nd read

27


0 000 F8

1 000 56

Set 0 Set 1

Cold Miss


28


0 000 F8 010 67

1 000 56

Set 0 Set 1

Cold Miss


29


0 000 F8 010 67

1 000 56

Set 0 Set 1

Conflict Miss


30


0 100 91 010 67

1 000 56

Set 0 Set 1

Conflict Miss

Question 5

Processor - 80286

GDTR – 100000H

31

GDT

Address Data

100008 00 00 82 01 00 00 FF FF

100010 00 00 93 20 00 00 00 7F

100018 00 00 83 03 00 00 00 3F

100020 00 00 A1 0A 00 00 00 1F

100028 00 00 DF B0 00 00 01 FF

100030 00 00 92 B1 00 00 0F FF

100038 00 00 BF 7B 00 00 3F FF

100040 00 00 D2 7A 00 00 07 FF

100048 00 00 9F A1 00 00 1F FF

100050 00 00 C4 02 00 38 10 00

100058 00 00 85 00 00 20 00 00

100060 00 00 B3 50 00 00 1F FF

32

LDT1

Address Data

010000 00 00 82 01 00 00 FF FF

010008 00 00 82 20 00 00 FF FF

010010 00 00 83 03 00 00 00 3F

010018 00 00 FC 0A 00 00 00 1F

010020 00 00 DF B0 00 00 01 FF

010028 00 00 92 B1 00 00 0F FF

010030 00 00 B2 7B 00 00 03 FF

010038 00 00 D2 7A 00 00 07 FF

010040 00 00 9F A1 00 00 1F FF

010048 00 00 B3 A3 00 00 3F FF

010050 00 00 B3 B1 00 00 FF FF

010058 00 00 82 50 00 00 1F FF

33

LDT2

Address Data

200000 00 00 82 01 00 00 FF FF

200008 00 00 82 20 00 00 FF FF

200010 00 00 83 03 00 00 00 3F

200018 00 00 FC 0A 00 00 00 1F

200020 00 00 DF B0 00 00 01 FF

200028 00 00 92 B1 00 00 0F FF

200030 00 00 B2 7B 00 00 03 FF

200038 00 00 D2 7A 00 00 07 FF

200040 00 00 9F A1 00 00 1F FF

200048 00 00 B3 A3 00 00 3F FF

200050 00 00 82 B1 00 00 FF FF

200058 00 00 B3 50 00 00 1F FF

34

Question

Current CPL - 10

CALL 0051H , [1200H]

35

Solution

7B 10 00H

36

Question

Current CPL 00

CALL 0058H , [1400H]

37

0000 0000 0000 0000 Link

ESP0

0000 0000 0000 0000 SS0

ESP1

0000 0000 0000 0000 SS1

ESP2

0000 0000 0000 0000 SS2

CR3

EIP (00 00 10 00)

EFLAGS

EAX

ECX

EDX

EBX

ESP

EBP

38

ESI

EDI

0000 0000 0000 0000 ES

0000 0000 0000 0000 CS (5000)

0000 0000 0000 0000 SS

0000 0000 0000 0000 DS

0000 0000 0000 0000 FS

0000 0000 0000 0000 GS

0000 0000 0000 0000 LDT

Available T

Available to user

39

tutorial 14 - sign in or register | edge · tutorial 14 module 10 1. question 1 ... block tag data...

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