tutorial ahs11 srinivas

Design of ADCs with Adaptive

Resolution

A Mahesh Kumar, V. Sreehari, M.B. Srinivas

Birla Institute of Technology and Science

Hyderabad Campus, India

Outline of the Presentation

• Introduction

• ADC Performance Parameters

• ADC Architectures - Overview

• Adaptive ADCs

• Simulation Results

• Practical Applications

• Conclusion

Introduction

• What is an ADC ?

– An ADC is a circuit which converts analog signal (

Continuous form) to digital form (Discrete form)

Introduction

• Continuously varying analog signals are sampled at a fixed

rate.

• Sampled values are then expressed as a digital number, using a

binary numbering system.

A

t

Basic illustration of Analog to digital conversion

Analog-to-Digital

Converter

V

t

Introduction

• Every signal that can be measured is an analog signal f(t) i.e.,

continuous in time.

• Samples of the signal f(t) are taken at specified time intervals

T.

Introduction

• Sample and hold circuit needed for rapidly changing signals

(not compulsory, though)

• A simple sample-and-hold circuit,

Introduction

• Block diagram of an ADC

A

t

A

t

V

t

ADC

Analog i/p signal

Digital o/p signal

Sampled signal

S/H ADC Remaining

Ckt

Introduction

Introduction

• Fundamental Characteristics of ADC are sampling

and quantization

Sampling - Convert a continuous time input signal to a

discrete time representation. The input signal must be band

limited to no more than ½ Fs to prevent aliasing.

Quantization - Convert a continuous amplitude input signal

to a discrete amplitude representation.

Introduction

• Sampling

Time domain Frequency domain

Introduction

• Nyquist-Rate Sampling – sampling at twice the signalfrequency; Otherwise, aliasing will occur.

• There are two ways to prevent aliasing:

– To sample fast enough to cover all spectral components,

including the ones outside band of interest (parasitics)

– To adequately filter all undesired signals (limit fin,max

through filtering) so the ADC does not digitize them.

Introduction

Oversampling (Upsampling)• Signal is sampled at a rate greater than Nyquist rate. If the

signal has bandwidth of fB, then fs>> fB

- Relaxes requirements on the preceding antialias filter

- Oversampling also helps to reduce the quantization noise.

Introduction

Subsampling (Downsampling or undersampling)• Sampling at a rate less than the Nyquist rate results in aliasing

in frequency domain. If the signal is centered at anintermediate frequency and band-limited, it is not necessarilydestructive. Subsampling can be exploited to mix anarrowband RF or IF signal down to a lower frequency.

Performance Parameters

• Resolution indicates no. of discrete values an ADC canproduce

• For example,

– An ADC that encodes an analog input to one of 256discrete values has a resolution of 8 bits. (2^8 = 256).

– Higher the resolution, more accurate the measurement.

• Voltage Resolution = overall voltage measurement rangedivided by no. of discrete values.

• For example,

– If full scale measurement is 0 to 10 V

and ADC resolution is 12 bits i.e., 2^12 = 4096 levels

– Voltage resolution = (10-0)/4096 = 2.44 mV.


• Performance of ADC is studied by its Static and Dynamic

parameters.

• Static Parameters: Describe the difference between the actual

points and the ideal points in the staircase transfer function of

ADC when converting DC signals

• Static parameters are Offset error, Gain error, Full scale error,

DNL (Differential Non-linearity), and INL ( Integral N0n-

linearity).


• Offset Error

– Offset error is the difference between the nominal and

actual offset points as shown below


• Gain Error

– Difference between the actual and ideal gain points

when offset has been reduced to zero, measured at

the rightmost


• Full Scale Error

– Full scale error is a measure of how far the last

code transition is from the ideal full scale maxi-

mum voltage.


• DNL (Differential Non-linearity)

– Maximum deviation in the difference between two

successive threshold points from 1LSB.


• INL (Integral Non Linearity):

– Maximum deviation of the transition point from the straight

line passed through the end points or best-fit. It is referred

to as the relative accuracy of a converter. If max INL is less

than 0.5LSB, the ADC is guaranteed to be monotonic.


– Dynamic parameters are related to AC specifications

such as resolution, sampling frequency and input

signal frequency.

– Important dynamic parameters are

– Signal-to-Quantization Noise Ratio

– Signal-to-noise ratio (SNR)

– Signal-to-noise and distortion ratio (SNDR)

– Effective number of bits (ENOB)

– Total harmonic distortion (THD)

– Spurious-free dynamic range (SFDR)


• Signal-to-Quantization Noise Ratio

– The ratio of the signal power to the quantization noise

power at the output, usually for a sinusoidal input signal.


• SNR (Signal-to-Noise Ratio) is given by the total noise

power (includes all bins except DC, signal, and 2nd through

7th harmonic)


• Signal-to-(Noise+Distortion) Ratio (SNDR) is the ratio

of the signal power to the noise and distortion power (includes

all bins except DC and signal) at the output for a full scale

sinusoidal input.

• SNDR depends on the amplitude and the frequency of the

sinusoidal input tone


• ENOB (Effective Number of Bits) is a global indication

of ADC accuracy at a specific input frequency and sampling

rate.

• ENOB – Obtained by measuring the peak of SNDR and is

defined by:


• Total Harmonic Distortion (THD) is the rms sum of all

harmonics in the output signal’s FFT spectrum. By

convention, total distortion power consists of 2nd through 7th

harmonic.

• In communications and RF applications, THD is often a more

important figure of merit for ADC than DC- nonlinearity.


• Spurious Free Dynamic Range (SFDR) is the differencebetween the maximum signal component and the largestdistortion component in dB. SFDR is important because noiseand harmonics restrict a data converter’s dynamic range.SFDR is very important for high frequency applications,where a spurs can be interpreted as adjacent channelinformation.

ADC Architectures - Overview

Flash ADC

• Flash ADC is the fastest ADC compared to any other ADC.

It is used for high-speed and very large bandwidth

applications.

Flash ADC• Disadvantages

– Large number of comparators

– Limited number of bits ( i.e., Low Resolution)

– Area & Power consumption.

– Larger input capacitance.

– Dynamic performance is poor.

• Applications

– Radar processing, digital oscilloscopes, high-density disk

drives, digital video, memory application.

Semi-Flash ADC

• Semi-Flash ADC (or Sub-ranging ADC) can beimplemented with two half resolution flash ADCs and adigital-to-analog converter (DAC). In this, number ofcomparators is reduced by a large number.

• Disadvantages

– DAC Inaccuracy

– Calibration techniques

– Area, power & speed

• Applications

– Telecommunication, Ethernet, video, control applications

Pipelined ADC

• Pipelined ADC can be implemented with at least two or

more low resolution flash ADCs . Each stage has a S/H circuit

to hold the amplified residue from the previous stage. The final

binary output is obtained after passing through digital error

correction logic.

Pipelined ADC

• Disadvantages

– Limitations due to several clock cycles needed

– Latency

– Medium Speed.

• Applications

– Digital imaging, Data transmission, satellite

communications.

SAR ADC

• SAR ADC is commonly called successive approximation

converter. Architecture of the SAR ADC consists of one

comparator, a DAC, and a successive approximation register.

SAR ADC

• Disadvantages

– Limited Sampling rates

– Low Input Bandwidth

– Low speed

– DAC linearity

• Applications

– Data-acquisition applications, Touch Screens, Pressure

Measurements, Medical Imaging, Multi-channel

applications.

Sigma Delta ADC

• SIGMA DELTA ADC is also called an over-sampling

ADC. It consists of two main blocks : One is the sigma delta

modulator that includes an integrator, a comparator, and a

single-bit DAC and the second a digital filter.

Sigma Delta ADC

• Disadvantages

– Limited Sampling rates

– Low speed

– DAC linearity

– Over Sampling Ratio (OSR)

• Applications

– Wireless infrastructure, Digital audio processing,

Temperature sensing applications.

ADC Architectures – A Comparison

• Popular ADC architectures are addressed w.r.t resolution,

sampling frequency and performance.

ADC Architectures – Summary

• A Summary of the ADC features

Why Adaptive ADCs?

• In Conventional ADC designs, once the ADC is designed its

resolution is fixed.

• Power consumption of the ADCs increases with resolution

Elements of the Proposed Adaptive

ADC• “Peak detector circuit and sub-flash architecture are

introduced to make ADC resolution “Adaptive”

• CMOS decoder circuit of the ADC is designed with symmetryfor high speed conversion, small area and low powerconsumption

Design of Adaptive ADCs

Adaptive ADCs

Peak Detector Circuit for Reconfigurability

• A Novel peak detector circuit is introduced to make the ADCresolution adaptive based on the input analog signal voltagelevel

• It consists of an amplifier, three diodes (D1, D2, D3),comparators and multiplexers.

• Peak value of the input analog signal is stored on the outputcapacitor labeled as Vc.

• Peak detector circuit is used to generate control signals to ADCto select the mode of operation as 4-bit or 6-bit or 8-bit based onanalog input signals and reference voltages V1, V2 and V3.

Adaptive ADCs

V 1

+

_

+

V 2 V3

D1 D 2 D3K1 K 2 K 3

MUX1 MUX2 MUX3

Digital Logic

C1 C2 C38bit 6 bit 4bit

A1 A2 A3

Vin

Vc

+ +

comp1 comp2 comp3

_ _ _

Bias Block

V1 V2 V3

Peak Detector Circuit for Adaptive Resolution

Adaptive ADCsPeak Detector Circuit - Operation

• The operation of the peak detector circuit is described in the

table below:

• Note: C1, C2, C3 are used for PMOS devices to turn ON/OFF

and their complements are used for NMOS devices in ADC.

Input

Voltage

Condition

Code for stages (Ex:

Comparators)

Code for out stages

(Encoders & MUXs)

C1 C2 C3 A1 A2 A3

Vin<V3 1 1 0 1 1 0

Vin<V2 1 0 0 1 0 1

Vin<V1 0 0 0 0 1 1

Adaptive ADCsPeak Detector Circuit (OTA)

• A gain boosting folded cascode OTA circuit is used in peak

detector circuit to provide high gain and fast settling time i.e.,

peak detector should track input signal variations very fast and

generate digital code to inverters/buffers, encoder and

multiplexer circuits.

Adaptive ADCs

Sub-Flash Architecture

• “Sub Flash Circuit” in the design makes the ADC resolution

“Adaptive” w.r.t input signal voltage level

• Comparators and resistor-bias circuits are dynamically

controlled with digital bits generated from sub flash circuit

• Power consumption changes w.r.t resolution.

Adaptive ADCs

• Sub-flash Circuit – Block Diagram

+ _

Vin

V1

V2

V3

+ _

+ _

COMP1

COMP2

COMP3

DIG

ITA

L L

OG

IC

C3

C2

C1

Adaptive ADCs

• Operation of the Sub-flash circuit is described in Table below

• A1, A2 and A3 bits for encoder and MUX are generated from

C1, C2 and C3 bits using separate logic

Input Condition C1 C2 C3

V2>vin & V3<Vin 1 1 0

V1>vin & V2<Vin 1 0 0

V1<Vin 0 0 0

Reference Circuits for the ADC

Adaptive ADCs

Bandgap Reference Circuit (BGR)

• BGR circuit is used to generate constant reference which is

independent of process, voltage and temperature.

• The building blocks for BGR circuit are start up circuit, error

amplifier and bandgap core.

Adaptive ADCs

Bandgap Reference Circuit (BGR)

• BGR circuit involves adding two voltages that have

temperature coefficients of opposite sign with suitable

multiplication constants generating a reference voltage. The

resulting voltage obtained is independent of temperature.

• Complementary to Absolute Temperature (CTAT)

• Proportional to absolute temperature (PTAT)

• The reference voltage at the output is

BEBEout VR

RRVV

3

322

3

22 1)ln(

R

RnVV TBE

Adaptive ADCs

BGR OTA

• BGR circuit opamp is designed for high gain, fast settling and

good stability to generate a reference voltage of 1.21V with

less than 2% error.AVDD

M3

4.8u/2u

MCS22

MCS21

16u/1u

16u/1u

M5

19.2u/2u

Vbias1

Vbias2

MCS11

8u/1u

8u/1u

M1

9u/2u

M2

9u/2u

M4

4.8u/2u

AVSS

Vp VnOUT

2K

2P

MCS12

Adaptive ADCs

Voltage Regulator Circuit

• Voltage regulator circuit is used to generate V1, V2 and V3

voltages that are used in peak detector circuit to compare

analog input levels

• It consists of Error Amplifier, Pass transistor and feedback

network as shown below

+

_

R1

R2

R3

R4

AVDD

MP50U/0.3U

BGIN

V3

V2

V1

AVSS

Realization of the Adaptive Flash ADC

Components of the Adaptive Flash ADC

• Voltage Comparator (Inverter-based & comparator-

based)

• Multiplexer-based Encoder circuit

• Complete Design [Integration of blocks]

Adaptive Flash ADC

Voltage Comparator (Inverter-based)

• Comparator is the most important component in the adaptive

flash ADC architecture, shown below

Proposed Inverter & its Voltage Transfer Characteristics

Adaptive Flash ADC

Features of the Inverter

• Programmable CMOS Inverter as comparator

• It consists of controllable inputs Vctrlp and Vctrln to operate the

inverter in active or stand-by mode

• Threshold voltages of the inverters are used as reference

voltages to quantize the analog input signal

• The proposed 8-bit design has 255 CMOS inverters with

different thresholds, designed based on input dynamic range.

• At the input, the analog signal quantization level is set by Vm

that depends on the W/L ratios of PMOS and NMOS

transistors

r

VVVrV

TnTpDD

m1

|)|(with

n

p

k

kr

Adaptive Flash ADC

• PMOS & NMOS transistor dimensions for desired switching

threshold voltage

Switching Threshold Voltage PMOS Dimensions (M1) NMOS Dimensions (M2)

102.7mV 5um/0.06um 10um/0.06um

105mV 5um/0.06um 9.95um/0.06um

107.7mV 5um/0.06um 9.9um/0.06um

. . .

450mV 5um/0.06um 5u/0.06um

. . .

795mV 9.9um/0.06um 5um/0.06um

797.3mV 9.95um/0.06um 5um/0.06um

800mV 10um/0.06um 5um/0.06um

Adaptive Flash ADC

Voltage Comparator (Conventional Comparator)

C1 and C1B are used to control resolution

INP INN

BIAS

C1

From Peak

Detector

CLK

OUTN

OUTP

P1 P1 P2 P2

N1 N1

N2 N2N3

P3C1B P3 C1B

Adaptive Flash ADC

Encoder Circuit

• The Encoder circuit is based on 2:1 multiplexers connected as a

tree.

• Has Regular structure, Low Hardware cost and shortest critical

path0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

b 3

1

1

1

1

1

1

1

1

1

1

b 2

b 1 1 b 0

0

0

0

0

0

0

0

0

1

1

1

1

1

11

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

b 3

b 2

b 1

b 0

(a) (b)

S

S

S

S

A

B

B

A

(c)

Adaptive Flash ADC

Encoder Circuit

• Advantages

– Gain Boosting, Symmetry, Low leakage, Low power

dissipation and Minimum area.

• Comparison of different types of encoders.

Type of Encoder No of MUX’s Critical Path

Wallace tree 171 MUX 18 tmux

4-level folded 81 MUX 12 tmux

Multiplexer

based

57 MUX 5 tmux

Adaptive Flash ADC

C1

C2

C15

C16

C62

C63

C254

C255

4bit

6bit

8bit

Encoder

3 to 1

MUX

(8)

4

6

8

8

peak detector circuitC1 C2 C3 A3 A2 A1

Analog Input

Vin

Vin

Flash ADC Circuit (Inverter-Based)

Adaptive Flash ADC

+

_

Vin

+

_

+

_

+

_

+

_

+

_

Vref

MP1

A1

ENCODER

peak detector circuitC1C2C3 Vin

4-bit

6-bit

8-bit

A3A2A1

8

6

4

3 to 1Mux(8)

C16

C1

C15

C63

C255

C64

8

Vref

MP3

A3

Vref

MP2

A2

CLK

Vref

Flash ADC Circuit (Conventional Comparator-based)

Adaptive Flash ADC

+

_

Vin

+

_

+

_

+

_

+

_

+

_

Vref

MP1

A1

ENCODER

&

MULTIPLEXER

BIAS & SUB-FLASH BLOCKS

C1C2C3 Vin A3A2A1

C16

C1

C15

C63

C255

C64

8

Vref

MP3

A3

Vref

MP2

A2

CLK

Vref

Flash ADC Circuit (with sub-flash architecture)

Adaptive Flash ADC

Operation

• Lowest Analog Input Voltage : The control signals C1 = C2

= C3 = 0 will turn on all the 256 inverters while pattern A1=0,

A2=A3=1 will select the 8-bit encoder and the output

multiplexer such that the ADC operates as an 8-bit converter.

Thus the lowest magnitude input signal results in the ADC to

operate in 8-bit mode.

• Medium Analog Input Voltage : The control signals C1, C2,

C3 will turn on inverters from 0 to 63 while the inverters

numbered from 64 to 255 are turned off. The control signals

A1, A2 and A3 will select 6-bit encoder and output

multiplexer such that the proposed ADC operates as a 6-bit

converter.

Adaptive Flash ADC

• Highest Analog Input Voltage : The control signals C1, C2,

C3 will turn on inverters from 0 to 15 while the inverters

numbered from 16 to 255 are turned off. The control signals

A1, A2 and A3 will select 4-bit encoder and output

multiplexer such that the proposed ADC operates as a 4-bit

converter.

Two-Step Adaptive Flash ADC with peak

detector and sub-flash circuits

Two-Step Adaptive Flash ADC

• Example : 6-bit Flash ADC circuit

Two-Step Adaptive Flash ADC

• Complete Block Diagram

Adaptive Pipelined ADC with peak detector and

sub-flash circuits

Adaptive Pipelined ADC

Stage1

On Chip Digital Logic with Error

Correction Circuit

2-bit

Analog input

Clock Generator

12 bit

Peak detector block forVariable

resolution

C1

C 2

V 3

On - chip

Voltage / current

Reference bias

V2 V1

C 3

A1

A2

A 3

Stage2

V3 V2 V1

Stage3 Stage4 Stage5 Stage12AMP

C3

CS

C3C1

C1

C2

S3

S2

S1

2- bit 2 -bit 2 -bit 2-bit 2-bit

Clock

Vref

CS

CS

CS - > Complementary Switch

C1 C2

• Block diagram with peak detector

Adaptive Pipelined ADC

Stage1

On Chip Digital Logic with Error

Correction Circuit

2-bit

Analog input

Clock Generator

12 bit

Sub-Flashblock forVariable

resolution

C1

C 2

V 3

On - chip

Voltage / current

Reference bias

V2 V1

C 3

A1

A2

A 3

Stage2

V3 V2 V1

Stage3 Stage4 Stage5 Stage12AMP

C3

CS

C3C1

C1

C2

S3

S2

S1

2- bit 2 -bit 2 -bit 2-bit 2-bit

Clock

Vref

CS

CS

CS - > Complementary Switch

C1 C2

• Block diagram with sub-flash circuit

Simulation Results

Simulation ResultsBandgap Reference Circuit

Montecarlo simulation of Bandgap reference circuit for 6-sigma variation under DC-temperature sweep, withtemperature ranging from -40 °C to 125°C. The Outputreference voltage variations is +/- 3%.

Typical Reference Voltage =1.18V

Simulation Results

Bandgap Reference Circuit

AC analysis of the op-amp in the band-gap reference circuit tofind gain, phase margin and unity gain-bandwidth for PVTcorners

DC Gain=100dB, PM=65deg, UGB=24MHz

Simulation Results


• Transient analysis of the voltage regulator circuit to find

variation in V1, V2 and V3 reference voltages for PVT corners

Simulation Results


• AC analysis of the op-amp in the voltage regulator circuit to

find gain, phase margin and unity gain-bandwidth for PVT

corners


Simulation ResultsPeak Detector Circuit

• Peak Detector circuit output for three voltages required for

variable resolution of ADC

Simulation Results

Peak Detector Circuit

• AC analysis of the op-amp in the peak detector circuit to find

gain, phase margin and unity gain-bandwidth for PVT corners


Simulation Results

Flash ADC

• Transient analysis of the flash ADC has been performed by

generating a ramp input going from 0 to 2.5V. Digital codes

have been obtained correctly, going from 0 to 255 for 8-bit

output, indicating that the ADC’s working is functionally

correct.

Simulation ResultsFlash ADC

Simulation Results

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

1 12 23 34 45 56 67 78 89 100 111 122 133 144 155 166 177 188 199 210 221 232 243 254

OUTPUT CODE

DN

L (

LS

B)

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

1 12 23 34 45 56 67 78 89 100 111 122 133 144 155 166 177 188 199 210 221 232 243 254

OUTPUT CODE

INL

(L

SB

)

• DNL of the ADC in

8-bit mode is +/- 0.4.

• INL of the ADC in 8-

bit mode is +/- 0.36.

Flash ADC (DNL & INL)

Simulation Results

FFT of the ADC output sine wave is shown below from whichSNR and SNDR values have been obtained at different inputfrequency ranges

Flash ADC (SNR & SNDR)

Simulation Results

• Effective number of bits (ENOB) of the adaptive flash ADC is

given in table below

I/P Frequency ENOB for 6-bits ENOB for 8-bits

200MHz 5.45 7.65

300MHz 5.50 7.60

400MHz 5.45 7.55

500MHz 5.40 7.50

600MHz 5.35 7.45

700MHz 5.30 7.40

800MHz 5.25 7.35

Flash ADC (ENOB)

Simulation Results

Static power consumption of the adaptive flash ADC andconventional flash ADC are compared in figure below

Flash ADC (static power consumption)

Simulation Results

Characteristic

Adaptive Flash ADC

Comparator

based

8-bit ADC

4-bit 6-bit 8-bit

DNL (LSB) 0.3 0.36 0.4 0.8

INL (LSB) 0.28 0.32 0.36 0.5

Input frequency 1.6Gs/sec 1.2Gs/sec 800Ms/sec 800Ms/sec

SNR 25dB 35.2dB 47dB 44.6dB

SNDR 24.5dB 34.6dB 46.3dB 44dB

ENOB 3.77 5.45 7.4 7.0

Avg.Power(mw) 3.5mw 9mw 21.5mw 70mw

Layout Area (um2) 850 x 850 1400 x 1400

Power supply (v) 2.5 2.5 2.5 2.5

Simulation ResultsSemi Flash ADC

Simulation Results

• DNL of the ADC in

6-bit mode is +/- 0.4.

• INL of the ADC in 6-

bit mode is +/- 0.36.

Semi Flash ADC

Simulation Results

FFT of the ADC output sine-wave is plotted below from whichSNR and SNDR values have been obtained at different inputfrequency ranges

Semi Flash ADC

Simulation Results

• Effective number of bits (ENOB) of the adaptive semi-flash

ADC is given in Table below

I/P Frequency No of bits ENOB

100MHz 12 11.25

200MHz 12 11.10

300MHz 12 10.95

400MHz 12 10.80

500MHz 12 10.65

600MHz 12 10.50

Semi Flash ADC

Simulation Results

Characteristic

Inverter based Semi Flash ADC

DESIGNComparator

based

8-bit ADC

12-bit 10-bit 8-bit

DNL (LSB) 0.4 0.36 0.3 0.8

INL (LSB) 0.35 0.32 0.28 0.5

Input frequency 0.8Gs/sec 0.9Gs/sec 1Gs/sec 800Ms/sec

SNR 68.5dB 59.43dB 47.8dB 44.6dB

SNDR 66.7dB 58.35dB 46.91dB 44dB

ENOB 10.8 9.4 7.5 7.0

Avg.Power(mw) 16mw 12mw 8mw 40mw

Layout Area (um2) 650 x 650 900 x 900

Semi Flash ADC

Simulation Results

• DNL of the pipelined

ADC in 12-bit mode

is +/- 0.25.

• INL of proposed

ADC in 12-bit mode

is +/- 0.50.

Pipelined ADC

Simulation Results

The FFT of the ADC output sine-wave is plotted from whichSNDR values have been obtained

Pipelined ADC

Simulation Results

• Effective number of bits (ENOB) of the proposed ADC is

given in Table below

I/P Frequency No of bits ENOB

1KHz 12 11.5

10KHz 12 11.37

1MHz 12 11.23

10MHz 12 11.18

Pipelined ADC

Simulation Results

8-bit 10-bit 12-bit

DNL (LSB) 0.18 0.22 0.25

INL (LSB) 0.38 0.45 0.5

Input frequency 150Ms/sec 150Ms/sec 150Ms/sec

SNR 48.3dB 59.6dB 71.5dB

SNDR 47.75dB 58.46dB 69.1dB

ENOB 7.64 9.42 11.18

Power (mW) 16mW 20mW 24mW

Pipelined ADC

Characteristic

Practical Applications of Adaptive ADCs

• Adaptive Resolution of ADC is highly desirable in manywireless mobile applications. For example, the strength of aradio frequency (RF) signal varies greatly depending ongeographic location

• Resolution of the adaptive ADC will reduce upon reception ofa strong signal, and will increase for a weak signal.

• Substantial reduction of power consumption at lowerresolution will prolong the battery life for mobile devices.

Conclusion

• A novel ADC architecture with adaptive resolution has beenproposed. It employs a novel peak detector and sub-flashcircuit to achieve high performance

• The proposed ADC, designed in standard CMOS technology(65nm, thick gate process) offers higher data conversion rateswhile maintaining a comparable power consumption. Theperformance of the ADC has been studied over the process,power supply and temperature (PVT) variations

• It has application in wideband RF, wireless in local loop,radar/communications and universal computer networkadaptor, etc…

Publications• Journal

1 A. Mahesh Kumar, Sreehari Veeramachaneni, and M. B. Srinivas “A NovelLow Power, Variable Resolution Flash Analog-to-Digital Converter” J.Low Power Electronics 5, 279–290 (2009).

• Conference Papers

1 A Mahesh Kumar, Sreehari Veeramachaneni, Venkat Tummala,M.B.Srinivas, “Design of a Low Power, Variable-Resolution FlashADC", In the Proceedings of the 22nd IEEE/ACM InternationalConference on VLSI Design and Embedded Systems (VLSI DESIGN -2009),New Delhi , India, 5th -9th January 2009

2 A. Mahesh Kumar, Sreehari Veeramachaneni , M.B.Srinivas, “A NovelLow Power, Variable Resolution Pipelined Analog to DigitalConverter”, In the proceedings of the 22nd IEEE International SOCconference (IEEE SOCC 2009) 9th -11th September 2009 in Belfast,Northern Ireland, UK.

tutorial ahs11 srinivas

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