4

Tutorial Introduction

PURPOSE:– This tutorial describes the key features of the DSP56300 family of processors.

OBJECTIVES:– Describe the main features of the DSP 24-bit core.– Identify the features and functions of the 56300 peripherals and related

applications.– Describe the DSP56300 peripheral data transfer methods, I/O functions, and

memory.

CONTENTS:– 19 pages– 4 questions

LEARNING TIME:– 25 minutes

In this tutorial, we’ll examine the key features that make the DSP56300 family a market leader. In particular, we’ll examine the 24-bit core architecture, the main 56300 peripherals, and related applications. We’ll also discuss peripheral data transfers, I/O functions, and memory.

DSP Core

PLLClock

Generator

Internal DataBus

Switch

YAB

XABPAB

YDBXDBPDBGDB

MODB/IRQBMODC/IRQC

ExternalData Bus

Switch

11

MODD/IRQD

DSP56300 24-Bit

24

18

DDB

DAB

Peripheral

Core

YM_E

B

XM_E

B

PM_E

B

PI O

_ EB

Expansion Area

RESET

MODA/IRQA

PINIT/NMI

EXTALXTAL

Address

Control

Data

AddressGeneration

UnitSix ChannelDMA Unit

Data ALU24 × 24+56→ 56-bit MACTwo 56-bit Accumulators

56-bit Barrel Shifter

PowerManagement

ExternalBus

Interfaceand

I - CacheControl

Memory Expansion Area

ExternalAddress

BusSwitch

BootstrapROM

PCAP

Program Control UnitOnCE™

JTAG5

DE

Let’s begin with a look at the DSP core. The three main functional units of the core processor are the AGU, PCU, and Data ALU. Other features include clocks and the JTAG interface. Each DSP56300 device implements the DSP56300 core with a unique configuration of on-chip memory, cache, and peripherals.

The Address Generation Unit (AGU) uses integer arithmetic to calculate the effective address of address data operands in memory. It also contains the registers that generate the addresses. The AGU implements four types of arithmetic: linear, modulo, multiple wrap-around modulo, and reverse-carry.

The Program Control Unit (PCU) performs instruction pre-fetch, instruction decoding, hardware do-loop control, and exception processing.

The Data Arithmetic Logic Unit (ALU) performs all arithmetic and logical operations on data operands in the core.

The Clock/Phase Locked Loop (PLL) allows the processor to operate at a high internal clock frequency using a low frequency clock input. It reduces costs by eliminating the need for external oscillators in the system.

The Joint Test Action Group Port / On-Chip Emulator, or JTAG/OnCE, provides a means of interacting with the DSP core and its peripherals. This enables you to examine registers, memory, or on-chip peripherals, thus facilitating hardware and software development. JTAG allows the designer to perform boundary scan operations to test circuit-board electrical continuity. It provides a means of entering debug mode and various other test capabilities.

The JTAG and OnCE registers are accessible only through external signals. The registers are not memory-mapped.

Note that you can access a detailed view of the DSP56300 block diagram using the reference button on page 20.

Peripherals

The DSP I/O peripherals are shown here. These consist of an 8-bit parallel Host Interface (HI08), two Enhanced Synchronous Serial Interfaces (ESSI), a Serial Communications Interface (SCI), and a Triple Timer module.

The HI08 is a one-byte port that provides glueless communication between the DSP and a host processor for advanced input/output. The DSP56301 features a 32-bit host interface, while all other products in this family feature the HI08.

The two ESSIs are full-duplex ports used for serial communications with standard data converters, DSP's, microprocessors, and SPIs. The ESSIs provide multiplexed serial connections.

The SCI is a duplex port that supports serial communications with DSP's, controllers, and other peripherals. The SCI is used for simple input/output.

The Triple Timer module is actually three independent, general-purpose timers. These timers provide general timing and measurement functions, as well as pulse-width modulation and watchdog applications.

Each peripheral features multiple operating modes all under programmer control. Programming models contain the control and data registers used to initialize and apply each peripheral. In addition to providing industry standard interfaces, each of these peripherals can be configured to provide one or more GPIO signals, up to 34 total.

Peripheral Data Transfer Methods

• Polling– Easiest method to implement– Requires a large amount of core processing power– Core polls peripheral control registers

• Interrupts– Configure using peripheral registers– Core can process other routines while waiting for data I/O– Peripherals trigger interrupt when data is ready to be transferred– Requires additional code - interrupt service routines

• Direct Memory Access (DMA) Controller– Configured using DMA control registers– Permits data transfers and I/O without core intervention– DMA moves data to/from peripheral transmit/receive registers– Uses dedicated address and data buses and internal memory partitioning

The three methods for peripheral data transfers are polling, interrupts, and direct memory access.

Polling is the easiest method to implement. Peripheral control registers provide bits that tell the core when data is ready to be transferred to or from the peripheral. The core polls these bits to determine when to interact with the peripheral.

Since the core cannot be involved in other processing activities while it is polling, this transfer method requires a large amount of core processing power. Also, for proper operation of data transfers, the DSP56300 core must write to empty transmit buffers and read from full receive buffers.

With the interrupt method, an interrupt is generated when data is ready to be transferred to or from the peripheral device. Interrupts require more code than polling, but the core can process other routines while waiting for data I/O.

To configure interrupts, first setup the interrupt routine and then enable interrupts. Events that change bits in the peripheral control registers can then trigger the interrupt. Depending on the peripheral, two to six peripheral interrupt sources are available to the programmer.

The Direct Memory Access (DMA) controller permits data transfers between memory and I/O without intervention from the DSP56300 core. This includes data transfers from any combination of internal/external memory and internal/external I/O. Dedicated DMA address and data buses and internal memory partitioning provide a high level of isolation, so that DMA operations don’t interfere or slow down core operations.

The DMA moves data to and from the peripheral transmit and receive registers. You configure sources and destinations of data transfers using the DMA control registers. Depending on the peripheral, you will find one to four peripheral request sources available.Note that we’ll discuss the DMA Controller in more detail later in the tutorial.

Question

Which type of peripheral data transfer uses dedicated address and data buses and transfers data without core intervention? Click on your choice.

a) DMA Controllerb) Interruptsc) Polling

Let’s check your understanding of the material presented so far with a question. Which type of peripheral data transfer uses dedicated address and data buses to transfer data without core intervention? Click on your choice.

Answer: The DMA Controller transfers data without core intervention. It uses dedicated address and data buses, so that DMA operations do not interfere with core operations.

8-bit parallel Host Interface (HI08)

Next, let’s look at each peripheral in more detail, beginning with the HI08. This example shows how the DSP56300 can be used with a master processor, such as the MPC860, for voice compression through the HI08.

The HI08 interface provides glueless or minimal glue logic connection for the most popular buses and processors. It includes programmable pin polarity and functionality, including multiplex address and data buses. It also supports mixed 8-, 16-, and 24-bit data transfers.

Note that HI08 data transfers can be handled by software polling, interrupts, or DMA.

Enhanced Synchronous Serial Interfaces (ESSI)

Each ESSI is a full-duplex serial port that provides serial communication with a variety of serial devices, including industry-standard data converters, other DSPs, microprocessors, and peripherals that implement Serial Peripheral Interface (SPI). This example shows how ESSIs can be used in a video conferencing application.

The ESSI’s capabilities include:• Independent (asynchronous) or shared (synchronous) transmit and receive sections, with separate or shared internal/external clocks,• One receiver and three transmitters per ESSI,• Normal mode of operation using frame sync,• Network mode of operation with as many as 32 time slots,• Programmable word length (8, 12, 16, 24, or 32 bits), and• Program options for frame synchronization and clock generation.

Since each ESSI unit can be configured with one receiver and three transmitters, the two units can be used together for surround sound applications, which require two digital input channels and six digital output channels.

Networking the ESSI

The ESSI network mode allows more than one time slot per frame. Up to 32 data words can be transferred for each frame sync. When the ESSI is in network mode, the DC bits in Control Register A, CRA (bits 0:4), define the number of time slots per frame minus one. You can select between 2 and 32 time slots per frame.

Note that when the DC bits are cleared, the ESSI is reserved for on-demand mode, which does not generate a periodic frame sync.

Serial Communications Interface (SCI)

Next, let’s discuss the SCI.

The SCI interfaces to peripherals that use TTL-level signals without additional logic. With a small amount of additional logic, the SCI can connect to peripheral interfaces that have non-TTL level signals.

The SCI consists of separate transmit and receive sections that can operate asynchronously with respect to each other. A programmable baud-rate generator provides the transmit and receive clocks.

The figure shows a typical application of the SCI port - an analog modem. In this application, data originates in the user’s PC and enters the SCI port via the UART.

The DSP then processes and converts the data and sends it out to the ESSI port for transmission to the phone network.

Triple Timer Module

• 21-bit prescaler• 3 independent timers:

• Functions as timer or GPIO • Uses internal or external clocking• Can interrupt DSP• Can trigger DMA transfers• Can signal external device

• Timer registers• Timer Load Register (TLR)• Timer Compare Register (TCPR)• Timer Count Register (TCR)

The triple timer is composed of a common 21-bit prescaler and three independent general-purpose 24-bit timers, each with its own memory-mapped register set.

Each timer has the following characteristics: • A signal that can function as either a GPIO signal or a timer signal, • The ability to use internal or external clocking, to interrupt the DSP, or to trigger DMA transfers after a specified number of events, and• The ability to signal an external device after counting internal events.

Each timer connects to the external world through one bi-directional signal and can operate in one of several modes. When this signal is configured as an input, the timer functions as an external event counter. It can also measure the pulse width or period of the external signal. When the signal is used as an output, the timer can function as a timer, a watchdog, or a pulse width modulator.

This diagram shows the general relationship between the timer control registers and the time continuum. The timer registers include the Timer Load Register (TLR), Timer Compare Register (TCPR), and Timer Count Register (TCR). The register values can be combined in many ways to change the timer I/O signals. The waveform shown here is a pulse, but the signal can also be toggled.

To schedule an event, calculate the clock cycles required before the event and set the TLR and TCPR registers accordingly. In all modes, if the TRM bit in the TCSR is cleared, the counter operates as a free-running counter.

Question

Which of the following statements describes the ESSI port? Select all that apply and then click Done.

I) Provides glueless logic between the DSP and host processorI) Includes one receiver and four transmitters that operate asynchronouslyC) Includes programmable word lengthI) Interfaces with peripherals that use TTL logicC) Operates in normal mode or network modeC) Provides multiplexed serial connections with other DSPs

Done

Here’s another question for you. Which of the following statements describes the ESSI port? Select all that apply and then click Done.

Answer: The ESSI provides multiplexed serial connections with other DSPs. It operates in normal mode or network mode, and includes a programmable word length. Note that each ESSI includes one receiver and three transmitters.

GPIO Configuration

HI08 - 16 signalsESSI - 6 signalsESSI - 6 signalsSCI - 3 signals3 signals

Let’s continue with a look at General-Purpose I/O (GPIO). As noted earlier, all peripheral pins can be configured as GPIO for a total of 34 GPIO signals. When a peripheral is configured as GPIO, the peripheral pins are controlled by the memory-mapped port control registers. Software and hardware resets clear all control registers and configure the peripheral pins as GPIO inputs.

The ports have these GPIO signal lines:• Port B, the HI08, has 16 signals,• Port C and D, the two ESSIs, each have 6 signals,• Port E, the SCI, has 3 signals, and • The Timers have 3 signals.

Memory Expansion

Program RAM• Internal program memory• Optional 1K instruction cache• Bootstrap ROM• Optional off-chip memory expansion (up to 4M)

X Data RAM • Internal X data memory • Internal X I/O space• Optional off-chip memory expansion (up to 4M)• 4K are shared with EFCOP

Y Data RAM• Internal Y data memory• Internal Y I/O space• Optional off-chip memory expansion (up to 4M)• 4K are shared with EFCOP

Memory for the DSP56300 is located in this Memory Expansion Module. This module consists of Program RAM, X Data RAM, and Y Data RAM. The characteristics of these memory types are shown here. Both X Data and Y Data memory share memory with the EFCOP.

Note that memory can be accessed directly through the DMA and also expanded via Port A.

Direct Memory Access (DMA)

The Direct Memory Access (DMA) controller performs data transfers between:

• Internal memory (X, Y, or P)• External memory (X, Y, or P)• Internal I/O (X,Y)• External I/O (Y)

Here, we see a detailed view of the DMA Controller. The DMA has six identical DMA channels, each with its own register set mapped to X-data memory. It features programmable channel priority, so that multi-channel DMA transfers proceed in a round-robin fashion according to the programmed priority. Alternatively, the DMA can operate in continuous mode to avoid page misses for DRAM access.

The DMA also features programmable core versus DMA priorities, multiple DMA request sources, including external pins, software control, and peripherals, and mixed addressing modes for multiple types of data transfers. DMA transfers take two clock cycles per word transfer, plus any wait states for external accesses.

As noted earlier, DMA transfers can be in any combination without intervention of the core program. X, Y, and P internal memories are divided into 256-word banks, and the DMA controller and core can access different banks simultaneously without contention.

Port A Memory

• Provides connection to:– Static memory– Dynamic memory– I/O devices– Multiple bus master system

• Provides programmable wait states• Enables programmer to expand the

memory accessible to the core • Can be used to expand memory-

mapped I/O

Port A provides a low part-count connection with static memories, dynamic memories, I/O devices, and a multiple bus master system. The speed of memory access through Port A depends largely on the speed of the memory used.

Port A provides a programmable number of wait states that correspond to the specifications of the memory used. A minimum of one wait state is required for external accesses. Any other timing issues are determined by system constraints and delays.

Using Port A, the core easily accesses external memory for processing large blocks of data. The MOVE instruction accesses a single piece of data, or the DMA can be used to transfer a large block into on-chip memory for faster execution.

Enhanced Filter CoProcessor (EFCOP)

The last feature we’ll discuss is the Enhanced Filter CoProcessor (EFCOP), which is a hardware accelerator for filtering applications. It is general-purpose, fully programmable, and performs at the same frequency as the core. An example use of the EFCOP is filtering. The coprocessor performs echo cancellation independently, leaving the core to perform vocoding.

Note that the EFCOP is described in more detail in the next tutorial.

Question

Which of the following describes the HI08 general purpose signal lines? Click on your choice.

a) 8 signals through Port Ab) 16 signals through Port Bc) 6 signals through Port Dd) 3 signals through Port E

Let’s complete this tutorial with a couple of questions. Which of the following describes the HI08 general purpose signal lines? Click on your choice.

Answer: The HI08 uses 16 general purpose signal lines through Port B.

Question

Which of the following is a typical application of the SCI? Click on your choice.

a) Analog modemb) Echo cancellationc) Voice compressiond) Surround sound

Which of the following is a typical application of the SCI? Click on your choice.

Answer: A typical application of the SCI is an analog modem. Note that the EFCOP is used for echo cancellation, the HI08 is used in voice compression applications, and the ESSI is used in surround sound applications.

Tutorial Completion

• DSP 24-bit core • AGU• PCU• Data ALU• Clocks/PLL• JTAG/OnCE

• 56300 peripherals• HI08• ESSI• SCI Ports• Triple Timer Module• EFCOP

• Peripheral data transfers • GPIO and memory• DMA Controller

This concludes our overview of the DSP56300 family. In this tutorial, we discussed the key features that make the 56300 family a market leader. We looked at the 24-bit core and its main functional blocks: the AGU, PCU, and ALU, as well as clock generation and the JTAG interface.

We examined the 56300 peripherals, including typical applications, and the different peripheral data transfer methods. We also discussed I/O, memory, and the DMA controller.

DSP56300

PLLOnCE™

ClockGenerator

Internal DataBus

Switch

YAB

XABPAB

YDBXDBPDBGDB

MODB/IRQBMODC/IRQC

ExternalData Bus

Switch

11

MODD/IRQD

DSP56300

616

24-Bit

24

18

DDB

DAB

Peripheral

Core

YM_E

B

XM_E

B

PM_E

B

PI O

_ EB

Expansion Area

6

JTAG5

3

RESET

MODA/IRQA

PINIT/NMI

EXTALXTAL

Address

Control

Data

AddressGeneration

UnitSix ChannelDMA Unit

ProgramInterrupt

Controller

ProgramDecode

Controller

ProgramAddress

Generator

Data ALU24 × 24+56→ 56-bit MACTwo 56-bit Accumulators

56-bit Barrel Shifter

PowerManagement

ExternalBus

Interfaceand

I - CacheControl

Memory Expansion Area

DE

ProgramRAM

32 K × 24 bitsX DataRAM

48 K × 24 bits

Y DataRAM

48 K × 24 bits

ExternalAddress

BusSwitch

SCIInterface

EnhancedFiltering

Co-

(EFCOP)

processorESSI

InterfaceHost

Interface(HI08)

TripleTimer or

31 K × 24 bits

InstructionCache

1024 × 24 bits

BootstrapROM

PCAP

and

This is a detailed view of the DSP56300 block diagram.