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Santa Clara University School of Engineering

Department of Electrical Engineering Tutorial for Xilinx ISE 9.1i WebPACK and Xilinx Spartan 3 Prepared By: Sally Wood, PhD and Shu-Ting Lee(Fall 2007) Outline: I- Project with Xilinx Project Navigator II- Schematic with Xilinx Project Navigator III- Simulation with Xilinx ISE Simulator

IV- Hardware Description Language with Xilinx Project Navigator and Xilinx XST V- Implementation and Downloading on Xilinx Spartan 3 VI- Logic and Input/Output Blocks with Xilinx FPGA Editor VII- Xilinx Spartan 3 and Digilent Starter Board

I- Project with Xilinx Project Navigator: 1- Open Xilinx ISE 9.1i Project Navigator, you can do that either by double-clicking on the Xilinx ISE 9.1i

desktop icon, or from Start → All Programs → Xilinx ISE 7.1i → Project Navigator

Figure 1. Xilinx Project Navigator initial window

BE CAREFUL: When you open the Xilinx Project Navigator, if you have a previous project already open, then you need to close the old project and proceed with creating a new project.

2- Create a new project, from the menus bar do as follows: File → new project

Project name: tutorial Top-level source type: Schematic Project location: Student’s Z:\ or E:\ drive

2Figure 2. Naming the new project

In the next window: Family: Spartan 3

Device: xc3s200 Package: ft256 Speed grade: -4 Top-level module type: schematic Synthesis Tool: XST (VHDL/Verilog) Simulator: ISE Simulator Generated simulation language: Verilog

Figure 3. Device properties associated with the project

Source file window, just continue next → finish 3- Open a new schematic file in order to enter your circuits. Project → new source → choose schematic and put a name like: Circuit NOTE: Your top-level schematic should always be a source file. Moreover, all other files that need to be simulated, synthesized, implemented, and configured also need to be source files. There are many source file types; you will mostly use Schematic, Verilog module, and Testbench waveform source files.

HINT: If you are not sure whether you have your circuit on a regular schematic file or a schematic source file, check whether you have this schematic file appearing in a hierarchical manner under your project in the sub-window titled “sources in project”, if yes then your schematic is a source file, else you schematic is not a source file.

HINT: When you find that you have created your circuit on a regular schematic file rather than a source file, you need to create a source file, then select, copy and paste your circuit from your schematic file to the schematic source file.

BE CAREFUL: When you select, copy and paste some of your circuits from one schematic to another, sometimes the name of the wires return back to their default names, so you need to rename some of the nets all over again.

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Figure 4. Window to choose new source file type as well as file name

Figure 5. Newly created schematic source file appearing in an Hierarchical manner

4- If you want to save your schematic source file File → save, or use the toolbar icon for save. You can always use the icon next to it, save all, which saves all the changes in all the source files in your current project. BE CAREFUL: When you save a source file with the toolbar icon, make sure you have the source file that you want to save selected in the “Sources in Project” sub-window.

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II- Schematic with Xilinx Project Navigator: 1-After creating your schematic source file, you need to add the logic gates to your schematic Categories → logic, then Symbols → and2, for example (and2 is an AND gate with 2 inputs) And to add a rotated symbol: Symbol → inv, for example (inv is an inverter), then Orientation → Rotate 90

Figure 6. Menu for adding logic symbols

You can always select the used symbol on your schematic and right click, which will give you several options like copy, cut and delete, also options like zoom in or out, rotate and mirror, among others. If you double click on a component in your schematic, you will get the following pop-up window:

5Figure 7. Object Properties window which appears when double-clicking on a symbol

Later in this tutorial, you will need to access the Object Properties window of some components NOTE: If you want to gain more knowledge regarding a specific symbol, select that symbol and click on the button called Symbol Info which is located at the bottom of the sub-window from which you added the symbol. It will take you to an online documentation site courtesy of Xilinx.

Figure 8. Symbol Info button on the bottom of the Symbols sub-window

2- Add text to the page (names of the students, Lab number, Circuit Title, Date) from the tool bar

Figure 9. Add text option from the tool bar

HINT: Make sure you use large font size while adding text to your schematic, so that it can be readable when you print your schematic. You can change the font size from the following sub-window, which would show at the lower left of the interface.

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Figure 10. Add Text Options sub-window

Write the required text in the box, just like done above for circuit1, and as you move the mouse cursor, you will drag this text with it to you preferred location on your schematic. 3- Add wire as connecting nets between different symbols on your schematic, from the tool bar

Figure 11. Add wire from the tool bar

HINT: Add the symbols and circuit components first to your schematic and then make the net connections between them, this way you will avoid any dangling wires and faulty connections.

HINT: If you want to delete a net that you added to your schematic, select the net and after it becomes red you can use the delete button on your keyboard.

HINT: If you only want to delete a net segment and not the whole net connection, you have an option that needs to be change as done in the following figure.

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Figure 12. Select Options sub-window

4- Add net names to name all the wires from the tool bar

Figure 13. Add net names to the connected wires

Figure 14. Add the name of the wire and then drag and drop it on that specific wire on the schematic

HINT: If you have a set of net which have increasing set of numbers, for instance X0, X1, X2….etc. you can just write the first one on the Add Net Name Options sub-window and then increase or decrease these name numbers with the arrows on the right side of this box.

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Naming the nets is helpful when the circuit gets complicated and you do not have enough space to make a physical wire connection between two symbols, rather you can extend small wires from each symbol and give these small extensions the exact same net names. This will allow the tool to consider these extensions as part of an actual wire connection between these two symbols.

Figure 15. Connecting two symbols by just naming the nets in between

BE CAREFUL: When you use specific net names in a schematic source file, you should not use the same net names in any other schematic source file in that same project; otherwise you will basically short those wires together.

5- Add I/O markers (input and output markers), as well as, add input buffers, Ibuf, and output buffers,

Obuf, between the input and output markers and the symbols of your schematic

Figure 16. Add I/O markers to your schematic inputs and outputs

When you want to drop the I/O markers on your schematic, just click on the end-point and the tool will automatically know whether it is an input or an output. You can name the I/O markers by double-clicking on them and changing its name. BE CAREFUL: When you name the I/O marker, choose a name which is different than the net name before the Ibuf or the Obuf. If you choose the same name, you will basically short the buffer input to its output, which is considered to be a schematic error.

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Figure 17. Add ibuf and obuf between the input markers and the symbols of your schematic

Figure 18. Example of I/O markers with Ibuf and Obuf connected to and2 logic symbol

6- Add Bus connections, which is basically a wire with not only 1 bit but many bits of transmission. In order to create this bus connection, we will again benefit from the idea of making connection with naming the nets and not using any physical connections. In the figure below, we have outputted a bus of 8 bits from CB8CE, which is an 8 bit counter, and named this thick wire Q(7:0), furthermore we have used only one bit, the most significant one, Q(7), as a clock input for a second counter CB4CE, which is a 4 bit counter.

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Figure 19. Bus connection done by naming the nets

7- After adding all the symbols and making all the required connections and naming the nets, it is necessary

that you check your schematic for errors. From the menus tool bar go to: tools → check schematic NOTE: When you check your schematic for errors, and it turns out that you have wires which have errors, it is recommended to solve the problem by deleting the erroneous segment of the wire, and rewire properly.

8- Choose the right printer in your lab room and print your schematic source file as a landscape. 9- Make sure you save your work on your drive (Z:\ drive) not on the C:\ drive. NOTE: If your schematic design needs more sheet space, you can go to Edit from the menus bar, and “change sheet size”, and change the C size to an E size.

11Figure 20. Schematic properties window to change the sheet size

III- Simulation with Xilinx ISE Simulator: 1- Regarding the simulation: go to Project → new source → choose ‘Test Bench WaveForm’ as your source type. Then continue and choose the schematic source file on which you want run your simulations. 2- To explain the simulation process, here is an example of a circuit on a schematic source file

Figure 21. Logic circuit example with three inputs and 1 output, representing a 2-1 multiplexer

3- Next you will see a pop-up window just like the following:

12Figure 22. Initialize Timing window to set up the testbench properties

Make sure you do exactly like done in the previous figure. Change to falling edge, because we want to observe all the possible combination of the three input signals. This example has three inputs, which means there are 23 = 8 distinct input combinations, which explains the reason you should choose ‘Initial Length of Test Bench’ to be 800 nsec, as well as ‘Clock Time High’ and ‘Clock Time Low’ to be 100 nsec. Moreover, in the Clock Information section, select Single Clock, this would be one of the input signals in the circuit.

Figure 23. Initial timing diagram which appears after the Initialize timing window

4- After your testbench source file is opened and you can notice the above timing diagram, you have to click on the timing diagram for each input and change its values, so that at the end you will have all the input combinations, in this example, all the input combinations start from 000 to 111. As shown on the figure below:

Figure 24. Instances where the inputs need to make transitions from high to low, and from low to high

Figure 25. All input combinations starting from 000 to 111

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5- After making sure you have added all the input values, save your testbench source file. NOTE: If your testbench does not appear in the hierarchy of source file in the sub-window ‘Sources in Project’ that means you have not saved you testbench, which you need to do in order to proceed with your simulation.

6- In the Sources window, select the Behavioral Simulation view to see that the test bench waveform file is automatically added to your project. In the Processes tab, click the “+” to expand the Xilinx ISE Simulator process and double-click the Simulate Behavioral Model process.

Figure 26. Behavior Simulation Selection

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Figure 27. Simulating Design

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7- To view your simulation results, select the Simulation tab

Figure 28. Correct simulation result at the output

In the simulation mode you will see the following icons, which you can use:

Figure 29. Explained simulation mode taskbar buttons

IV- Hardware Description Language with Xilinx Project Navigator and Xilinx XST 1- When creating a new project, remember that in the Project Properties window, you need to specify the ‘Preferred Language’ to the Hardware Description Language (HDL) of your choice, in the following window it is Verilog.

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Figure 30. New project properties window showing the Preferred Language as Verilog

2- After creating the project, go to Project from the menus tool bar → New Source → select Verilog Module

as your source type and name your file. As an example, we will design a full adder module and instantiate it in a 4 bit adder module.

Figure 31. New source file window with a Verilog Module file type

3- When you continue with Next you will encounter a window for defining your Verilog source file inputs

and outputs.

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Figure 32. Defining the Verilog source file inputs and outputs for the full adder

4- The Verilog code for a full adder is shown in the next figure; this code is in a structural level

representation. A full adder is basically an adder with 3 inputs and 2 outputs. The inputs consist of the two 1 bit primary inputs which need to be added as well as the carry in, and the outputs are the 1 bit sum output as well as the carry out.

Figure 33. Verilog module of a full adder

5- To check if you have any syntax errors in your Verilog code, go to the Process View options window → Synthesis XST → Check Syntax (Double Click).

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Figure 34. Check Syntax

6- After creating a Verilog source file for the full adder, we need to create a Verilog source file in the same

manner for the 4 bit adder. In this 4 bit adder we will instantiate 4 full adders. The difference between these two source files is clear in the following figure. When we define the inputs for the 4 bit adder module we need to specify the number of bits for our inputs and outputs, in this case 4 bits, which can be translated as an array from 0 to 3, having 0 as the least significant bit (LSB), and the 3 as the most significant bit (MSB).

Figure 35. Defining the Verilog source file inputs and outputs of the 4 bit adder

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In the 4 bit adder we have three inputs and 3 outputs. The inputs consist of the two 4 bit numbers as well as the carry in, and the outputs consist of the 4 bit sum output as well as the carry out and the overflow output.

Figure 36. Verilog module of a 4 bit adder

7- In order to use the 4 bit adder in our top level schematic, we need to go to the “Process View” options list

and from “Design Utilities”, choose Create Schematic Symbol. With this step you create a symbol for your 4 bit adder so that you can use it in a schematic source file. You can open the “*.sym” form menu File → Open.

Figure 37. Schematic symbol created from the 4 bit adder Verilog module

BE CAREFUL: Every time you go back and make a change in your HDL file, you need to redo the step of creating a schematic symbol.

NOTE: After you make changes to your HDL file and create a new schematic symbol, when you go back to your schematic file, you will notice that the tool will ask you whether you want to update the changed symbol.

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8- Because we have instantiated 4 full adder module in the 4 bit adder code, notice that in the Sources, in the

project options window, you have created a little hierarchy tree, with the 4 bit adder source being the parent of the full adder sources.

Figure 38. Hierarchy of the project source files

9- In order to use the created schematic symbol in the top level schematic source file, open the tab where you

can choose Symbols → from Categories choose <Z:\your project folder> → from Symbol choose myAdder4. Drag this new symbol and use it in your top level schematic source file. Notice that after you save all these source files you will see a hierarchy like shown above.

Figure 39. Use the created symbol

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V- Implementation and Downloading on Xilinx Spartan 3: 1- After creating a schematic source file, which has the logic circuit with all the Ibuf’s and Obuf’s and the

corresponding I/O markers, select these buffers, double click on them and you will get the following pop-up window:

Figure 40. Buffer properties window

2- On the above figure notice that we don’t have an attribute called LOC, (which stands for location), thus you

need to create that new trait → go to new → attribute name: LOC, attribute value: K13, attribute value type: string, as explain in the following figure.

21Figure 41. Creating a new attribute, LOC, for a buffer

3- Connect the Xilinx Spartan 3 FPGA board to the computer as well as to the power outlet. BE CAREFUL: When connecting the JTAG connection to its port on the Digilent board, make sure you have the names of the pins on the connection match the ones on the port.

HINT: From the Process View sub-window right-click on the ‘Generate Programming File’ and select the ‘Properties’ you will get a pop-up window like shown below. Under ‘Readback Options’ select “Enable Readback and Reconfiguation’ and check the rest of the values.

Figure 42. Changing the start up clock to a JTAG clock

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4- In order to download your schematic design on the board, you need to undergo the final configuration of your design → from the Process View options scroll down till the end → double click Configure Device (iMPACT) → You will get a pop-up window called configure device → choose Boundary Scan Mode, shown in the following set of figures.

Figure 43. Configure Device (iMPACT) from the Processes to source sub-window

Figure 44. Pop-up window appearing while configuring a device,

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5- After clicking the ‘Finish’ in last figure, you will be asked to assign the configuration file (the .bit file) for

device ‘xc3s200’ by a pop-up, and for the second device ‘xcf02s’just click on the Bypass button, as shown in the following figures.

Figure 45. Choosing the .bit configuration file for the first device

Figure 46. Choosing Bypass for the second device

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6- Select the xc3s200 .bit device → go to Operations from the menus bar → Program → ok

Figure 47. Program options window for the first device

Figure 48. Program was downloaded successfully on the Digilent Spartan 3 Board

NOTE: When you get “Programming Failed” try to program again, most of the time it programs successfully the second time you try. If not, make sure the connection is place properly, and also that you have chosen the right .bit file for the first device, and of course that you are using the right device, in our case the xc3s200.

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7- Again from the Process View window of options → implement Design → place and route → Place and Route report (PAR) double click on that and you will get a report file

Figure 49. Place and Route Report (PAR) option from the process view sub-window

try to locate the device utilization summary → you usually need to find out how many input/output buffers (IOB) and logic block slices you have used, also make sure you check that you have no errors, as seen in the following figure.

Figure 50. Part of the Place and Route report showing the number of IOB’s and Slices used

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VI- Logic and Input/Output Blocks with Xilinx FPGA Editor: 1- You need to examine your implementation by going to FPGA Editor (from the start menu → Xilinx ISE

9.1i → accessories or from the process view sub-window options) you will get the following window:

Figure 51. Xilinx FPGA Editor graphical user interface

2- Go to file → open and browse → go to your project folder and choose the file which has the name of your

schematic that you did and an extension .ncd as shown in the figure below

Figure 52. Opening a design with Xilinx FPGA Editor

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3- From the list 1 window change the all components option in the scroll box to routed nets, select one of the

nets and then zoom in, in order to find out the route of the specified net. The specified net would turn red when selected.

Figure 53. Close view of a selected logic slice

4- If you place the cursor of your mouse on one of the red or blue blocks it will tell you if it is a Slice (logic block) or an IOB (input/output block) with its specific number. Double click on these blocks and you will get a window like the following (this one is the window after selecting a Slice):

Figure 54. Inside a slice, which includes two Look-up tables (LUT) and two flip flops

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Notice, in this block, we have two look-up tables (LUT) and two flip flops, if you leave the cursor of the mouse on an LUT or if you click on an LUT, you will get its logic function. LUT set the logic functions, while the flip-flops act as storage elements.

Figure 55. Close-up view for a set of one LUT and one Flip flop with all their surrounding circuitry

But if you select an IOB and double click, you will get a window like the following figure.

Figure 56. Inside an input/output block

The inside view of a logic slice is completely different from that of a IOB.

HINT: When getting the equation (logic function) of an LUT, the @ sign symbolizes an XOR, and the ~ sign symbolizes an inverse.

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VII- Xilinx Spartan 3 and Digilent Starter Board: The Xilinx Spartan 3 field programmable gate arrays (FPGA) are the most commonly used educational logic device families. The Xilinx Spartan 3 FPGA used in this introductory logic design lab is mounted on the Digilent Starter board, which has many student-friendly features and attributes. The following picture courtesy of Digilent and Xilinx shows the essential parts of this board.

Figure 57. Essential parts on an Digilent Xilinx Spartan 3 Starter Board

The following are helpful resources for further incite: Spartan-3 Starter Kit Board User Guide Xilinx ISE 9.1 Software Manuals and Help – PDF Collection

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