uart interface

8/3/2019 Uart Interface

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Interfacing Serial RS-232 with FPGA

Introduction

This lab will be an introduction on how to establish an interconnection between PC and FPGA kit

through serial RS-232 interface using hyper terminal available on the laptop/PC.

Objective

The objective is to control the frequency of a simple 4-bit counter through RS-232 port using hyper-

terminal. The counter implemented here is a 4-bit counter operated at five different frequencies. Here

to show the user a method to interface a laptop or PC with an FPGA kit using available RS-232 port onthe board with appropriate interactive signals. WISHBONE protocol is employed in the present labto

establish the communication.

4-bit Counter Design Overview

The 4-bit counter is implemented at five different frequencies using the system clock running at 50

Mhz. The frequencies are50Mhz

23

,50Mhz

223

,50Mhz

224

,50Mhz

225

,50Mhz

226

, (the frequencies

are chosen to make the counter action visible through the LEDs, except for the highest frequency whichis solely to verify the design in the Xilinx Simulator).

The frequencies are controlled using input signal FREQUENCY which in turn is controlled using the

five keys (1, 2, 3, 4 & 5) on the keyboard.The output of the 4-bit counter is connected to four of the available seven LEDs (LD0, LD1, LD2,

LD3).An asynchronous reset is also provided to the design which is connected to one of the sliding switches(SW0).

The UART core is taken from http://www.opencores.org/?do=project&who=muart.

RS-232 Serial Interface

1.Characteristics Uses a 9 pin connector DB-9 (older PCs use 25 pins DB-25 and newer laptops do not have

serial port anymore, so a USB to serial converter is required). Allows bidirectional full-duplex communication (the PC can send and receive data at the same

time).

Can communicate at a maximum speed of roughly 10KBytes/s.


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2.DB-9 Connector

DB-9 connector (male) appears as shown in Figure 1.

Figure 1: DB-9 Connector

The pin numbering on the connector is as follows:

Figure 2: Pin Numbering (male connector)

Figure 3: Pin Numbering (female connector)


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Pin Description of RS-232 male connector:

Pin

No.

Name Dir Notes/Description

1 DCD IN Data Carrier Detect. Raised by DCE when modem synchronized.

2 RD IN Receive Data (RD, Rx). Arriving data from DCE.3 TD OUT Transmit Data (TD, Tx). Sending data from DTE.

4 DTR OUT Data Terminal Ready. Raised by DTE when powered on. In auto-answer mode raised only when RI arrives from DCE.

5 GND - Ground

6 DSR IN Data Set Ready. Raised by DCE to indicate ready.

7 RTS OUT Request To Send. Raised by DTE when it wishes to send. Expects

CTS from DCE.

8 CTS IN Clear To Send. Raised by DCE in response to RTS from DTE.

9 RI IN Ring Indicator. Set when incoming ring detected - used for auto-answer application. DTE raised DTR to answer.

Table 1: Pin Description (male connector)

The three important ones among the 9 pins are:

pin 2: RD (receive data).

pin 3: TD (transmit data). pin 5: GND (ground).

Using just 3 wires, one can send and receive data.

3.Serial Communication

Data is sent one bit at a time. One wire is used for each direction. Since computers usually need at leastseveral bits of data, the data is serialized before being sent. Data is commonly sent by chunks of 8 bits.

The LSB (data bit 0) is sent first, the MSB (bit 7) last.

4.Asynchronous Communication

This interface uses an asynchronous protocol which means that no clock signal is transmitted alongwith data. The receiver has to have a way to time itself to the incoming data bits. In the case of RS-232,

it is done in the following way:


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1. Both side of the cable agree in advance on the communication parameters (parameters shown inFigure 4). It is done manually before communication starts (which will be explained later).

Figure 4: Serial Communication Parameters

2. The transmitter sends a "1" when the line is idle.3. The transmitter sends a "start" (a "0") before each byte is transmitted, so that the receiver can

understand that data is coming.

4. After the "start", data comes in with the agreed speed and format, so the receiver can interpretit.

5. The transmitter sends a "stop" (a "1") after each data byte.

For example, a 0x55 byte when transmitted appears in the following way:

Figure 5: 0x55 Byte Transmission

Byte 0x55 is 01010101 in binary.

But since it is transmitted LSB (bit-0) first, the line toggles like that: 1-0-1-0-1-0-1-0.

Another example:


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Figure 6: 0xC4 Byte Transmission

Here the data is 0xC4, which is difficult to interpret. It an illustration to show how important it is forthe receiver to know at which speed the data is sent.

5.Operation Speed

The speed is specified in baud, i.e. how many bits-per-seconds can be sent. For example, 1000 bauds

would mean 1000 bits-per-seconds, or that each bit lasts one millisecond.

Common implementations of the RS-232 interface (like the one used in PCs) do not allow just any

speed to be used. One has to settle to some "standard" speed.Common values are:

1200 bauds.

9600 bauds.

38400 bauds.

115200 bauds.

At 115200 bauds, each bit lasts (1/115200) = 8.7s. If one transmits 8-bit data, it lasts for 8 x 8.7s =

69s. But each byte requires an extra start and stop bit, so one actually needs 10 x 8.7s = 87s. Thattranslates to a maximum speed of 11.5 KBytes per second.

At 115200 bauds, some PCs with faulty chips require a "longer" stop bit (1.5 or 2 bits long) whichmakes the maximum speed drop to around 10.5KBytes per second.

6.Physical Layer

The signals on the wires use a positive/negative voltage scheme.

"1" is sent using -10V (or between -5V and -15V).

"0" is sent using +10V (or between 5V and 15V).

So an idle line carries something like -10V.

WISHBONE Protocol

The WISHBONE System-on-Chip (SoC) Interconnect Architecture is a portable interface for use with

semiconductor IP cores. Its purpose is to foster design reuse by alleviating system-on-a-chip integration


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problems. It is accomplished by creating common logical interfaces. This improves the portability and

reliability of the system, and results in faster time-to market for the end user. WISHBONE is not an IPcore but is a specification for creating IP cores.

WISHBONE System-on-Chip Interconnect protocol can be used as an interface to all cores that require

interfacing to other cores inside a chip (FPGA, ASIC, etc.). The WISHBONE architecture sits betweenthe PC and UART interface as shown below in Figure 7.

Figure 7: System Block Diagram

The WISHBONE protocol is a set of handshake signals carried out in a systematic exchange fashion inorder to maintain synchronization between two systems.

The handshake signals and their respective order as used in this protocol are as shown below in Figure8.

PC UART FPGA

WISHBONEProtocol

SerialCommunication


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Figure 8: WISHBONE Protocol Signal Exchange

Present UART Design Description

This UART (Universal Asynchronous Receiver Transmitter) is designed to make aninterface between a RS-232 line and a WISHBONE bus.

It is built to be very small (to fit in small FPGAs), but also efficient.It is not suited to interface a modem as there is no control handshaking (CTS/RTS).

It integrates two separate clocks, one for WISHBONE bus, the other for bit stream generation.

This has the advantage to let the user operate at any desired frequency (limited only by RS-232interface) for the baud rate. There are full functionality UARTs available on opencores.com but the full

functionality is not required for this lab. For this lab, the proposed light UART will be sufficient.

Design supports:1. WISHBONE interface in 8-bit data bus

2. Two clocks: one for WISHBONE interface, one for RS-232 bit stream generation3. Baud rate divisor from 1 to 65536 (generic parameter set at integration time)

Design does not support:1. FIFO input/output2. Control handshaking

Rx_int = 1

Tx_int = 1

STB = 1

WR = 1

ADDR = 00

DATA = XX

ACK = 1

STB = 0

ACK = 0

SYSTEM UART

Last ACK signal is not implemented in theWISHBONE State Machine of the present design


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IO Ports:

WISHBONE Interface Signals:

Port Width Direction Description

WB_CLK_I 1 Input Blocks clock input

WB_RST_I 1 Input Asynchronous ResetWB_ADDR_I 2 Input Used for register selection

WB_DAT_I 8 Input Data input

WB_DAT_O 8 Output Data output

WB_WE_I 1 Input Write or read cycle selection

WB_STB_I 1 Input Specifies transfer cycle

WB_ACK_O 1 Output Acknowledge of a transfer

Table 2: WISHBONE Interface Signals

Other Internal Signals:


IntTx_O 1 Output Transmit Interrupt

IntRx_O 1 Output Receive Interrupt

BR_CLK_I 1 Output Clock for serialisation/unserialisation

Table 3: Other Internal Signals

External (off-chip) Connections:


TxD_PAD_O 1 Output The serial output signal

RxD_PAD_I 1 Input The serial input signal

Table 4: External Connections

Clocks:

Name Source Rates (MHz) Remarks Description

Max Min Resolution

WB_CLK_I WISHBONEbus

Limitedby target

host

None WISHBONE clock

BR_CLK_I User None Baudrate clock

Table 5: Clocks


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Registers:

1. Register List:

Name Address Width Access Description

Receive buffer 0 8 R Contain byte received

Transmit buffer 0 8 W Contain byte to transmitStatus 1 8 R Receive buffer full / Transmitter busy

Reserved 2 8

Reserved 3 8

Table 6: Register List

2. Status Register:

Bit # Access Description

0 R Transmitter buffer state = IntTx_O pin0 Busy. Cant accept incoming byte

1 Accept a byte to transmit

1 R Receiver buffer state = IntRx_O pin0 Buffer empty

1 Buffer contain a received byte

Table 7: Status Register

Reset Value: XXXXXX01b


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UART Design Operation

The UART Operation is very basic:

Upon a write to the data input bus WB_DAT_I, the core will automatically serialize and emit the byteon the TxD_PAD_O. It will hold IntTx_O low as long as it cannot accept an incoming byte. Therefore

a rising edge on IntTx_O can trigger the interrupt line of a microcontroller to emit another byte.Upon reception of a bit stream on RxD_PAD_O, the core will de-serialise the information and assertIntRx_O pin. This announces that the received byte can be read on the data output bus WB_DAT_O. As

soon as the byte is read, IntRx_O is negated.

WISHBONE Bus

The design is 8-bit WISHBONE compatible. It doesnt use the WB_CYC_I pin as it will never insert

wait states.

Initialization

The design doesnt need to be reset, as it is ready to use upon power on.However, a synchronous assertion of WB_RST_I will abort any pending transmit/receive and will set

the core in idle state.

Baudrate Divisor

A generic VHDL parameter allows the user to introduce a divisor between BR_CLK_I clock and the bit

stream frequency. In addition, the core inserts a 4 divisor for sampling purpose for the receiver.

Thus:Baudrate = Freq(BR_CLK_I) / BRDIVISOR / 4

where BRDIVISOR is the generic parameter.

For example to instantiate the component in a VHDL unit, write:

U1 : MiniUART

generic map (BRDIVISOR => 103)port map (clk, rst, adr, ...);

for a division of 103.


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Below are given some divisor values for common baudrates:

Baudrate tolerance:

The receiver will accept a slight variation between the expected baudrate and the effective bit stream

baudrate that is:

Min freq Nominal Baudrate -2.60%

Max freq Nominal Baudrate +5.90%

Equivalent in period :

Min period Nominal period -5.90%Max period Nominal period +2.60%

Going beyond these limits will make the receiver unable to de-serialise correctly (illustrated in Figure 9).

BRDIVISOR Baudrate

2080 1200

1040 2400

520 4800

260 9600

130 19200

65 38400

BR_CLK_I at 10MHz

BRDIVISOR Baudrate

192 2400

96 4800

48 9600

32 14400

24 19200

16 28800

8 57600

4 115200

2 230400

1 460800

BR_CLK_I at 1.8432MHz

Start Bit 0 Bit 1 Bit 2 Bit 3 Bit 4

+2.6%

Bit 6 Bit 7 Stop

Byte

0x42

-5.9%

Bit 5

Nominal expected

baudrate

Max period for the

bit stream

Min period for the

bit stream


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Figure 9: Baudrate Tolerance Margin Illustration


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Architecture

The block diagram of the design is as given:

Figure 10: Block Diagram of the System Design

WISHBONE

BusinterfaceWISHBONE

SIGNALS

Transmitter

ReceiverRxD_PAD_I

TxD_PAD_O

%4

BR_CLK_I

IntTx_O

IntRx_O

Baudrate

Divisor


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Initial Set-up and Output

Connect the Digilent Spartan-3E kit to a laptop/PC as shown below.

Figure 11: USB Connection

Then connect the serial port (DCE terminal) available on the FPGA board to the another USB port

available on the laptop/PC using a USB-to-Serial converter as shown below.

Figure 12: USB-to-Serial Converter


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Figure 13: RS-232 Interface

Switch on the board and configure the device using the Xilinx ISE 10.1 tool.

Open the hyper terminal as shown below.


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Figure 14: Hyper Terminal Path


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The following window will pop up.

Figure 15: Hyper Terminal

Give an appropriate name and press OK. Then the following window will show up. Select theappropriate com port and press OK.

Figure 16: Com Port Selection


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The following window will show up. Make the port settings as shown below or set the baudrate to a

desired rate depending on the design parameters. As the baudrate in the present design is configured for9600 baud, the following settings are been chosen.

Figure 17: Hyper Terminal Settings

Once the port settings are made press OK and the following terminal will show up. Now try pressing

any of the following five keys: 1, 2, 3, 4 & 5 and observe the change in the frequency of the

counter by looking at the four LEDs (LD0, LD1, LD2 & LD3) operation speed.


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Figure 18: Output

uart interface

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