uc3844b, uc3845b, uc2844b, uc2845b high performance … · mount (soic−8) plastic package as well...

© Semiconductor Components Industries, LLC, 2013

August, 2013 − Rev. 111 Publication Order Number:

UC3844B/D

UC3844B, UC3845B,UC2844B, UC2845B

High PerformanceCurrent Mode Controllers

The UC3844B, UC3845B series are high performance fixed frequencycurrent mode controllers. They are specifically designed for Off−Lineand dc−dc converter applications offering the designer a cost−effectivesolution with minimal external components. These integrated circuitsfeature an oscillator, a temperature compensated reference, high gainerror amplifier, current sensing comparator, and a high current totem poleoutput ideally suited for driving a power MOSFET.

Also included are protective features consisting of input andreference undervoltage lockouts each with hysteresis, cycle−by−cyclecurrent limiting, a latch for single pulse metering, and a flip−flopwhich blanks the output off every other oscillator cycle, allowingoutput deadtimes to be programmed from 50% to 70%.

These devices are available in an 8−pin dual−in−line and surfacemount (SOIC−8) plastic package as well as the 14−pin plastic surfacemount (SOIC−14). The SOIC−14 package has separate power andground pins for the totem pole output stage.

The UCX844B has UVLO thresholds of 16V (on) and 10V (off), ideallysuited for off−line converters. The UCX845B is tailored for lower voltageapplications having UVLO thresholds of 8.5V (on) and 7.6V (off).Features• Trimmed Oscillator for Precise Frequency Control• Oscillator Frequency Guaranteed at 250 kHz• Current Mode Operation to 500 kHz Output Switching Frequency• Output Deadtime Adjustable from 50% to 70%• Automatic Feed Forward Compensation• Latching PWM for Cycle−By−Cycle Current Limiting• Internally Trimmed Reference with Undervoltage Lockout• High Current Totem Pole Output• Undervoltage Lockout with Hysteresis• Low Startup and Operating Current• These Devices are Pb−Free and are RoHS Compliant

• NCV Prefix for Automotive and Other Applications RequiringUnique Site and Control Change Requirements; AEC−Q100Qualified and PPAP Capable

Pin numbers in parenthesis are for the D suffix SOIC-14 package.

Output

VC

RT/CT

VrefVCC

UndervoltageLockout

GND

5.0VReference

VrefUndervoltage

Lockout

LatchingPWM

Oscillator

ErrorAmplifier

5(9)

3(5)

5(8)

6(10)

7(11)

PowerGround

CurrentSense Input

1(1)

2(3)

4(7)

8(14)

Output/Compensation

VoltageFeedback

Input

VCC 7(12)

R

R

Figure 1. Simplified Block Diagram

14

SOIC−14D SUFFIX

CASE 751A1

See detailed ordering and shipping information in the packagedimensions section on page 15 of this data sheet.

ORDERING INFORMATION

See general marking information in the device markingsection on page 16 of this data sheet.

DEVICE MARKING INFORMATION

1

8

PDIP−8N SUFFIXCASE 626

PIN CONNECTIONS

Compensation

NCVoltage Feedback

NCCurrent Sense

NCRT/CT

CompensationVoltage Feedback

Current SenseRT/CT

Vref

Vref

NCVCC

VCOutputGNDPower Ground

VCC

OutputGND

(Top View)

8

7

6

5

1

2

3

4

1

2

3

4

14

13

12

11

5

6

7

10

9

8

(Top View)

SOIC−8D1 SUFFIXCASE 751

1

8

http://onsemi.com

UC3844B, UC3845B, UC2844B, UC2845B

http://onsemi.com2

MAXIMUM RATINGS

Rating Symbol Value Unit

Bias and Driver Voltages (Zero Series Impedance, see also Total Device spec) (Note 1) VCC, VC 36 V

Total Power Supply and Zener Current (ICC + IZ) 30 mA

Output Current, Source or Sink (Note 2) IO 1.0 A

Output Energy (Capacitive Load per Cycle) W 5.0 �J

Current Sense and Voltage Feedback Inputs Vin − 0.3 to + 5.5 V

Error Amp Output Sink Current IO 10 mA

Power Dissipation and Thermal CharacteristicsD Suffix, Plastic Package, SOIC−14 Case 751A

Maximum Power Dissipation @ TA = 25°CThermal Resistance, Junction−to−Air

D1 Suffix, Plastic Package, SOIC−8 Case 751Maximum Power Dissipation @ TA = 25°CThermal Resistance, Junction−to−Air

N Suffix, Plastic Package, Case 626Maximum Power Dissipation @ TA = 25°CThermal Resistance, Junction−to−Air

PDR�JA

PDR�JA

PDR�JA

862145

702178

1.25100

mW°C/W

mW°C/W

W°C/W

Operating Junction Temperature TJ +150 °C

Operating Ambient Temperature UC3844B, UC3845BUC2844B, UC2845B

UC3844BV, UC3845BV

TA 0 to +70−25 to +85−40 to +105

°C

Storage Temperature Range Tstg − 65 to +150 °CStresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above theRecommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affectdevice reliability.1. The voltage is clamped by a zener diode (see page 9 Under Voltage Lockout section). Therefore this voltage may be exceeded as long as

the total power supply and zener current is not exceeded.2. Maximum package power dissipation limits must be observed.3. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per JEDEC Standard

JESD22-A114B, Machine Model Method 200 V per JEDEC Standard JESD22-A115-A4. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78

ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 5], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max valuesTA is the operating ambient temperature range that applies [Note 6], unless otherwise noted.)

UC284xB UC384xB, xBV, NCV384xBV

Characteristic Symbol Min Typ Max Min Typ Max Unit

REFERENCE SECTION

Reference Output Voltage (IO = 1.0 mA, TJ = 25°C) Vref 4.95 5.0 5.05 4.9 5.0 5.1 V

Line Regulation (VCC = 12 V to 25 V) Regline − 2.0 20 − 2.0 20 mV

Load Regulation (IO = 1.0 mA to 20 mA) Regload − 3.0 25 − 3.0 25 mV

Temperature Stability TS − 0.2 − − 0.2 − mV/°C

Total Output Variation over Line, Load, & Temperature Vref 4.9 − 5.1 4.82 − 5.18 V

Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C) Vn − 50 − − 50 − �V

Long Term Stability (TA = 125°C for 1000 Hours) S − 5.0 − − 5.0 − mV

Output Short Circuit Current ISC − 30 − 85 −180 − 30 − 85 −180 mA

OSCILLATOR SECTION

Frequency TJ = 25°CTA = Tlow to Thigh

TJ = 25°C (RT = 6.2 k, CT = 1.0 nF)

fOSC 4948225

52−

250

5556275

4948225

52−

250

5556275

kHz

Frequency Change with Voltage (VCC = 12 V to 25 V) �fOSC/�V − 0.2 1.0 − 0.2 1.0 %

Frequency Change w/ Temperature (TA = Tlow to Thigh) �fOSC/�T − 1.0 − − 0.5 − %

Oscillator Voltage Swing (Peak−to−Peak) VOSC − 1.6 − − 1.6 − V

5. Adjust VCC above the Startup threshold before setting to 15 V.6. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

Tlow = 0°C for UC3844B, UC3845B Thigh = + 70°C for UC3844B, UC3845B= − 25°C for UC2844B, UC2845B = + 85°C for UC2844B, UC2845B= − 40°C for UC384xBV, NCV384xBV =+105°C for UC3844BV, UC3845BV

= +125°C for NCV384xBV

UC3844B, UC3845B, UC2844B, UC2845B

http://onsemi.com3

ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 7], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max valuesTA is the operating ambient temperature range that applies [Note 8], unless otherwise noted.)

UC284xB UC384xB, xBV,NCV384xBV


OSCILLATOR SECTION

Discharge Current (VOSC = 2.0 V) TJ = 25°CTA = Tlow to Thigh (UC284XB, UC384XB)

(UC384XBV)

Idischg 7.87.5−

8.3−−

8.88.8−

7.87.67.2

8.3−−

8.88.88.8

mA

ERROR AMPLIFIER SECTION

Voltage Feedback Input (VO = 2.5 V) VFB 2.45 2.5 2.55 2.42 2.5 2.58 V

Input Bias Current (VFB = 5.0 V) IIB − − 0.1 −1.0 − − 0.1 − 2.0 �A

Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) AVOL 65 90 − 65 90 − dB

Unity Gain Bandwidth (TJ = 25°C) BW 0.7 1.0 − 0.7 1.0 − MHz

Power Supply Rejection Ratio (VCC = 12 V to 25 V) PSRR 60 70 − 60 70 − dB

Output Current − Sink (VO = 1.1 V, VFB = 2.7 V)Output Current − Source (VO = 5.0 V, VFB = 2.3 V)

ISinkISource

2.0− 0.5

12−1.0

−−

2.0− 0.5

12−1.0

−−

mA

Output Voltage SwingHigh State (RL = 15 k to ground, VFB = 2.3 V)Low State (RL = 15 k to Vref, VFB = 2.7 V)

(UC284XB, UC384XB)(UC384XBV)

VOHVOL

5.0

−−

6.2

0.8−

−

1.1−

5.0

−−

6.2

0.80.8

−

1.11.2

V

CURRENT SENSE SECTION

Current Sense Input Voltage Gain (Notes 9 & 10)(UC284XB, UC384XB)(UC384XBV)

AV2.85−

3.0−

3.15−

2.852.85

3.03.0

3.153.25

V/V

Maximum Current Sense Input Threshold (Note 9)(UC284XB, UC384XB)(UC384XBV)

Vth0.9−

1.0−

1.1−

0.90.85

1.01.0

1.11.1

V

Power Supply Rejection Ratio (VCC = 12 V to 25 V) (Note 9) PSRR − 70 − − 70 − dB

Input Bias Current IIB − − 2.0 −10 − − 2.0 −10 �A

Propagation Delay (Current Sense Input to Output) tPLH(In/Out) − 150 300 − 150 300 ns

OUTPUT SECTION

Output VoltageLow State (ISink = 20 mA)

(ISink = 200 mA, UC284XB, UC384XB)(ISink = 200 mA, UC384XBV)

High State (ISource = 20 mA, UC284XB, UC384XB)(ISource = 20 mA, UC384XBV)(ISource = 200 mA)

VOL

VOH

−−−13−12

0.11.6−

13.5−

13.4

0.42.2−−−−

−−−13

12.912

0.11.61.613.5−

13.4

0.42.22.3−−−

V

Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 1.0 mA) VOL(UVLO) − 0.1 1.1 − 0.1 1.1 V

Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C) tr − 50 150 − 50 150 ns

Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C) tf − 50 150 − 50 150 ns

UNDERVOLTAGE LOCKOUT SECTION

Startup Threshold UCX844B, BVUCX845B, BV

Vth 157.8

168.4

179.0

14.57.8

168.4

17.59.0

V

Minimum Operating Voltage After Turn−On UCX844B, BVUCX845B, BV

VCC(min) 9.07.0

107.6

118.2

8.57.0

107.6

11.58.2

V

7. Adjust VCC above the Startup threshold before setting to 15 V.8. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

Tlow = 0°C for UC3844B, UC3845B Thigh = + 70°C for UC3844B, UC3845B= − 25°C for UC2844B, UC2845B = + 85°C for UC2844B, UC2845B= − 40°C for UC384xBV, NCV384xBV = +105°C for UC3844BV, UC3845BV

= +125°C for NCV384xBV9. This parameter is measured at the latch trip point with VFB = 0 V.10.Comparator gain is defined as: AV = �V Output/Compensation

�V Current Sense Input

UC3844B, UC3845B, UC2844B, UC2845B

http://onsemi.com4

ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 11], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/maxvalues TA is the operating ambient temperature range that applies [Note 12], unless otherwise noted.)

UC284xB UC384xB, xBV, NCV384xBV


PWM SECTION

Duty CycleMaximum (UC284XB, UC384XB)Maximum (UC384XBV)Minimum

DC(max)

DC(min)

47−−

48−−

50−0

4746−

4848−

50500

%

TOTAL DEVICE

Power Supply CurrentStartup (VCC = 6.5 V for UCX845B, Startup (VCC = 14 V for UCX844B, BV)Operating (Note 11)

ICC−

−

0.3

12

0.5

17

−

−

0.3

12

0.5

17

mA

Power Supply Zener Voltage (ICC = 25 mA) VZ 30 36 − 30 36 − V

11. Adjust VCC above the Startup threshold before setting to 15 V.12.Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

Tlow = 0°C for UC3844B, UC3845B Thigh = + 70°C for UC3844B, UC3845B= − 25°C for UC2844B, UC2845B = + 85°C for UC2844B, UC2845B= − 40°C for UC384xBV, NCV384xBV = +105°C for UC3844BV, UC3845BV

=+125°C for NCV384xBV

0.8

2.0

5.0

8.0

20

50

80

RT,

TIM

ING

RES

ISTO

R (k

)Ω

1.0 M500 k200 k100 k50 k20 k10 k

fOSC, OSCILLATOR FREQUENCY (kHz)

Figure 2. Timing Resistorversus Oscillator Frequency

Figure 3. Output Deadtimeversus Oscillator Frequency

1.0 M100 k10 k

fOSC, OSCILLATOR FREQUENCY (kHz)

50

% D

T, P

ERC

ENT

OU

TPU

T D

EAD

TIM

EÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ

1.�CT = 10 nF2.�CT = 5.0 nF3.�CT = 2.0 nF4.�CT = 1.0 nF5.�CT = 500 pF6.�CT = 200 pF7.�CT = 100 pF

55

60

65

70

75

20 k 50 k 200 k 500 k

2

3

7

5

6NOTE: Output switches at1/2 the oscillator frequency

VCC = 15 VTA = 25°C

0.5 �s/DIV

20 m

V/D

IV

2.55 V

2.5 V

2.45 V

VCC = 15 VAV = -1.0TA = 25°C

VCC = 15 VAV = -1.0TA = 25°C

1.0 �s/DIV

200

mV/

DIV

2.5 V

3.0 V

2.0 V

Figure 4. Error Amp Small SignalTransient Response

Figure 5. Error Amp Large SignalTransient Response

1

4

For RT � 5 Kf � 1.72RTCT

UC3844B, UC3845B, UC2844B, UC2845B

http://onsemi.com5

Δ, O

UTP

UT

VOLT

AGE

CH

ANG

E (2

.0 m

V/D

IV)

O

V

-�20

AVO

L, O

PEN

LO

OP

VOLT

AGE

GAI

N (d

B)

10 M10

f, FREQUENCY (Hz)

Gain

Phase

0

30

60

90

120

150

180100 1.0 k 10 k 100 k 1.0 M

0

20

40

60

80

100

, EXC

ESS

PHAS

E (D

EGR

EES)

φ

0VO, ERROR AMP OUTPUT VOLTAGE (VO)

0

, CU

RR

ENT

SEN

SE IN

PUT

THR

ESH

OLD

(V)

V th

0.2

0.4

0.6

0.8

1.0

1.2

2.0 4.0 6.0 8.0

TA = -�55°C

ÄÄÄÄÄÄÄÄ

VCC = 15 VRL ≤ 0.1 �

Figure 6. Error Amp Open Loop Gain andPhase versus Frequency

Figure 7. Current Sense Input Thresholdversus Error Amp Output Voltage

Figure 8. Reference Voltage Changeversus Source Current

Figure 9. Reference Short Circuit Currentversus Temperature

, REF

EREN

CE

VOLT

AGE

CH

ANG

E (m

V)

-�16

0Iref, REFERENCE SOURCE CURRENT (mA)

20 40 60 80 100 120

ref

V

-�12

-�8.0

-�4.0

0

, REF

EREN

CE

SHO

RT C

IRC

UIT

CU

RR

ENT

(mA)

SCI

50-�55

TA, AMBIENT TEMPERATURE (°C)-�25 0 25 50 75 100 125

70

90

110

Δ

-�20

-�24

TA = 125°C

VCC = 15 VVO = 2.0 V to 4.0 VRL = 100 kTA = 25°C

VCC = 15 V

TA = 25°C

Δ, O

UTP

UT

VOLT

AGE

CH

ANG

E (2

.0 m

V/D

IV)

O

2.0 ms/DIV

V

2.0 ms/DIV

VCC = 12 V to 25 VTA = 25°C

VCC = 15 VIO = 1.0 mA to 20 mATA = 25°C

Figure 10. Reference Load Regulation Figure 11. Reference Line Regulation

VCC = 15 V

TA = 125°C

TA = 25°C

TA = -�55°C

UC3844B, UC3845B, UC2844B, UC2845B

http://onsemi.com6

ÄÄÄÄÄÄÄÄÄÄ

Sink Saturation(Load to VCC)

ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ

RT = 10 kCT = 3.3 nFVFB = 0 VISense = 0 VTA = 25°C

, SU

PPLY

CU

RR

ENT

(mA)

CC

I

00

VCC, SUPPLY VOLTAGE (V)10 20 30 40

5

10

15

20

25

UC

X845

B

UC

X844

B

Figure 12. Output Saturation Voltageversus Load Current

Figure 13. Output Waveform

ÄÄÄÄÄÄ

TA = 25°C

ÄÄÄÄÄÄÄÄ

TA = -�55°C

ÄÄVCC ÄÄÄÄÄÄÄÄÄÄ

VCC = 15 V80 �s Pulsed Load120 Hz Rate

ÄÄÄÄÄÄÄÄ

TA = -�55°CÄÄÄÄÄÄÄÄ

TA = 25°C

0V sat

, OU

TPU

T SA

TUR

ATIO

N V

OLT

AGE

(V)

8000I�O, OUTPUT LOAD CURRENT (mA)

200 400 600

1.0

2.0

3.0

-�2.0

-1.0

0

ÄÄÄÄÄÄÄÄÄÄ

Source Saturation(Load to Ground)

ÄÄÄGND

50 ns/DIV

90%

10%

VCC = 15 VCL = 1.0 nFTA = 25°C

100 ns/DIV

VCC = 30 VCL = 15 pFTA = 25°C

, SU

PPLY

CU

RR

ENT

100

mA/

DIV

20 V

/DIV

I, O

UTP

UT

VOLT

AGE

VC

CO

Figure 14. Output Cross Conduction Figure 15. Supply Current versus Supply Voltage

PIN FUNCTION DESCRIPTION

Pin

Function Description8−Pin 14−Pin

1 1 Compensation This pin is the Error Amplifier output and is made available for loop compensation.

2 3 Voltage Feedback

This is the inverting input of the Error Amplifier. It is normally connected to the switching powersupply output through a resistor divider.

3 5 Current Sense A voltage proportional to inductor current is connected to this input. The PWM uses thisinformation to terminate the output switch conduction.

4 7 RT/CT The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistorRT to Vref and capacitor CT to ground. Oscillator operation to 1.0 kHz is possible.

5 GND This pin is the combined control circuitry and power ground.

6 10 Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourcedand sunk by this pin. The output switches at one−half the oscillator frequency.

7 12 VCC This pin is the positive supply of the control IC.

8 14 Vref This is the reference output. It provides charging current for capacitor CT through resistor RT.

8 Power Ground

This pin is a separate power ground return that is connected back to the power source. It is usedto reduce the effects of switching transient noise on the control circuitry.

11 VC The Output high state (VOH) is set by the voltage applied to this pin. With a separate power sourceconnection, it can reduce the effects of switching transient noise on the control circuitry.

9 GND This pin is the control circuitry ground return and is connected back to the powersource ground.

2,4,6,13 NC No connection. These pins are not internally connected.

UC3844B, UC3845B, UC2844B, UC2845B

http://onsemi.com7

OPERATING DESCRIPTION

The UC3844B, UC3845B series are high performance,fixed frequency, current mode controllers. They arespecifically designed for Off−Line and DC−DC converterapplications offering the designer a cost−effective solutionwith minimal external components. A representative blockdiagram is shown in Figure 16.

OscillatorThe oscillator frequency is programmed by the values

selected for the timing components RT and CT. Capacitor CTis charged from the 5.0 V reference through resistor RT toapproximately 2.8 V and discharged to 1.2 V by an internalcurrent sink. During the discharge of CT, the oscillatorgenerates an internal blanking pulse that holds the centerinput of the NOR gate high. This causes the Output to be ina low state, thus producing a controlled amount of outputdeadtime. An internal flip−flop has been incorporated in theUCX844/5B which blanks the output off every other clockcycle by holding one of the inputs of the NOR gate high. Thisin combination with the CT discharge period yields outputdeadtimes programmable from 50% to 70%. Figure 2 showsRT versus Oscillator Frequency and Figure 3, OutputDeadtime versus Frequency, both for given values of CT.Note that many values of RT and CT will give the sameoscillator frequency but only one combination will yield aspecific output deadtime at a given frequency. The oscillatorthresholds are temperature compensated to within ±6%at 50 kHz. Also, because of industry trends moving theUC384X into higher and higher frequency applications, theUC384XB is guaranteed to within ±10% at 250 kHz.

In many noise−sensitive applications it may be desirableto frequency−lock the converter to an external system clock.This can be accomplished by applying a clock signal to thecircuit shown in Figure 18. For reliable locking, thefree−running oscillator frequency should be set about 10%less than the clock frequency. A method for multi−unitsynchronization is shown in Figure 19. By tailoring theclock waveform, accurate Output duty cycle clamping canbe achieved to realize output deadtimes of greater than 70%.

Error AmplifierA fully compensated Error Amplifier with access to the

inverting input and output is provided. It features a typicaldc voltage gain of 90 dB, and a unity gain bandwidth of1.0 MHz with 57 degrees of phase margin (Figure 6). Thenon−inverting input is internally biased at 2.5 V and is notpinned out. The converter output voltage is typically divideddown and monitored by the inverting input. The maximuminput bias current is −2.0 �A which can cause an outputvoltage error that is equal to the product of the input biascurrent and the equivalent input divider source resistance.

The Error Amp Output (Pin 1) is provided for externalloop compensation (Figure 29). The output voltage is offsetby two diode drops (≈1.4 V) and divided by three before itconnects to the inverting input of the Current Sense

Comparator. This guarantees that no drive pulses appear atthe Output (Pin 6) when Pin 1 is at its lowest state (VOL).This occurs when the power supply is operating and the loadis removed, or at the beginning of a soft−start interval(Figures 21, 22). The Error Amp minimum feedbackresistance is limited by the amplifier’s source current(0.5 mA) and the required output voltage (VOH) to reach thecomparator’s 1.0 V clamp level:

Rf(min) ≈3.0 (1.0 V) + 1.4 V

0.5 mA= 8800 �

Current Sense Comparator and PWM LatchThe UC3844B, UC3845B operate as a current mode

controller, whereby output switch conduction is initiated bythe oscillator and terminated when the peak inductor currentreaches the threshold level established by the ErrorAmplifier Output/Compensation (Pin 1). Thus the errorsignal controls the peak inductor current on acycle−by−cycle basis. The Current Sense Comparator PWMLatch configuration used ensures that only a single pulseappears at the Output during any given oscillator cycle. Theinductor current is converted to a voltage by inserting theground−referenced sense resistor RS in series with thesource of output switch Q1. This voltage is monitored by theCurrent Sense Input (Pin 3) and compared to a level derivedfrom the Error Amp Output. The peak inductor current undernormal operating conditions is controlled by the voltage atPin 1 where:

Ipk =V(Pin 1) − 1.4 V

3 RS

Abnormal operating conditions occur when the powersupply output is overloaded or if output voltage sensing islost. Under these conditions, the Current Sense Comparatorthreshold will be internally clamped to 1.0 V. Therefore themaximum peak switch current is:

Ipk(max) =1.0 V

RS

When designing a high power switching regulator itbecomes desirable to reduce the internal clamp voltage in orderto keep the power dissipation of RS to a reasonable level. Asimple method to adjust this voltage is shown in Figure 20. Thetwo external diodes are used to compensate the internal diodes,yielding a constant clamp voltage over temperature. Erraticoperation due to noise pickup can result if there is an excessivereduction of the Ipk(max) clamp voltage.

A narrow spike on the leading edge of the currentwaveform can usually be observed and may cause the powersupply to exhibit an instability when the output is lightlyloaded. This spike is due to the power transformerinterwinding capacitance and output rectifier recovery time.The addition of an RC filter on the Current Sense Input witha time constant that approximates the spike duration willusually eliminate the instability (refer to Figure 24).

UC3844B, UC3845B, UC2844B, UC2845B

http://onsemi.com8

Figure 16. Representative Block Diagram

Figure 17. Timing Diagram

Capacitor CT

Latch “Set" Input

Output/Compensation

Current SenseInput

Latch “Reset"Input

Output

Large RT/Small CTSmall RT/Large CT

+-

ReferenceRegulator

VCCUVLO

+- Vref

UVLO3.6V

36V

S

RQ

InternalBias

+ 1.0mA

Oscillator

2.5VR

R

R

2R

ErrorAmplifier

VoltageFeedback

Input

Output/Compensation Current Sense

Comparator

1.0V

VCC 7(12)

GND 5(9)

VC

7(11)

Output

6(10)

Power Ground

5(8)

Current Sense Input

3(5)RS

Q1

VCC Vin

1(1)

2(3)

4(7)

8(14)

RT

CT

Vref

= Sink Only Positive True LogicPin numbers adjacent to terminals are for the 8-pin dual-in-line package.Pin numbers in parenthesis are for the D suffix SOIC-14 package.

PWMLatch

(SeeText)

T

UC3844B, UC3845B, UC2844B, UC2845B

http://onsemi.com9

Undervoltage LockoutTwo undervoltage lockout comparators have been

incorporated to guarantee that the IC is fully functionalbefore the output stage is enabled. The positive powersupply terminal (VCC) and the reference output (Vref) areeach monitored by separate comparators. Each has built−inhysteresis to prevent erratic output behavior as theirrespective thresholds are crossed. The VCC comparatorupper and lower thresholds are 16 V/10 V for the UCX844B,and 8.4 V/7.6 V for the UCX845B. The Vref comparatorupper and lower thresholds are 3.6 V/3.4 V. The largehysteresis and low startup current of the UCX844B makesit ideally suited in off−line converter applications whereefficient bootstrap startup techniques are required(Figure 30). The UCX845B is intended for lower voltagedc−dc converter applications. A 36 V Zener is connected asa shunt regulator from VCC to ground. Its purpose is toprotect the IC from excessive voltage that can occur duringsystem startup. The minimum operating voltage for theUCX844B is 11 V and 8.2 V for the UCX845B.

OutputThese devices contain a single totem pole output stage that

was specifically designed for direct drive of powerMOSFETs. It is capable of up to ±1.0 A peak drive currentand has a typical rise and fall time of 50 ns with a 1.0 nF load.Additional internal circuitry has been added to keep theOutput in a sinking mode whenever an undervoltage lockoutis active. This characteristic eliminates the need for anexternal pulldown resistor.

The SOIC−14 surface mount package provides separatepins for VC (output supply) and Power Ground. Properimplementation will significantly reduce the level ofswitching transient noise imposed on the control circuitry.This becomes particularly useful when reducing the Ipk(max)clamp level. The separate VC supply input allows the

designer added flexibility in tailoring the drive voltageindependent of VCC. A Zener clamp is typically connectedto this input when driving power MOSFETs in systemswhere VCC is greater than 20 V. Figure 23 shows properpower and control ground connections in a current−sensingpower MOSFET application.

ReferenceThe 5.0 V bandgap reference is trimmed to ±1.0%

tolerance at TJ = 25°C on the UC284XB, and ±2.0% on theUC384XB. Its primary purpose is to supply charging currentto the oscillator timing capacitor. The reference hasshort−circuit protection and is capable of providing inexcess of 20 mA for powering additional control systemcircuitry.

Design ConsiderationsDo not attempt to construct the converter on

wire−wrap or plug−in prototype boards. High frequencycircuit layout techniques are imperative to preventpulse−width jitter. This is usually caused by excessive noisepick−up imposed on the Current Sense or Voltage Feedbackinputs. Noise immunity can be improved by lowering circuitimpedances at these points. The printed circuit layout shouldcontain a ground plane with low−current signal andhigh−current switch and output grounds returning onseparate paths back to the input filter capacitor. Ceramicbypass capacitors (0.1 �F) connected directly to VCC, VC,and Vref may be required depending upon circuit layout.This provides a low impedance path for filtering the highfrequency noise. All high current loops should be kept asshort as possible using heavy copper runs to minimizeradiated EMI. The Error Amp compensation circuitry andthe converter output voltage divider should be located closeto the IC and as far as possible from the power switch andother noise−generating components.

Bias

+

Osc

R

R

R

2R

EA

5(9)

1(1)

2(3)

4(7)

8(14)

RT

CT

Vref

Figure 18. External Clock Synchronization Figure 19. External Duty Cycle Clamp andMulti−Unit Synchronization

0.01

The diode clamp is required if the Sync amplitude is large enough to causethe bottom side of CT to go more than 300 mV below ground.

ExternalSyncInput

47

+

R

R

R

2R

Bias

Osc

EA

5(9)

1(1)

2(3)

4(7)

8(14)

To AdditionalUCX84XBs

R

SQ

8 4

6

5

2

1

C

3

7

RA

RB5.0k

5.0k

5.0kMC1455

f� �� 1.44(RA� �� 2RB)C

D(max)� �� RARA� �� 2RB

UC3844B, UC3845B, UC2844B, UC2845B

http://onsemi.com10

If: SENSEFET = MTP10N10MRS = 200

Figure 20. Adjustable Reduction of Clamp Level Figure 21. Soft−Start Circuit

Figure 22. Adjustable Buffered Reduction of Clamp Level with Soft−Start

+-

5.0V Ref

+-

S

RQ

Bias

+

Osc

R

R

R2REA

1.0V

5(9)

7(11)

6(10)

5(8)

3(5) RS

Q1

VCC Vin

1(1)

2(3)

4(7)

8(14)

R1

VClampR2

Ipk(max)� ��VClamp

RS

Where: 0 ≤ VClamp ≤ 1.0 V

5.0V Ref

+-

S

RQ

Bias

+

1.0mA

Osc

R

R

R2R

EA

1.0V

5(9)

1(1)

2(3)

4(7)

8(14)

C

1.0M

tSoft-Start ≈ 3600C in �F

+-

+-

S

R

+

R

R

R2R

Ipk(max)� ��VClamp

RS

Figure 23. Current Sensing Power MOSFET

5.0V Ref

Q

Bias

Osc

EA

1.0V

5(9)

7(11)

6(10)

5(8)

3(5)RS

Q1

VCC Vin

1(1)

2(3)

4(7)

8(14)

R1

R2

Where: 0 ≤ VClamp ≤ 1.0 V

MPSA63

+-

5.0V Ref

+-

S

RQ

(11)

(10)

(8)

Comp/Latch

(5) RS1/4 W

VCC Vin

KM

D SENSEFET

GS

Power Ground:To Input Source

Return

Control Circuitry Ground:To Pin (9)

Virtually lossless current sensing can be achieved with the implementationof a SENSEFET� power switch. For proper operation during over-currentconditions, a reduction of the Ipk(max) clamp level must be implemented.Refer to Figures 20 and 22.

VPin�5� ��RS�Ipk�rDS(on)

rDM(on)� �� RS

Then :� VPin�5� �� 0.075�Ipk

7(12)

7(12)

1.0 mA

Comp/Latch

Comp/Latch

1.0 mA

(12)

T

T

T TVClamp

VClamp ≈1.67

�R2R1

� 1� + 0.33x10-3 � R1R2R1 � R2

�

VClamp ≈1.67

�R2R1

� 1�

tSoftStart � In1 � VC3VClamp

��C R1�R2R1 � R2

UC3844B, UC3845B, UC2844B, UC2845B

http://onsemi.com11

Figure 24. Current Waveform Spike Suppression

+-

5.0V Ref

+

-

S

RQ

7(11)

6(10)

5(8)

3(5)

RS

Q1

VCC Vin

C

R

The addition of the RC filter will eliminateinstability caused by the leading edge spike on the current waveform.

7(12)

Comp/Latch

T

Figure 25. MOSFET Parasitic Oscillations Figure 26. Bipolar Transistor Drive

+-

S

R

5.0V Ref

Q

7(11)

6(10)

5(8)

3(5) RS

Q1

VCC Vin

Series gate resistor Rg will damp any high frequencyparasitic oscillations caused by the MOSFET inputcapacitance and any series wiring inductance in thegate-source circuit.

6(10)

5(8)

3(5) RS

Q1

Vin

C1

Base ChargeRemoval

The totem pole output can furnish negative base currentfor enhanced transistor turn-off, with the addition ofcapacitor C1.

IB

+

-

0

7(12)

Rg

Comp/Latch

T

+

-

UC3844B, UC3845B, UC2844B, UC2845B

http://onsemi.com12

+

R

2R1.0mA

EA

2(3)

5(9)

2.5V

1(1)

RfCfRd

Rp

From VO

Error Amp compensation circuit for stabilizing current mode boostand flyback topologies operating with continuous inductor current.

Cp

Ri

Figure 27. Isolated MOSFET Drive

Figure 28. Latched Shutdown

Figure 29. Error Amplifier Compensation

+-

S

R

5.0V Ref

Q

7(11)

6(10)

5(8)

3(5)

RS

Q1

VCC Vin

IsolationBoundary

VGS Waveforms

+

-

0

50% DC 25% DC

�NSNp�

Bias

+

Osc

R

R

R

2R

EA

5(9)

1(1)

2(3)

4(7)

8(14)

The MCR101 SCR must be selected for a holding of < 0.5 mA @ TA(min). Thesimple two transistor circuit can be used in place of the SCR as shown. Allresistors are 10 k.

MCR101

2N3905

2N3903

+

R

2R1.0mA

EA

2(3)

5(9)

2.5V

1(1)

RfCfRd

Ri

From VO

Error Amp compensation circuit for stabilizing any current mode topology exceptfor boost and flyback converters operating with continuous inductor current.

Rf ≥ 8.8k

Comp/Latch

7(12)

R

C NS NP

1.0 mA

T

+

-0

+

-

Ipk =V(Pin�1) - 1.4

3 RS

UC3844B, UC3845B, UC2844B, UC2845B

http://onsemi.com13

MUR110

+-

+-

S

R

+

R

R

5.0V Ref

Q

Bias

EA

5(9)

7(11)

6(10)

5(8)

3(5)0.5

MTP4N50

1(1)

2(3)

4(7)

8(14)

33k

1.0nF

470pF

150k100pF

18k

4.7k

Figure 30. 7 W Off−Line Flyback Regulator

0.01

100

+

1.0k

115 Vac

4.7�MDA202

250

56k

4.7k 3300pF

1N4935 1N4935

+ +68

47

1N4937

1N4937680pF 2.7k

L3

L2

L1

+ +

+ +

+ +

1000

1000

2200

10

10

1000

5.0V/4.0A

5.0V RTN

12V/0.3A

±12V RTN

-12V/0.3A

Primary: 45 Turns #26 AWGSecondary ±12 V: 9 Turns #30 AWG (2 Strands) Bifiliar WoundSecondary 5.0 V: 4 Turns (six strands) #26 Hexfiliar WoundSecondary Feedback: 10 Turns #30 AWG (2 strands) Bifiliar WoundCore: Ferroxcube EC35-3C8Bobbin: Ferroxcube EC35PCB1Gap: ≈ 0.10" for a primary inductance of 1.0 mH

MUR110

MBR1635T1

22Osc

T1 -

7(12)

Comp/Latch

T

L1L2, L3

- 15 �H at 5.0 A, Coilcraft Z7156- 25 �H at 5.0 A, Coilcraft Z7157

1N5819

Test Conditions Results

Line Regulation: 5.0 V±12 V

Vin = 95 Vac to 130 Vac � = 50 mV or ±0.5%� = 24 mV or ±0.1%

Load Regulation: 5.0 V±12 V

Vin = 115 Vac, Iout = 1.0 A to 4.0 AVin = 115 Vac, Iout = 100 mA to 300 mA

� = 300 mV or ±3.0%� = 60 mV or ±0.25%

Output Ripple: 5.0 V±12 V

Vin = 115 Vac 40 mVpp80 mVpp

Efficiency Vin = 115 Vac 70%

All outputs are at nominal load currents unless otherwise noted.

UC3844B, UC3845B, UC2844B, UC2845B

http://onsemi.com14

Osc

+-

ReferenceRegulator

+-

34V

S

RQ

InternalBias

+0.5mA

Osc

R

R

R

2R

ErrorAmplifier

1.0V

7(12)

7(11)

6(10)

5(8)

3(5)

R1

Vin = 15V

1(1)

2(3)

4(7)

8(14)

10k

1.0nF

The capacitor's equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series resistormay be required when using tantalum or other low ESR capacitors. The converter's output can provide excellent lineand load regulation by connecting the R2/R1 resistor divider as shown.

Figure 31. Step−Up Charge Pump Converter

5(9)

PWM

T

Latch

Current SenseComparator

2.5V

3.6V

VCCUVLO

VrefUVLO

UC3845B+

47

1N5819

15 101N5819

+47

R2Connect toPin 2 forclosed loopoperation.

�R2R1

� 1�

VO ≈ 2 (Vin)

Output Load Regulation(Open Loop Configuration)

IO (mA) VO (V)

0291836

29.928.828.327.424.4

+-

+-

S

R

+

R

R

R

2R

5(9)

PWM

T

Latch

Current SenseComparator

+47

15 101N5819

+47

ReferenceRegulator

34V

Q

InternalBias

0.5mA

ErrorAmplifier

1.0V

7(12)

7(11)

6(10)

5(8)

3(5)

Vin = 15V

1(1)

2(3)

4(7)

8(14)

10k

1.0nF

The capacitor's equivalent series resistance must limit the Drive Output current to 1.0 A.An additional series resistor may be required when using tantalum or other low ESR capacitors.

Figure 32. Voltage−Inverting Charge Pump Converter

2.5V

3.6V

VCCUVLO

VrefUVLO

UC3845B

VO ≈ -Vin

Output Load Regulation

IO (mA) VO (V)

0291832

−14.4−13.2−12.5−11.7−10.6

1N5819

+

VO = 2.5

UC3844B, UC3845B, UC2844B, UC2845B

http://onsemi.com15

ORDERING INFORMATION

Device Operating Temperature Range Package Shipping†

UC384xBDG

TA = 0° to +70°C

SOIC−14(Pb−Free)

55 Units/Rail

UC384xBDR2G SOIC−14(Pb−Free)

2500 Tape & Reel

UC384xBD1G SOIC−8(Pb−Free)

98 Units/Rail

UC384xBD1R2G SOIC−8(Pb−Free)

2500 Tape & Reel

UC384xBNG PDIP−8(Pb−Free)

50 Units/Rail

UC284xBDG

TA = −25° to +85°C


55 Units/Rail

UC284xBDR2G SOIC−14(Pb−Free)

2500 Tape & Reel

UC284xBD1G SOIC−8(Pb−Free)

98 Units/Rail

UC284xBD1R2G SOIC−8(Pb−Free)

2500 Tape & Reel

UC284xBNG PDIP−8(Pb−Free)

50 Units/Rail

UC384xBVDG

TA = −40° to +105°C


55 Units/Rail

UC384xBVDR2G SOIC−14(Pb−Free)

2500 Tape & Reel

UC384xBVD1G SOIC−8(Pb−Free)

98 Units/Rail

UC384xBVD1R2G SOIC−8(Pb−Free)

2500 Tape & Reel

UC384xBVNG PDIP−8(Pb−Free)

50 Units/Rail

NCV3845BVD1R2G*TA = −40° to +125°C

SOIC−8(Pb−Free)

2500 Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.

x indicates either a 4 or 5 to define specific device part numbers.*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP

Capable.

UC3844B, UC3845B, UC2844B, UC2845B

http://onsemi.com16

MARKING DIAGRAMS

SOIC−14D SUFFIX

CASE 751A

SOIC−8D1 SUFFIXCASE 751

PDIP−8N SUFFIXCASE 626

UC384xBVNAWL

YYWWG

1

8

UC384xBVDGAWLYWW

1

14

384xBALYWV

�

1

8

UC384xBNAWL

YYWWG

1

8

UC284xBNAWL

YYWWG

1

8

UC384xBDGAWLYWW

1

14

UC284xBDGAWLYWW

1

14

384xBALYW

�

1

8

284xBALYW

�

1

8

x = 4 or 5A = Assembly LocationWL, L = Wafer LotYY, Y = YearWW, W = Work WeekG or � = Pb−Free Package

SENSEFET is a trademark of Semiconductor Components Industries, LLC.

PDIP−8CASE 626−05

ISSUE PDATE 22 APR 2015

SCALE 1:1

1 4

58

b2NOTE 8

D

b

L

A1

A

eB

XXXXXXXXXAWL

YYWWG

E

GENERICMARKING DIAGRAM*

XXXX = Specific Device CodeA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekG = Pb−Free Package

*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “ �”,may or may not be present.

A

TOP VIEW

C

SEATINGPLANE

0.010 C ASIDE VIEW

END VIEW

END VIEW

WITH LEADS CONSTRAINED

DIM MIN MAXINCHES

A −−−− 0.210A1 0.015 −−−−

b 0.014 0.022

C 0.008 0.014D 0.355 0.400D1 0.005 −−−−

e 0.100 BSC

E 0.300 0.325

M −−−− 10

−−− 5.330.38 −−−

0.35 0.56

0.20 0.369.02 10.160.13 −−−

2.54 BSC

7.62 8.26

−−− 10

MIN MAXMILLIMETERS

NOTES:1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.2. CONTROLLING DIMENSION: INCHES.3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-

AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH

OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARENOT TO EXCEED 0.10 INCH.

5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUMPLANE H WITH THE LEADS CONSTRAINED PERPENDICULARTO DATUM C.

6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THELEADS UNCONSTRAINED.

7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THELEADS, WHERE THE LEADS EXIT THE BODY.

8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARECORNERS).

E1 0.240 0.280 6.10 7.11

b2

eB −−−− 0.430 −−− 10.92

0.060 TYP 1.52 TYP

E1

M

8X

c

D1

B

A2 0.115 0.195 2.92 4.95

L 0.115 0.150 2.92 3.81°°

H

NOTE 5

e

e/2A2

NOTE 3

M B M NOTE 6

M

STYLE 1:PIN 1. AC IN

2. DC + IN3. DC − IN4. AC IN5. GROUND6. OUTPUT7. AUXILIARY8. VCC

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.

98ASB42420BDOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1PDIP−8

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

SOIC−8 NBCASE 751−07

ISSUE AKDATE 16 FEB 2011

SEATINGPLANE

14

58

N

J

X 45�

K

NOTES:1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEWSTANDARD IS 751−07.

A

B S

DH

C

0.10 (0.004)

SCALE 1:1

STYLES ON PAGE 2

DIMA

MIN MAX MIN MAXINCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B 3.80 4.00 0.150 0.157C 1.35 1.75 0.053 0.069D 0.33 0.51 0.013 0.020G 1.27 BSC 0.050 BSCH 0.10 0.25 0.004 0.010J 0.19 0.25 0.007 0.010K 0.40 1.27 0.016 0.050M 0 8 0 8 N 0.25 0.50 0.010 0.020S 5.80 6.20 0.228 0.244

−X−

−Y−

G

MYM0.25 (0.010)

−Z−

YM0.25 (0.010) Z S X S

M� � � �

XXXXX = Specific Device CodeA = Assembly LocationL = Wafer LotY = YearW = Work Week� = Pb−Free Package


1

8

XXXXXALYWX

1

8

IC Discrete

XXXXXXAYWW

�1

8

1.520.060

7.00.275

0.60.024

1.2700.050

4.00.155

� mminches

�SCALE 6:1

*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

Discrete

XXXXXXAYWW

1

8

(Pb−Free)

XXXXXALYWX

�1

8

IC(Pb−Free)

XXXXXX = Specific Device CodeA = Assembly LocationY = YearWW = Work Week� = Pb−Free Package

*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “�”, mayor may not be present. Some products maynot follow the Generic Marking.


PACKAGE DIMENSIONS



DESCRIPTION:


PAGE 1 OF 2SOIC−8 NB


SOIC−8 NBCASE 751−07

ISSUE AKDATE 16 FEB 2011

STYLE 4:PIN 1. ANODE

2. ANODE3. ANODE4. ANODE5. ANODE6. ANODE7. ANODE8. COMMON CATHODE

STYLE 1:PIN 1. EMITTER

2. COLLECTOR3. COLLECTOR4. EMITTER5. EMITTER6. BASE7. BASE8. EMITTER

STYLE 2:PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #13. COLLECTOR, #24. COLLECTOR, #25. BASE, #26. EMITTER, #27. BASE, #18. EMITTER, #1

STYLE 3:PIN 1. DRAIN, DIE #1

2. DRAIN, #13. DRAIN, #24. DRAIN, #25. GATE, #26. SOURCE, #27. GATE, #18. SOURCE, #1

STYLE 6:PIN 1. SOURCE

2. DRAIN3. DRAIN4. SOURCE5. SOURCE6. GATE7. GATE8. SOURCE

STYLE 5:PIN 1. DRAIN

2. DRAIN3. DRAIN4. DRAIN5. GATE6. GATE7. SOURCE8. SOURCE

STYLE 7:PIN 1. INPUT

2. EXTERNAL BYPASS3. THIRD STAGE SOURCE4. GROUND5. DRAIN6. GATE 37. SECOND STAGE Vd8. FIRST STAGE Vd

STYLE 8:PIN 1. COLLECTOR, DIE #1

2. BASE, #13. BASE, #24. COLLECTOR, #25. COLLECTOR, #26. EMITTER, #27. EMITTER, #18. COLLECTOR, #1

STYLE 9:PIN 1. EMITTER, COMMON

2. COLLECTOR, DIE #13. COLLECTOR, DIE #24. EMITTER, COMMON5. EMITTER, COMMON6. BASE, DIE #27. BASE, DIE #18. EMITTER, COMMON

STYLE 10:PIN 1. GROUND

2. BIAS 13. OUTPUT4. GROUND5. GROUND6. BIAS 27. INPUT8. GROUND

STYLE 11:PIN 1. SOURCE 1

2. GATE 13. SOURCE 24. GATE 25. DRAIN 26. DRAIN 27. DRAIN 18. DRAIN 1

STYLE 12:PIN 1. SOURCE

2. SOURCE3. SOURCE4. GATE5. DRAIN6. DRAIN7. DRAIN8. DRAIN

STYLE 14:PIN 1. N−SOURCE

2. N−GATE3. P−SOURCE4. P−GATE5. P−DRAIN6. P−DRAIN7. N−DRAIN8. N−DRAIN

STYLE 13:PIN 1. N.C.

2. SOURCE3. SOURCE4. GATE5. DRAIN6. DRAIN7. DRAIN8. DRAIN

STYLE 15:PIN 1. ANODE 1

2. ANODE 13. ANODE 14. ANODE 15. CATHODE, COMMON6. CATHODE, COMMON7. CATHODE, COMMON8. CATHODE, COMMON

STYLE 16:PIN 1. EMITTER, DIE #1

2. BASE, DIE #13. EMITTER, DIE #24. BASE, DIE #25. COLLECTOR, DIE #26. COLLECTOR, DIE #27. COLLECTOR, DIE #18. COLLECTOR, DIE #1

STYLE 17:PIN 1. VCC

2. V2OUT3. V1OUT4. TXE5. RXE6. VEE7. GND8. ACC

STYLE 18:PIN 1. ANODE

2. ANODE3. SOURCE4. GATE5. DRAIN6. DRAIN7. CATHODE8. CATHODE

STYLE 19:PIN 1. SOURCE 1

2. GATE 13. SOURCE 24. GATE 25. DRAIN 26. MIRROR 27. DRAIN 18. MIRROR 1

STYLE 20:PIN 1. SOURCE (N)

2. GATE (N)3. SOURCE (P)4. GATE (P)5. DRAIN6. DRAIN7. DRAIN8. DRAIN

STYLE 21:PIN 1. CATHODE 1

2. CATHODE 23. CATHODE 34. CATHODE 45. CATHODE 56. COMMON ANODE7. COMMON ANODE8. CATHODE 6

STYLE 22:PIN 1. I/O LINE 1

2. COMMON CATHODE/VCC3. COMMON CATHODE/VCC4. I/O LINE 35. COMMON ANODE/GND6. I/O LINE 47. I/O LINE 58. COMMON ANODE/GND

STYLE 23:PIN 1. LINE 1 IN

2. COMMON ANODE/GND3. COMMON ANODE/GND4. LINE 2 IN5. LINE 2 OUT6. COMMON ANODE/GND7. COMMON ANODE/GND8. LINE 1 OUT

STYLE 24:PIN 1. BASE

2. EMITTER3. COLLECTOR/ANODE4. COLLECTOR/ANODE5. CATHODE6. CATHODE7. COLLECTOR/ANODE8. COLLECTOR/ANODE

STYLE 25:PIN 1. VIN

2. N/C3. REXT4. GND5. IOUT6. IOUT7. IOUT8. IOUT

STYLE 26:PIN 1. GND

2. dv/dt3. ENABLE4. ILIMIT5. SOURCE6. SOURCE7. SOURCE8. VCC

STYLE 27:PIN 1. ILIMIT

2. OVLO3. UVLO4. INPUT+5. SOURCE6. SOURCE7. SOURCE8. DRAIN

STYLE 28:PIN 1. SW_TO_GND

2. DASIC_OFF3. DASIC_SW_DET4. GND5. V_MON6. VBULK7. VBULK8. VIN

STYLE 29:PIN 1. BASE, DIE #1

2. EMITTER, #13. BASE, #24. EMITTER, #25. COLLECTOR, #26. COLLECTOR, #27. COLLECTOR, #18. COLLECTOR, #1

STYLE 30:PIN 1. DRAIN 1

2. DRAIN 13. GATE 24. SOURCE 25. SOURCE 1/DRAIN 26. SOURCE 1/DRAIN 27. SOURCE 1/DRAIN 28. GATE 1



DESCRIPTION:




SOIC−14 NBCASE 751A−03

ISSUE LDATE 03 FEB 2016

SCALE 1:11

14


XXXXXXXXXGAWLYWW

1

14

XXXXX = Specific Device CodeA = Assembly LocationWL = Wafer LotY = YearWW = Work WeekG = Pb−Free Package

*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “ �”,may or may not be present.

STYLES ON PAGE 2

NOTES:1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.2. CONTROLLING DIMENSION: MILLIMETERS.3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSIONSHALL BE 0.13 TOTAL IN EXCESS OF ATMAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDEMOLD PROTRUSIONS.

5. MAXIMUM MOLD PROTRUSION 0.15 PERSIDE.

H

14 8

71

M0.25 B M

C

hX 45

SEATINGPLANE

A1

A

M

�

SAM0.25 B SC

b13X

BA

E

D

e

DETAIL A

L

A3

DETAIL A

DIM MIN MAX MIN MAXINCHESMILLIMETERS

D 8.55 8.75 0.337 0.344E 3.80 4.00 0.150 0.157

A 1.35 1.75 0.054 0.068

b 0.35 0.49 0.014 0.019

L 0.40 1.25 0.016 0.049

e 1.27 BSC 0.050 BSC

A3 0.19 0.25 0.008 0.010A1 0.10 0.25 0.004 0.010

M 0 7 0 7

H 5.80 6.20 0.228 0.244h 0.25 0.50 0.010 0.019

� � � �

6.50

14X0.58

14X

1.18

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

0.10


PACKAGE DIMENSIONS



DESCRIPTION:




SOIC−14CASE 751A−03

ISSUE LDATE 03 FEB 2016

STYLE 7:PIN 1. ANODE/CATHODE

2. COMMON ANODE3. COMMON CATHODE4. ANODE/CATHODE5. ANODE/CATHODE6. ANODE/CATHODE7. ANODE/CATHODE8. ANODE/CATHODE9. ANODE/CATHODE

10. ANODE/CATHODE11. COMMON CATHODE12. COMMON ANODE13. ANODE/CATHODE14. ANODE/CATHODE

STYLE 5:PIN 1. COMMON CATHODE

2. ANODE/CATHODE3. ANODE/CATHODE4. ANODE/CATHODE5. ANODE/CATHODE6. NO CONNECTION7. COMMON ANODE8. COMMON CATHODE9. ANODE/CATHODE

10. ANODE/CATHODE11. ANODE/CATHODE12. ANODE/CATHODE13. NO CONNECTION14. COMMON ANODE

STYLE 6:PIN 1. CATHODE

2. CATHODE3. CATHODE4. CATHODE5. CATHODE6. CATHODE7. CATHODE8. ANODE9. ANODE

10. ANODE11. ANODE12. ANODE13. ANODE14. ANODE


2. ANODE/CATHODE3. ANODE/CATHODE4. NO CONNECTION5. ANODE/CATHODE6. NO CONNECTION7. ANODE/CATHODE8. ANODE/CATHODE9. ANODE/CATHODE

10. NO CONNECTION11. ANODE/CATHODE12. ANODE/CATHODE13. NO CONNECTION14. COMMON ANODE

STYLE 3:PIN 1. NO CONNECTION

2. ANODE3. ANODE4. NO CONNECTION5. ANODE6. NO CONNECTION7. ANODE8. ANODE9. ANODE

10. NO CONNECTION11. ANODE12. ANODE13. NO CONNECTION14. COMMON CATHODE

STYLE 4:PIN 1. NO CONNECTION

2. CATHODE3. CATHODE4. NO CONNECTION5. CATHODE6. NO CONNECTION7. CATHODE8. CATHODE9. CATHODE

10. NO CONNECTION11. CATHODE12. CATHODE13. NO CONNECTION14. COMMON ANODE


2. ANODE/CATHODE3. ANODE/CATHODE4. NO CONNECTION5. ANODE/CATHODE6. ANODE/CATHODE7. COMMON ANODE8. COMMON ANODE9. ANODE/CATHODE

10. ANODE/CATHODE11. NO CONNECTION12. ANODE/CATHODE13. ANODE/CATHODE14. COMMON CATHODE

STYLE 2:CANCELLED



DESCRIPTION:




onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliatesand/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to anyproducts or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of theinformation, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or useof any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its productsand applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications informationprovided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance mayvary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any licenseunder any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systemsor any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. ShouldBuyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an EqualOpportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATIONTECHNICAL SUPPORTNorth American Technical Support:Voice Mail: 1 800−282−9855 Toll Free USA/CanadaPhone: 011 421 33 790 2910

LITERATURE FULFILLMENT:Email Requests to: [email protected]

onsemi Website: www.onsemi.com

Europe, Middle East and Africa Technical Support:Phone: 00421 33 790 2910For additional information, please contact your local Sales Representative

◊

https://www.onsemi.com/site/pdf/Patent-Marking.pdf

uc3844b, uc3845b, uc2844b, uc2845b high performance … · mount (soic−8) plastic package as well...

Documents