The Ninth International Syrnpo�ium on Semiconductor Manufacturing

P-48

Achieving Stretched Capacity Goal Through Integrated Engineering and Manufacturing Excellence

Reginald See Theam K wooi Intel Technology (M) Sdn Bhd

Bayan Lepas Free Industrial Zone, P.O. Box No. 121, 11900 P enang, Malaysia E-mail: theam.kwooLreginald.see@intel.com

Abstract - Achieving Stretched Equipment Capacity and HIgh Productivity in High Volume Manufacturing is a gritty challenge to drive down cost continuously in this competitive chipset market. With unprecedented volume ramp of both key products in Q4 '99, the Test Module faced a shortage of two to four testers.

Driving through working group, a refurbishment process was achieved successfully resulting in 60% reduction of tester faults thus improving Mean TIme Between Failure (MTBF) from 140hrs to 160hrs. With the implementation of improved pogo pins at Tester Interface Unit (TlU) and test head had improved cleaning frequency from 5k to 90k, one­sum test yieldfrom 88.7% to 97.5% and reduced non-genuine SBLfrom 10% to less than 3% consistently. The new design of JLSI handler s floating head also increased the Mean TIme Between Assist (MTBA) from 0.79hrs to 1. 16hrs. Besides, hardware retest implementation has also seen reduction in retest rate from 10% to 2.1% and 5%for both key products. Manufacturing also helped in optimizing the tester s loading with standby lots and zero idling time. Consequently, machine utilization exceeded 80% with additional volume supported flawlessly thus avoiding additional testers. The strategy is to always look into ways of stretching machine capability in order to support additional volume.

Index Terms - Machine Utilization

INTRODUCTION

Enhancing productivity was a continuous challenge to ensure agility and flexibility in supporting steep volume ramp consistently in an assembly ball grid array (BGA) factory. This is very key to ensuring low cost in the competitive chipset market. In QI '99, test module faced an uphill task in coming up with breakthrough strategies to support steep volume ramp (1.4Mu per week) for its two key products in view of the tester's shortage come Q4'99. The problem statement was there were shortages of at least two to four Trillium testers based on the build plan and POR numbers.

Partnering with retest Jet (joint engineering team), product engineering and manufacturing, the TrilliumlJLSI Jet strove to stretch the capacity goal through integrated engineering and manufacturing excellence. As a result, the team decided to concentrate on five top key focuses: a) tester fault reduction b) JLSI mean time between assist (MTBA) improvement c) tester interface unit (TIU) cleaning frequency d) product test time reduction (TI'R) with hardware retest e) optimize tester's loading.

TESTER FAULT REDUCTION Background and Approach

Tester Fault due to quadrant and test head power supplies had been the main contributor to the high down time impacting Trillium testers since 1998. It contributed at least 70% of the total down time. As a result, the working group team decided to work with the vendor, LTX to look into the problem statement, root causes and come up with concrete solutions to reduce this serious issue. The result of the fmding was there was high breakdown in terms of main capacitor and output capacitors based on historical repair data. Both contributed 86% of the power supplies failure. Besides, the life span of the power supplies which was 7 years had been far exceeded. Thus, a refurbishment process was worked out with LTX to replace the highly breakdown capacitors of the quad and test head power supplies namely the -S.2V/300A, -2.02V/300A, lSV/25A and lO.2V/22A every time a defective power supply was sent back for repair. The refurbishment process came alive without any cost incurred.

Tester Fault Reduction

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Figure 1. Tester Fault Reduction

The result was tremendous with Tester Fault reduced significantly as shown in Figure 1.

JLSI MTBA IMPROVEMENT Background

High jam rate and open test fallout due to misalignment

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between the floating head and TIU's guide pin had been a major concern for JLSI handler. Consequently, this resulted in loss of unnecessary downtime and prodJlctivity. Thus, the engineering team decided to study the floating head design in depth with the aim of enhancing the current design which also caused high PCB bent.

The floating head is an assembly attached to the front and rear arm of the transferring mechanism. These arms help to transfer DUT (device under test) from turntable to chamber which is the testing site. Figure I shows the old floating head design which frequently caused bent TIU's guide pin that led to high jam rate, open failure and PCB bent. The proposed change was to have a floating head with spring tension that could self-aligned itself to the TIU's guide pin as shown in Figure 2.

Old New Old .

Figure 2.01d vs New Floating Head

Check Result

New

Table I indicates MTBA improvement from O.79hr to 1.16 hrS with reduced jam rate.

Table I. MTBA Improvement Floating Head Old design MTBA(Hours) 0.79

New design 1.16

POGO PIN IMPLEMENTATION

With the increasing challenge to take productivity to another level of excellence, TIU had become a bottleneck contributing to very high setup time. There had been a lot of TIU breakdowns due to short life span of old style pogo pin which resulted in frequent cleaning and rel'lacement of pogo pins. Besides, for every breakdown operator needed to change the TIU and run standard test to confirm the whole setup which comprised of tester, handler and TIU. As a result, 15-20 minutes downtime was incurred per machine unnecessarily. Based on the fact that the cleaning frequency and life span of the old style pogo pins were 5k and 20k respectively, there would always be a minimum of 30-40 minutes loss of productivity per shift per machine. The impact was significarit considering the high number of testers

and handlers that the factory has in supporting steep ramp of high volume products.

Breakthrough solution T he retest Jet partnering with Intel test tooling organization (iTIO) brainstormed for innovative and cost effective solution to enhance the cleaning frequency and life span of the pogo pin in order for the factory to run faster and cheaper! In parallel, second sourcing was collaborated with Intel purchasing to deliver the solution based on Intel specifications.

Later, a thorough and comprehensive design of experiments was carried out on the new pogo pin in terms of solder ball coplanarity inducement, contact resistance, ESO, test yield, cleaning frequency and life span.

Check Result Table 2 shows the results which saw great improvement being achieved with the new pogo pin. This was deimitely a breakthrough solution resulting in 8% of productivity and cost savings of US$2 million.

Table 2. Old Style vs New Style Quality Characteristics Quality Old style New style

Characteristic ESD <200 V <200 V Solder All All

ball temperature: temperature: coplanarity Both Both inducement equivalent equivalent

Contact All All resistance temperature: temperature:

new style new style better better

Test yield 88.7% 95.5% Cleaning 1 s 151

frequency cleaning: 5k 2nd cleaning: 90k 2nd cleaning: 10k cleaning: lOOk

Life span 20k 200k Note: SEB means statistically equal or better Proliferation to TriUium test head

Acceptance Criteria

SEB SEB

SEB

SEB SEB

SEB

As this design was an excellent innovation, it was later proliferated to test head's pogo pin. The new design with crown tip provided better contact and through paired t testing, it was found that the one-sum test yield improved by . about 0.5%. Figure 3 showed the results achieved.

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Figure 3. One-sum Yield Improvement

PRODUCT TTR WITH HARDWARE RETEST

IMPLEMENTATION

In addition to the equipment perfonnance enhancement to achieve higher productivity, a test time reduction approach was pursued by the product engineering group to establish a more cost effective and agile HVM environment.

Hardware Retest Implementation A known non· genuine reject in BGA device is output voltage level test sensitive to TIU contactor resistance and open test due to inaccurate clamp of the DUT with the Tru. By lifting the lLSI ann and perfonning a reclamp of the DUT on the TIU, saving load and unload time, this hardware retest mechanism showed a 40% success rate. Besides, 20% of the lots tested achieved above 99% test yield. Hence, this paved the way for the realization of conditional retest. Only lA yield less than 99% would be subjected to retest.

Non Genuine SBL redution With the implementation of new style pogo pin on TIU and hardware retest, the non·genuine SBL improved tremendously from 10% to less than 5% consistently. Figure 4 and Figure 5 show the improvement seen in retest rate and non-genuine SBL for both key products.

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Retest rate for key products

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Figure 4. Retest Rate

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Non Genuine SBl for key products

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Figure 5. Non Genuine SBL Reduction

OPTIMIZE TESTER'S LOADING

Based on MU model, there were four key elements that contributed to the 80% MU namely engineering, operation, industrial engineering and product elements. Under operation element which comprises of staggered break times, it contributed a significant 5-6% loss of the MU. With this in mind, engineering worked with manufacturing to see how idling time of the machine could be reduced to achieve higher productivity. The team came up with several strategies: a) identify focus systems which were the most stable systems b) ensure all testers have standby lots c) ensure adequate coverage of machines during break time. d) consistent check on inventory and loading based on machine capacity and current inventory e) enough focus by maintenance engineer to attend to focus systems f) positive reinforcement rewarding system for line folks. A proper briefing was later conducted to the line folks as to how . productivity should be efficiently optimized to indirectly

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bring about achieving all volume goals and product cost reduction. This integrated effort by line folks helped to reduce the idling time successfully from Ihr to average 0.3hr, an improvement 0[70%.

CONCLUSION

Consequently, with all these concerted effort and partnership between engineering and manufacturing , the TrilliumlJLSI module exceeded the 80% MU goal and capacity was stretched to 230 kUnit per system per week and 202 kUnit per system per'week for both key products. All these effort represented a massive 30% productivity quantum leap. This excellent productivity improvement demonstrated through integrated engineering and manufacturing excellence allows Trillium/JLSI to continue to be reused to support upcoming new product startup and also avoided additional Trillium testers with the cost of US I Million per tester. Graph 6-8 were a proof of the excellent and tremendous effort put in by all parties in achieving Operations Excellence by the BGA factory.

Graph 6. MUIRun rate for Product A

i MU and Run rate for Product A

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Graph 7. MU/Run rate for Product B

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Graph 8. Excellent Pull-in data

ACKNOWLEDGEMENT

I would like to take this opportunity to express special thanks and appreciation especially to those operators and maintenance line engineers who one way or another PROVED that World Class Operation with speed, cost and agility could be achieved with special dedication, commitment and team work! Also thanks to engineering and manufacturing who made the BGA factory a benchmark in terms of world class performance.

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