umts application notes

49
WIRELESS I NFRASTRUCTURE S OLUTIONS G UIDE Digital Signal Processors, ASIC, Digital Upconverters/Downconverters, Data Converters, Amplifiers, Microcontrollers, Clock Distribution, Serial Gigabit, Interface, Logic, Power Management INSIDE Signal Chain 4 Timing and Interface 24 Logic 35 Power Management 38 4Q 2003 R E A L W O R L D S I G N A L P R O C E S S I N G TM

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Page 1: UMTS Application Notes

WIRELESS INFRASTRUCTURE SOLUTIONS GUIDEDigital Signal Processors, ASIC, Digital Upconverters/Downconverters, Data Converters, Amplifiers,

Microcontrollers, Clock Distribution, Serial Gigabit, Interface, Logic, Power Management

INSIDE Signal Chain 4

Timing and Interface 24

Logic 35

Power Management 38

4Q 2003

R E A L W O R L D S I G N A L P R O C E S S I N GTM

Page 2: UMTS Application Notes

TABLE OF CONTENTSGeneral Overview

TI’s High-Performance, Flexible Solutions Enable Lowest Cost/Channelin Wireless Networks 3

Signal Chain

Complete Wireless Signal Chain Solutions 4High-Performance DSPs Increase Base Station System Efficiency 5High-Density Solutions for Voice-over-Packet and Data Transcoding 5Comprehensive and Customizable UMTS Baseband Solution 6ASIC Solutions Enable Next-Generation WI 8 Programmable Quad DDC or DUC for 3G Systems 9 Quad Digital Upconverter Provides Two 3G W-CDMA Channels 10Quad Digital Downconverter Enables UMTS, Multi-Standard

Downconversion 1014-Bit, 400-MSPS DAC with 2×/4× Interpolation 12Dual DACS for I & Q Processing 12Ultra-Low-Power 12-Bit, 40-MSPS Dual DAC 13Low-Cost, Single DAC Family 130.6-GHz to 1-GHz Quadrature Modulators 14Integer-N RF PLL Synthesizer 1412-Bit ADC with Integrated DDC 15Lowest-Power, Lowest-Cost ADC for BTS Receivers 1550-MHz to 400-MHz Cascadeable IF Amplifiers 16High-Speed, Fully Differential Op Amp 16Fixed-Gain, High-Speed Op Amp with Power Down 17Ultra-Low-Distortion, High-Speed Op Amps with Shutdown 172-GHz, Low Distortion, Current Feedback Amplifier 183–9-GHz GBW, Ultra-Low Noise, Voltage Feedback Op Amps 18Ultra-Wide Band, Current Feedback Op Amp with Disable 19Wideband, Ultra-Low-Noise, Voltage Feedback Amplifier 1916-Bit RISC Flash MCU for only $0.99 2016-Bit RISC Flash MCU with Integrated 12-Bit ADC, Multiplier,

and USARTs 20Product Selection Guides 21Timing and Interface Products

Timing and Interface Overview 24 High-Speed, Point-to-Point 8-Channel Gigabit Ethernet Transceivers 25Gigabit Ethernet- and Fibre Channel-Compliant Transceivers 25LVDS SerDes Backplane Transmitter/Receiver Chipsets 2616:1 Serializer/Deserializer Transceivers with PRBS Testability 263- or 4-Channel, Point-to-Point Transmitter and Receiver Pair 27LVPECL/CML/LVDS Repeaters/Translators and Crosspoint Switches 27Multipoint-LVDS for Backplanes and Cables 28Low-Voltage Clock Drivers for Clock-Distribution Applications 28Low-Jitter Clock Multiplier with Programmable Delay and

Phase Alignment 293.3-V ×4 Clock Multiplier with 8 Outputs 29Gunning Transceiver Logic Plus 30Product Selection Guides 31 Logic

16-Bit Buffer/Driver with 3-State Outputs 36 Low-Voltage Quadruple-FET Bus Switch 36 Product Selection Guides 37Power Management

Power Management Overview 38Point-of-Load Power Modules Offer Auto-Track™ Sequencing 3975-W/100-W Converters Offer 90% Efficiency 39Triple-Output Modules Feature 50% Smaller Footprint Plus

Sequencing 40-48 V, 8-Pin, Hot Swap Controllers 40High-Efficiency Synchronous Buck DC/DC Controllers 41Synchronous Buck DC/DC Converters with Integrated MOSFETS 41Tracking Switcher with Integrated FETs for Sequencing 4295% Efficient, 600-mA, Step-Down Converters 42Dual, 4-Amp, MOSFET Gate Driver 43LoadShare Controller for Parallel Power Supplies 43Low-Input-Voltage, Output-Cap-Free 1-A LDOS 44Ultra-Low-Noise, High PSRR, Fast-RF LDO in SOT-23 44Product Selection Guides 45

2 Wireless Infrastructure Solutions Guide Texas Instruments 4Q 2003

TI WORLDWIDE TECHNICAL SUPPORTInternet

TI Semiconductor Product Information Center Home Page

support.ti.comTI Semiconductor KnowledgeBase Home Page

support.ti.com/sc/knowledgebase

Product Information Centers

Americas

Phone +1(972) 644-5580Fax +1(972) 927-6377Internet/E-mail support.ti.com/sc/pic/americas.htmEurope, Middle East, and Africa

PhoneBelgium (English) +32 (0) 27 45 55 32Finland (English) +358 (0) 9 25173948France +33 (0) 1 30 70 11 64Germany +49 (0) 8161 80 33 11Israel (English) 1800 949 0107Italy 800 79 11 37Netherlands (English) +31 (0) 546 87 95 45Spain +34 902 35 40 28Sweden (English) +46 (0) 8587 555 22United Kingdom +44 (0) 1604 66 33 99

Fax +(49) (0) 8161 80 2045E-mail [email protected] support.ti.com/sc/pic/euro.htmJapan

Fax International +81-3-3344-5317Domestic 0120-81-0036

Internet/E-mail International support.ti.com/sc/pic/japan.htmDomestic www.tij.co.jp/pic

Asia

PhoneInternational +886-2-23786800Domestic Toll-Free Number

Australia 1-800-999-084China 108-00-886-0015Hong Kong 800-96-5941Indonesia 001-803-8861-1006Korea 080-551-2804Malaysia 1-800-80-3973New Zealand 0800-446-934Philippines 1-800-765-7404Singapore 800-886-1028Taiwan 0800-006800Thailand 001-800-886-0010

Fax 886-2-2378-6808E-mail [email protected] support.ti.com/sc/pic/asia.htm C010203

Important Notice: The products and services of Texas Instruments Incorporated and its subsidiaries describedherein are sold subject to TI’s standard terms and conditions of sale. Customers are advised to obtain the mostcurrent and complete information about TI products and services before placing orders. TI assumes no liability forapplications assistance, customer’s applications or product designs, software performance, or infringement ofpatents. The publication of information regarding any other company’s products or services does not constitute TI’sapproval, warranty or endorsement thereof.

The black/red banner, Real World Signal Processing, Auto-Track, SWIFT, MicroStar Jr., OMAP,Predictive Gate Drive, TMS320C6000, C6000, TMS320C64x, PowerPAD, TImeBuilder,TPS40K, and Excalibur are trademarks of Texas Instruments. Bluetooth is a registered trade-mark of the Bluetooth SIG, Inc. FireWire is a trademark of Apple Computer Inc. i.LINK is atrademark of Sony Corporation. Intel is a registered trademark of Intel Corporation.

© 2003 Texas Instruments IncorporatedPrinted in U.S.A. at Earth Color, Houston, Texas

Cover photos used with permission from Ericsson.

Page 3: UMTS Application Notes

Generic Wireless Infrastructure System

GENERAL OVERVIEWTI’S HIGH-PERFORMANCE, FLEXIBLE SOLUTIONS ENABLE LOWEST COST/CHANNEL INWIRELESS NETWORKS

4Q 2003 Texas Instruments Wireless Infrastructure Solutions Guide 3

Read more about Wireless Infrastructure solutions at www.ti.com/wisolutionsguide

Transitioning from the voice-centric services of a 2G network tothe multimedia-dominated data of 2.5G and 3G presents design-ers of wireless infrastructure systems with a number of chal-lenges, such as how to reduce cost per channel while effectivelyincreasing capacity, processing higher data rates and supportingseveral multimedia standards simultaneously. At the same timethough, designers must address the usual engineering questionsof size, cost and power consumption.

Base station manufacturers need a broad portfolio of flexibleproducts to provide a large degree of freedom when it comes topartitioning and migrating various critical tasks within systems asthey evolve. Successful manufacturers will be able to efficientlycustomize their system offerings for each cellular technology and

standard, thus enabling network evolution for service providersin a cost-effective manner.

TI’s high-performance solutions enable more simultaneous voiceand data calls so that base station manufacturers can sup-port more user terminals including cell phones, smartphones,wireless PDAs, Internet appliances and other types of devices.This results in improved profitability for the service provider,which ensures customer satisfaction for the infrastructure sys-tem manufacturer. With higher capacity systems capable of high-er data rates, service providers will be able to reduce subscriberchurn and generate more revenue. In addition, TI’s unmatchedsystem expertise will help manufacturers lower developmentcosts and rapidly deliver new 2.5G and 3G systems to market.

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Page 4: UMTS Application Notes

In wireless infrastructure (WI) systems, designers must address several cross-disciplinaryissues in the signal chain or that partition of the system where signals are processed.These challenging issues involve analog, mixed-signal, DSP, and chip-rate solutions, suchas operational amplifiers (op amps). Highly flexible solutions provide system designerswith the right level of hardware/software partitioning for cost-effective system-levelproducts that can be brought to market quickly. In addition, highly flexible WI systemswill better protect the manufacturer’s investment in software.

For 3G base station architectures and Voice-over-Packet (VoP) applications, the combina-tion of TI’s high-performance TMS320C64x™ DSP generation and its leading-edge ASICcapability provides customers with a winning wireless infrastructure solution. And, TI’sunparalleled silicon expertise ensures that system designers receive state-of-the-artASIC capability.

TI’s digital upconverters (DUCs) and digital downconverters (DDCs) lead the industry inperformance. These DDCs and DUCs can support multiple standards from 2G to 2.5Gand 3G. With the recent introduction of the industry’s best performing 14-bit 400-MSPSDAC, TI supports high-intermediate frequencies and 3G multi-carrier applications like thefour-carrier W-CDMA.

Innovative architectures and technology have made TI’s operational amplifiers some ofthe leading solutions in the industry. For example, the patented architecture of theTHS4271 makes it the only op amp to achieve low noise, low distortion, and high slewrate with unity gain stability.

And the THS4302 leverages a new fully complimentary bipolar silicon-germaniumfabrication process to deliver the first op amp with over 10 GHz of gain bandwidth.These devices and a wide selection of fully differential op amps give TI the mostcomprehensive array of high-speed, high-performance amplifiers for wireless infrastruc-ture applications.

General O

verviewSignal Chain

Timing &

InterfaceLogic

Power M

anagement

4 Wireless Infrastructure Solutions Guide Texas Instruments 4Q 2003

COMPLETE WIRELESS SIGNAL CHAIN SOLUTIONS TO KNOW MORE For detailed information about signalchain ICs for wireless infrastructure:

DSPs 5

Comprehensive UMTS 6baseband solution

ASIC 8

DUC/DDC 9

Up/Down converters 10

Data converters 11

Quadrature modulator 14

Synthesizers 14

Amplifiers 16

Microcontrollers 20

Product selection guides 21

Page 5: UMTS Application Notes

Read Wireless Infrastructure Solutions Guide online at www.ti.com/wisolutionsguideRead more about Wireless Infrastructure solutions at www.ti.com/wisolutionsguide

Timer 0

Timer 1

Timer 2

L1 Cache Direct Mapped, 16 KBytes Total

L1D Cache 2-Way Set Associative, 16 KBytes Total

McBSP 1

or

PCI

HPI 32

GPIO8

or

UTOPIA 2

McBSP 0

GPIO16

EMIF 16

Enha

nced

DM

A C

ontr

olle

r (64

Cha

nnel

)

L2 C

ache

/Mem

ory,

4 B

anks

, 1 M

Byt

e To

tal

TMS320C64x™ DSP CoreInstruction Fetch

Instruction Dispatch

Instruction Decode

Control Registers

AdvancedIn-Circuit Emulation

L1 S1 M1 D1

Data Path 1

Register File A

L2S2M2D2

Register File B

Data Path 2

Interrupt Control

EMIF 64

McBSP 2

PowerDownLogic

PLL

VCP

TCP

DSP Block Diagram – TMS320TCI100 DSP

Memory

16 EMIF

64 EMIF

UTOPIA 2

McBSP

HPI

Memory

Memory

VCP

Host

Bac

kpla

ne

CPUCore

TCP

TMS320TCI100

ChipRate

Tx/RxASIC

HIGH-PERFORMANCE DSPs INCREASE BASESTATION SYSTEM EFFICIENCYTMS320TCI100 DSP

Get samples and application reports at:www.ti.com/sc/device/tms320tci100

Key Features:• Industry-leading 90-nanometer process node

– 720 MHz core performance– Power-efficient design (~600-mW core power)– High integration through state-of-the-art CMOS manufacturing

process• DSP designed for wireless infrastructure applications

– Integrated Viterbi (VCP) and Turbo (TCP) coprocessors– TCP supports over 35 data (384 kbps) channels– VCP enables over 600 voice (7.95 kbps AMR) channels

• Complements TCI110 and TCI120 receive and transmitaccelerators for wideband CDMA

• Rich mix of robust peripherals– Two high-bandwidth (up to 10 Gbps), flexible interfaces to

external memory– Host port with glueless interface to most GPP– UTOPIA II port for interface to communication network– PCI for high-performance standard local bus

• Object-code compatible with all TMS320C6000™ DSPs• Pin compatible with TMS3206415 and TMS320C6416 DSPs

4Q 2003 Texas Instruments Wireless Infrastructure Solutions Guide 5

Applications:• Symbol-rate processing for 2G, 2.5G, and 3G (shown above)• Assist in chip-rate processing• Layer 2 processing in RNC

HIGH-DENSITY SOLUTIONS FOR VOICE-OVER-PACKET (VoP) AND DATA TRANSCODINGTMS320C55x™/TMS320C64x™ DSP Generations + TelogySoftware

Get samples and application reports at:www.ti.com/wisolutions_vop

The TMS320TCI100 DSP also fits well in voice-transcoding,mobile switching-center, and media-gateway applications.Combining the optimized TCI100 solution with TI’s high-density,field-hardened voice-over-packet (VoP) gateway solutionsaddresses the tough challenges facing service providers deploy-ing packet-based networks.

Key Features:• Flexible, carrier-grade solution

– Field-proven Telogy software with over 50 million total portsshipped

– Carrier-certified echo cancellation• Telogy software framework optimized for the TMS320C64x and

TMS320C55x DSP generations• Extensive voice CODEC suite

– Includes wireless codecs such as SMV, EVRC, AMR, WB-AMRand QCELP

Memory 16 EMIF

64 EMIF UTOPIA 2

McBSP

HPI

Memory

Memory

Host

Bac

kpla

ne

CPUCore

TMS320TCI100

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TMS320TCI100 DSP in Symbol-Rate Processing for 2G, 2.5G,and 3G Applications

TMS320TCI100 DSP in a Voice Encode and Decode Application

Applications:• Voice encode and decode (shown above)• Network control processing• Data formatting and routing

Page 6: UMTS Application Notes

6 Wireless Infrastructure Solutions Guide Texas Instruments 4Q 2003

NetworkInterface Card To

Mixed-SignalCard

FromMixed-SignalCard

EMIFB

64-Bit

16-Bit

Closed-LoopControl

EMIFA

HPI orMcBSP

PCI/AHPI

SDRAM

SDRAM

UTOPIADSP

TCI100

DSPTCI100

TCI110

TCI120

COMPREHENSIVE AND CUSTOMIZABLE UMTSBASEBAND SOLUTIONUMTS Baseband Platform

TI’s UMTS wireless infrastructure digital baseband platform is acomprehensive silicon and software product offering thatenables the design of low-cost, high-density UMTS channelcards. The TCI1x platform supports the 3GPP FDD Release 99standard as well as the HSDPA channels as per Release 5 of the3GPP FDD standard. The platform consists of a high-perform-ance wireless infrastructure tailored DSP and tightly coupled pro-grammable accelerators. The design achieves a low cost-per-channel solution by leveraging an efficient pooling of silicon andmemory resources on the chip-rate accelerators and optimallypartitioning the symbol rate and chip rate functions between theDSP and accelerators.

The UMTS platform offering includes:

TMS320TCI100 DSP• Industry leading 720 MHz core• VCP and TCP coprocessors• Pin and code compatible with TMS320C64x™ DSPs

TMS320TCI110• Single device for de-spreading, RACH and searching• Configured and controlled via DSP• The device is highly customizable with parameters such as

number of users, number of fingers per user, correlation lengthsand accumulation lengths configured via DSP software

• Efficient host interface between the TCI110 and the TCI100 DSPresulting in a high-channel-density solution

TMS320TCI120• The TCI120 is a highly configurable downlink chip-rate accelerator• Configured and controlled by the DSP• The channel block is made up of 9 channel groups and supports

a total of 288 downlink channel elements that can be configuredas common or dedicated channels

• The TCI120 supports HSDPA as per Release 5 of the 3GPPstandard

• Support for all the common channels, variable-rate dedicatedchannels, shared channels and compressed mode as perRelease 99 of the 3GPP standard

TCI1x Platform Software• Physical layer reference design which includes layer 1 application

and physical layer services manager• The TCI1x hardware abstraction layer abstracts the hardware

implementation details• Highly optimized symbol- and chip-rate software modules• TCI110 and TCI120 device control software

General O

verviewSignal Chain

Timing &

InterfaceLogic

Power M

anagement

UMTS Platform-Based Channel Card

FingerDespreader

PathMonitorFront

EndInterface

IQ HostInterface

EMIFA

TCI100 DSPChip-RateStreams RACH

PreambleDetector

Synch.Module

PowerEstimator

TCI110

Channel Block

FrontEnd

Memory

Closed-Loop

Control,AICH

EMIF

McBSP 0-5

OutputProcessor

DataFormat

Primary

Diversity

Symbol-RateDSP

Channel Group 1

Channel Group 2

Channel Group 3

Channel Group 4

Channel Group 5

Channel Group 6

Channel Group 7

Channel Group 8

Channel Group 0

TCI120

Page 7: UMTS Application Notes

4Q 2003 Texas Instruments Wireless Infrastructure Solutions Guide 7

TCI1x Development and Evaluation Tools• The familiar Code Composer Studio (CCStudio) suite of

development tools including the debug, profiling, and tuningtools allows for faster software development

• TCIStudio suite of evaluation and analysis tools includesaccelerator probes and performance analysis tools

• The TCIStudio along with the TCI1x Evaluation Module (EVM)help carry out the evaluation and performance analysis of theTCI1x accelerators and software

• The EVM also allows for initial code development before thecustomer’s channel card is ready

Key Features:• Customizable and flexible hardware configured and controlled

through DSP software• Comprehensive silicon and software UMTS baseband product

offering• TCI1x hardware abstraction layer provides a higher level of

device abstraction to the user enabling them to develop ahardware independent application

• CCStudio, TCIStudio and EVM reduce the time-to-market bymaking software development quicker and easier

Applications:• Low-cost, high-channel-density UMTS channel card

Read more about Wireless Infrastructure solutions at www.ti.com/wisolutionsguide

TCIStudio

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Page 8: UMTS Application Notes

8 Wireless Infrastructure Solutions Guide Texas Instruments 4Q 2003

Measure Markers

V p-p (1)Frequency (1)

V base (1)V base (2)

(1) Scale: 44.8 mV/divOffset: –27.5 mV

(2) Scale: 1.0 mV/divOffset: 0.0 mV

Time: 100.0 ps/divDelay: 24.1876 ns

Trigger Level:–380 mV

263.95 mW114 GHz–105.43 mWSource off

Current Mean X YStd Dev266.13 mW

? 220.5 GHx ?–103.81 mW- - - - - - - -

1.6868 mW131.9 GHz ?7.1021 mW- - - - - - - -

24.587 ns24.852 ns265.26 ps3.770 GHz

------- (1)- - - - (1)

1/ X

–66.00 mV69.80 mV135.80 mV

Leading-Edge IP: SoC with Multiple High-Performance SerDesLinks at 3.2-Gbps

3rd Party Tools

3rd PartyInt

TImeBuilder™Modules

(IP)

LibrariesI/Os, Gates

Support P&R

Ext

High PerformanceSR40, SR50

Low PowerGS40, GS50

Docs, AppsTraining

SLI Architect Service

TImePilot(TI + 3rd Party

Tools)

ASIC SOLUTIONS ENABLE NEXT-GENERATIONWIRELESS INFRASTRUCTURE (WI)ASIC

For detailed information, visit:www.ti.com/sc/asicFor further information, please contact your local TI SalesRepresentative (see page 2)

• Global leadership in semiconductor manufacturing– 0.18 µm – 55 nm (Ldrawn) nodes. 95-nm (Ldrawn) Cu product

15% faster than competition– High-performance/density library, I/O, and memory for varying

wireless infrastructure ASIC needs– Packaging: High-performance flip chip

• Experienced, flexible, and global design services– Worldwide design center staff for on-site support– Experienced WI applications team for system-level support– Collaborative design, traditional floor planning, place and route– Design kit with online documentation and full application notes

• System-level integration– Proven success on numerous multi-million gate designs– IP targeting WI, high-speed interfaces, and I/O (RapidIO /

SerDes)– IP-Ethernet, DSP, microprocessor cores, broad array of

peripherals• Comprehensive ASIC cells and tool support

– Robust module library/rich core library– Open EDA tool/flow support– Analog converter functions

Wireless Infrastructure Applications:• Application-specific digital downconverter/digital upconverter• Base-band processing

– Chip-rate and symbol-rate processing for CDMA systems– Combining/decombining/bridge chips

• Specialized applications – Viterbi/turbo decoding – Switching matrix

• Network control and interface processing– Base station uplink– RNC control and protocol processor

• Transcoding/echo canceller – Customized applications

• Embedded SOC designs– High performance– Low peak power

• PA linearization

Twenty Years of ASIC Leadership

Leading-Edge EDA Tools

General O

verviewSignal Chain

Timing &

InterfaceLogic

Power M

anagement

Page 9: UMTS Application Notes

4Q 2003 Texas Instruments Wireless Infrastructure Solutions Guide 9

Read more about Wireless Infrastructure solutions at www.ti.com/wisolutionsguide

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PROGRAMMABLE QUAD DDC OR DUC FOR 3G SYSTEMSGC5016

Get samples, datasheets, application reports, and EVMs at:www.ti.com/sc/device/gc5016

Each one of the GC5016’s four channels can be independentlyprogrammed to perform digital upconversion or downconversionof 3G systems such as W-CDMA or CDMA2000. Customers canchoose to use the device as a programmable digital upconverteror downconverter. Alternatively, they can use the device toimplement a two-channel upconversion and a two-channel down-conversion simultaneously on a single chip.

As with its predecessors, the GC5016 continues to offer thebest performance in the industry by delivering better than 115dB of spurious-free dynamic range, exceeding industry require-ments. While the maximum input data rate for each channel isthe fastest in the industry (at 150 MSPS) by more than 35%, itcan provide even faster input data rates of up to 300 MSPS bycombining two channels for even wider bandwidth applications.

In the upconversion mode, the GC5016 accepts real or complexsignals, interpolates them, and modulates them to selectedintermediate frequencies that are then output to a digital-to-analog converter, such as the DAC904, DAC2904, or DAC5686.In the downconversion mode, the GC5016 accepts digital signalsfrom an analog-to-digital converter, such as the ADS5410.

Key Features:• Input clock rates

– Up to 150 MSPS– Up to 300 MSPS in two-channel even/odd mode

• SFDR: 115 dB • Integrated AGC• FIR filter block consists of 16 cells providing up to 256 filter taps

per channel• 64 parallel input bits and 64 parallel output bits provide flexible

I/O options• Multiple multiplex output options• Future-proof filter performance, clock rate, and bandwidth• Power dissipation: 1 W at 100 MHz with all four channels in

operation

Applications:• Process four-channel UMTS in both downconvert or upconvert

modes, as well as combination upconvert and downconvertmode

• Efficient and economic beamforming• Low power is ideal for micro and pico base stations

GC5016Quad UMTS

DDC

RF to IFDownconvert A/D

One

Sect

or A/DASIC UMTSBasebandProcessor

C6000™ DSP

A/D

• Digitize

• Generate BasebandSignals

• Format/Combine• Spread

• Pulse Shape• Tune to IF

• Convertto Analog

• IF to RFUpconvert

• Amplify

• Downconvert4 UMTS Channels

• Filter/Pulse Shape• Decimate

• RAKE Process• De-spread

• Demodulate• Process

A/D

RF to IFDownconvert

RF to IFDownconvert

RF to IFDownconvert

D/A

D/A

D/A

D/A PA

PA

PA

PA

GC5016Quad UMTS

DUC

ASIC UMTSBasebandProcessor

IF to RFUpconvert

IF to RFUpconvert

IF to RFUpconvert

IF to RFUpconvert

C6000™ DSP

GC5016 UMTS Four-Element Beamform Base Station Receiver

GC5016 Internal Block Diagram

16 16

16 16

16 16

16 16

Format& Mux

Format& Mux

UMTS/CDMA2000Down/Upconversion Channel

UMTS/CDMA2000Down/Upconversion Channel

UMTS/CDMA2000Down/Upconversion Channel

UMTS/CDMA2000Down/Upconversion Channel

Upconversion Mode Channel Detail

FIR FilterInterp 1–16

5–6 StageCIC Filter

Intep 1–256

NCO

GainI I

Q Qor REAL

16

32Frequency

Phase

Downconversion Mode Channel Detail

Five StageCIC FilterDec 1–256

FIR FilterDec 1–16 AGC

NCO

16

16

32

I

Q

Frequency

Phase

GC5016 UMTS Four-Element Beamform Base Station Transmitter

New

Page 10: UMTS Application Notes

10 Wireless Infrastructure Solutions Guide Texas Instruments 4Q 2003

Channel Detail

16

16

32

Dec By 8 - 4 KFive StageCIC Filter

Decimate By 221 Tap Filter

Decimate By 263 Tap Filter Resampler Gain

& Format

I

Q

Output options

Decimation Tap Weights Tap Weights Resample Ratio FormatComplexNCO

FreqPhaseOffset

• 14 to 24 bits• Muxed parallel• Separate serial

• Muxed serial• Control port• Link port

DownconverterChannel

DownconverterChannel

DownconverterChannel

DownconverterChannel

OutputMix

CrossBar

SwitchFrom AIDs To DSP for

Demodulation

Aout

Bout

Cout

Dout

Ain

Bin

Cin

Din

QUAD DIGITAL DOWNCONVERTER ENABLES UMTS, MULTI-STANDARD DOWNCONVERSIONGC4016

Get samples, datasheets, and IBIS models at:www.ti.com/sc/device/gc4016

The GC4016 is the first digital downconverter (DDC) supportingmultiple wireless standards, including 3G standards. The GC4016can downconvert two UMTS/CDMA2000-3x with 2× oversam-pling or one channel with 4× oversampling.

Key Features:• Input rates up to 100 MSPS• Four independent Digital Down Convert (DDC) channels• Independent decimation and resampling, tuning, phase and gain

controls• Built-in diagnostics• > -115 dBc spurious free dynamic range• Low power: 115 mW (per GSM channel), up to 620 mW

(per 3.84-MB UMTS channel)

GC4016 DUC Block Diagram

Applications:• Cellular base transceiver stations: macro, micro, and pico• Repeaters• Wireless local loop• Cable headend and customer premise equipment

General O

verviewSignal Chain

Timing &

InterfaceLogic

Power M

anagement

Channel Detail:16

16I

Q

UpconverterChannel

Ain16 I/QSerial

UpconverterChannel

Bin16 I/QSerial

UpconverterChannel

Cin16 I/QSerial

UpconverterChannel

Din16 I/QSerial

Serial Serial

Baseband Signal Datafrom DSP Resampler

Outputto D/A

FormatGain

Tap Weights Interpolation

Format & GainInterpolate By 2

63 Tap FilterInterpolate By 2

31 Tap Filter

Interp By 8 - 1448Five StageCIC Filter

Frequency

Phase Offset

32

16

Out

ComplexNCO

QuadResampler

22

22

CascadeSum Input

QUAD DIGITAL UPCONVERTER PROVIDESTWO 3G W-CDMA CHANNELSGC4116

Get samples, datasheets, and IBIS models at:www.ti.com/sc/device/gc4116

The GC4116 is the first digital upconverter (DUC) to support mul-tiple standards. The chip can upconvert four narrowband chan-nels and up to two UMTS/CDMA2000-3x channels. The GC4116also can directly accept QPSK, GMSK, or QAM symbols fortransmit filtering or pulse shaping.

Key Features:• Output rates up to 106 MSPS• Four identical upconvert channels• 16-bit real or complex inputs, with summed output• Independent frequency, phase and gain controls• Serial interface controller simplifies interfacing with ASICs or DSPs• Low power: 117 mW (per GSM channel), up to 305 mW

(per UMTS channel)

GC4116 DUC Block Diagram

Applications:• Wireless base transceiver stations: macro, micro, and pico• Repeaters• Wireless local loop• Cable headend and customer premise equipment

Page 11: UMTS Application Notes

4Q 2003 Texas Instruments Wireless Infrastructure Solutions Guide 11

Read more about Wireless Infrastructure solutions at www.ti.com/wisolutionsguide

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CLK1CLK1C

CLK2CLK2C

DA[15:0]

IOUTA1IOUTA2

IOUTB1IOUTB2

DB[15:0]

Demux FIR1,2,3,4x2/x4/x8/x16

x2/x4/x8/x16

2 to 16Fdata

2-16xFdata

2 to 16Fdata

cos

NCO SIF

12-VReference

sin

FdataFIR5

Internal Clock Generation2x-16x PLL Clock Multiplier

16-b DAC

16-b DAC

xsin(x)

xsin(x)

Applications:• Cellular BTS

– CDMA: W-CDMA, CDMA2000, IS-95– TDMA: GSM, IS-136, EDGE/UWC-136

• Baseband I&Q transmit• Low-data-rate interface for quadrature modulation• Single sideband upconversion• Diversity transmit

DAC5686 Internal Block Diagram

Demux FIR1,2,3,4x2/x4/x8/x16

x2/x4/x8/x16

2 to 16Fdata 2 to 16Fdata

2 to 16Fdata

cos

FIR5

SIN

SIN

COS

COS

16-b DAC

16-b DACx

sin(x)

xsin(x)

IOUTA1IOUTA2

IOUTB1IOUTB2

DA[15:0]

DB[15:0]

DAC5686 in Single Sideband Mode

–20

–30

–40

–50

–60

–70

–80

–90

–100

–20

–30

–40

–50

–60

–70

–80

–90

–100

Ref –15 dBm

Center 30.72 MHz

Tx Channel W-CDMA 3PP FWD

Adjacent Channel

Alternate Channel

Bandwidth Power

BandwidthSpacing

BandwidthSpacing

3.84 MHz –17.83 dBm

3.84 MHz5 MHz

LowerUpper

–71.08 dB–70.41 dB

LowerUpper

0.12 dB–69.70 dB

3.84 MHz10 MHz

2.55 MHz Span 25.5 MHz

ATT 5 dB

RBW 30 kHzVBW 300 kHzSWT 2 x*

*1 RM

A

CLRWR

*

NOR

PRN

**

POS –15 dBm

DAC5686 Performance Plot

16-BIT, 500-MSPSPROGRAMMABLE DUAL DACDAC5686

Get datasheets at:www.ti.com/sc/device/dac5686

DAC5686 is designed to allow low data rate transfer from the ASICto the DAC. The DAC5686’s superior performance enables trans-missions of up to four W-CDMA carriers at high intermediate fre-quencies. The DAC5686 can be used in three modes of operation.

A. Dual-ChannelThe interpolation filters increase the DAC update rate, resultingin reduced sin x /x roll off. This greatly relaxes the requirementsfor analog-post filtering.

B. Quadrature Modulation ModeThis mode is used for baseband modulation or a two-channeldigital IF system. While channel selection is done throughcomplex mixing in the ASIC, the DAC5686 interpolates thisincoming low-data-rate signal into higher-data rates. Then, on-chip mixing using a flexible 32-bit programmable NCO providesthe final IF upconversion. Optional fs/4 mixing is available forlower power operation.

C. Single Sideband Upconversion ModeThis mode gives users the best interface to an analog upcon-verter, such as the TRF3701, for low-cost transmit solution.Complex mixing using the NCO can be used to offset thebaseband signal from the LO frequency. The LO feed through anunwanted side band can then be attenuated by IF filtering at RF.

Key Features:• 500-MSPS maximum DAC update rate• 71 dBc SNR in 100-kHz BW for fOUT ≤ 40 MHz• -82 dB IMD for four-tone CW input signal, each tone at

-12 dBFS (fOUT = 15.6, 15.8, 16.2, 16.4 MHz)• Low power dissipation: 440 mW (SSB mode)• Selectable 2× to 16× interpolation, dual-channel• On-chip 2×–16× PLL clock multiplier, PLL bypass mode• Differential scalable current outputs: 2 mA to 20 mA• 1.8-V digital / 3.3-V analog supply• 1.8-V / 3.3-V CMOS-compatible interface• Packaging: 100-HTQFP (PowerPAD™)

W-CDMA ACPR Performance:• W-CDMA 1 carrier:

– 74-dBc baseband, 245.76 MSPS– 77-dBc IF = 30.72 MHz, 245.76 MSPS– 71-dBc IF = 61.44 MHz, 245.76 MSPS

• W-CDMA 2 carrier:– 74-dBc IF = 30.72 MHz, 245.76 MSPS– 71-dBc IF = 61.44 MHz, 245.76 MSPS– 67-dBc IF = 122.88 MHz, 491.52 MSPS

• W-CDMA 4 carrier:– 67-dBc IF = 61.44 MHz, 245.76 MSPS– 64-dBc IF = 122.88 MHz, 491.52 MSPS

New

Page 12: UMTS Application Notes

12 Wireless Infrastructure Solutions Guide Texas Instruments 4Q 2003

14-BIT, 400-MSPS DAC WITH 2X/4X INTERPOLATIONDAC5674

Get samples, datasheets, app reports and EVMs at: www.ti.com/sc/device/dac5674

The DAC5674 is a digital-to-analog converter integrated with acascade of up to two 2× interpolation filters. The digital filteringoption allows either a low pass or high pass mode whichenables users to select the higher-order image for increased out-put frequency, potentially reducing an IF mixer stage. The low-pass interpolation mode provides excellent SFDR performancethat enables multi-carrier architectures in the first Nyquist zoneof up to 40-MHz IF with relaxed filter requirements.

Key Features:• High W-CDMA ACPR:

– 73 dB @ 15.36-MHz single carrier– 70 dB @ 46.08-MHz single carrier and 19.2-MHz dual carrier

• 2× or 4× interpolation with configurable low-pass/high-pass mode• On-chip PLL with bypass option• 1.8-V Digital and 3.3-V Analog supply operation• 1.8-V/3.3-V CMOS-compatible interface• Packaging: 48-lead PowerPAD™ HTQFP

General O

verviewSignal Chain

Timing &

InterfaceLogic

Power M

anagement

DAC290x

TRF3701

LPF

LO2

IF RFPA

BPF BPF

AnalogQuadrature ModulatorI-DAC

Q-DAC

DAC290x in Baseband Sampling Transmitter System

Applications:• Base stations, WLL, WLAN• Direct digital synthesis (DDS)• Baseband sampling transmitter• Diversity transmitter

DUAL DACS FOR I & Q PROCESSINGDAC2900, DAC2902, DAC2904

Get samples, datasheets, and EVMs at:www.ti.com/sc/device/partnumberReplace partnumber in URL with dac2900, dac2902, or dac2904

The two integrated DAC channels of the DAC290x family enablethe I and Q channels to have close gain matching to maintainlow error-vector magnitudes. These channels also provide highperformance at low cost and low power. The 10-, 12-, and 14-bitfamily is pin compatible, allowing easy resolution upgrades.

Key Features:• High SFDR:

– DAC2900: 68 dB at fOUT = 20 MHz– DAC2902: 70 dB at fOUT = 20 MHz– DAC2904: 78 dB at fOUT = 10 MHz

• Power: 310 mW• Power-down mode: 23 mW• Low glitch: 2 pVs• Internal reference• Packaging: 48-lead TQFP

x2/x4 PLL

x2/x4 DAC

Low data rate(< 200 MSPS)

High Sample Rate(< 400 MSPS)

14-Bit

DAC5674 Internal Block Diagram

Applications:• Cellular BTS:

– CDMA: W-CDMA, CMDA2000, IS-95– TDMA: GSM, IS-136, EDGE/UWC-136

• Low-data-rate interface• Wireless local loop

CH1 –18.48 dBmCH2 –18.57 dBmTotal –15.41 dBmACP Low ¬72.20 dBACP Up –70.22 dB

NOR

Span 20.3 MHz2.03 MHzCenter 19.2 MHz

Ref – 22.6 dBm * Att 5 dB

* RBW 30 kHz* VBW 300 MHz* SWT 15 s

120

100

90

80

70

60

50

40

30 A

1 RMCLRWR

Dual-Carrier W-CDMA with ACPR of 70 dB @ 19.2 MHz

Page 13: UMTS Application Notes

4Q 2003 Texas Instruments Wireless Infrastructure Solutions Guide 13

+1.22-V Reference Reference Control Amp

DACLatch 1

DACLatch 2

12-Bit40-MSPS

I-DAC1

12-Bit40-MSPS

I-DAC2

REFIN +VA +VD

+VDV +VAV

IOUT1

VOUT1

VOUT2

VOUT3

VOUT4

IOUT2

IOUT1

IOUT2

GSET FSA1 FSA2

Data1

Data2

CLK1Clock

Latch12-Bit

String-DAC1

12-BitString-DAC2

12-BitString-DAC3

12-BitString-DAC4

12

A0

A1

A2

A3

Dx

REFV

DIN

Parallel Data Input,[D0:D11]

CLK

PD

CS

STBY

SCLK

SYNC

PDV DGNDV AGNDV

Latch

Latch

Latch

Inpu

t Lat

chan

dD

e-M

ultip

lexe

r

Seri

al-t

o-Pa

ralle

lSh

ift R

egis

ter

V-DAC Section

I-DAC Section

12-Bit DataInterleaved

CLK2

AGND DGND

DAC2932

ULTRA-LOW-POWER 12-BIT, 40-MSPS DUALDACDAC2932

Get samples, datasheets, app reports and EVMs at:www.ti.com/sc/device/dac2932

The DAC2932 is a 12-bit 40-MSPS dual DAC with four integratedvoltage output control DACs. This DAC can be used for I and Q inwireless applications. The additional four voltage output controlDACs provide wireless system cost savings by allowing thedesigner to control transmit and receive path gain and adjust fil-ter and local oscillator frequencies. The use of these four controlDACs simplifies the system design, provides flexibility and canprovide overall system cost savings.

Key Features:• Dual 12-bit, 40-MSPS current output DACs• Four 12-bit Vout DACs for signal path control• Ultra low power: 29 mW• Adjustable full-scale output: 0.5 mA to 2 mA• 3.3-V supplies• Power down mode: 25 µW• Budgetary pricing: U.S. $7.95/1 KU• Packaging: 48-lead TQFP

Read more about Wireless Infrastructure solutions at www.ti.com/wisolutionsguide

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Single-Channel W-CDMA Signal on DAC904 with 15.36-MHzInput @ 122.88 MSPS

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

Center 15.36 MHz 2.5 MHz Span 25 MHz

cl2cl2

cl1cl1

cu1cu1

cu2cu2

C0C0

Ref Lvl-29 dBm

Marker 1 [T1]-105.48 dBm

27.86000000 MHz

RBWVBWSWT

RF Att

Unit

0 dB

dBm

1 RM

30 kHz300 kHz

2 s

1 [T1]

1

-105.48 dBm27.86000000 MHz

-18.90 dBm-66.51 dB-67.13 dB-67.54 dB-68.45 dB

CH PWRACP UpACP LowALT1 UpALT1 Low

Applications:• Transmit channel

– Wireless base station– Wireless local loop– Digital microwave

LOW-COST, SINGLE DAC FAMILYDAC904/DAC902/THS5671A/THS5661A

Get samples, datasheets, and EVMs at:www.ti.com/sc/device/partnumberReplace partnumber in URL with dac904, dac902, ths5671a, orths5661a

The DAC90x and THS56x1A families are pin-compatible, singleDACs with 8-bit, 10-bit, 12-bit, and 14-bit options. These are thelowest-cost DACs available on the market.

Key Features:• Update rate of 165 MSPS (DAC90x); 125 MSPS (THS56x1A)• Analog supply of 5 V; digital supply of 3 V or 5 V• On-chip, 1.2-V reference• Set-up and hold times of 1 ns• Twos complement or binary input code format (THS56x1A)• Differential current outputs of 2 mA to 20 mA• SFDR > 60 dBc at 27.4 MHz IF at 165 MSPS• Low power: 175 mW at 5 V• Packaging: 28-pin SOIC, 28-pin TSSOP (10- and 8-bit versions are

also available for both families)

DAC2932 Functional Block Diagram

Applications:• Transmit channels

– I and Q– PC card modems: GPRS, CDMA– Wireless network xards (NICs)

• Signal synthesis (DDS)• Portable medical instrumentation• Arbitrary waveform generation (AWG)

Page 14: UMTS Application Notes

14 Wireless Infrastructure Solutions Guide Texas Instruments 4Q 2003

General O

verviewSignal Chain

Timing &

InterfaceLogic

Power M

anagement

QUADRATURE MODULATORSTRF3701/TRF3702

Get datasheets at:www.ti.com/sc/device/partnumberReplace partnumber in URL with trf3701 or trf3702

TRF3701 and TRF 3702 are low-noise quadrature-direct modula-tors capable of converting complex input signals from 0–250MHz IF up to RF. An internal analog combiner sums the real andimaginary components of the RF output. The modulators areimplemented as a double-balanced mixer. An internal LO phasesplitter accommodates a single LO input.

Key Features:• TRF3701: IF to 900 MHz• TRF3702: IF to 2 GHz• Typical optimized carrier suppression > 50 dBc• Typical optimized sideband suppression > 50 dBc• Typical noise floor; -157 dBm/Hz at 700 to 900 MHz• 5-V single supply

DSP/ASIC

DAC

DAC

DAC2904DAC5686

LO1

PARF

Antenna

Duplexer

To ReceiveSection

TRF37010

90

TRF3701 and TRF3702 in Direct Upconversion Architecture

Applications:• Cellular BTS

– CDMA: W-CDMA, CDMA2000, IS-95– TDMA: GSM, IS-136, EDGE/UWC-136

• Wireless local loop• Wireless LAN 802.11• LMDS, MMDS

DVDD15 7 16

8REFIN

CLOCKDATA

LECE

RFINRFIN

111213

22

4 9 3

AGND DGND CPGND

AVDD

M3 M1

MUX

Charge Pump

Reference

CurrentSetting 1

CurrentSetting 2

LockDetect CP13

CP12CP11

CP16 CP14CP15

ENB 14

2

1

MUXOUT

CPOUT

RSET

M2

22

14

22

19

13

LD LD

6

N Divider

PrescalerP/P+1

6-Bit ACounter

13-Bit BCounter

10

65

PowerDown

FunctionLatch

24-Bit DataShift Register

R CounterLatch

A, B CounterLatch

14-Bit RCounter

AVDD VCP

PFD

INTEGER-N RF PLL SYNTHESIZERTRF3750

Get samples, datasheets, app reports and EVMs at: www.ti.com/sc/device/trf3750

The TRF3750 is frequency synthesizer that can be used to imple-ment local oscillators (LO) up to 3 GHz in the RF upconversionand downconversion chains of wireless transmitters andreceivers. A complete Phase Locked Loop (PLL) can be imple-mented using an external loop filter and a Voltage-ControlledOscillator (VCO) together with the TRF3750. The very wide fre-quency range simplifies system complexity and reduces cost.

Key Features:• Supports operation up to 3 GHz• Supply voltage of 2.7 V to 5.5 V• Programmable charge pump currents• Programmable anti-backlash pulse width• Analog and digital lock detect• Low phase noise• Extended VCO control range through independent VCP supply• Hardware and software power down• Packaging: 16-lead TSSOP

Applications:• Cellular BTS:

– CDMA: W-CDMA, CMDA2000, IS-95– TDMA: GSM, IS-136, EDGE/UWC-136

• Portable wireless communications equipment• Wireless local loop• Communications test equipment

TRF3750 Internal Block Diagram

Page 15: UMTS Application Notes

4Q 2003 Texas Instruments Wireless Infrastructure Solutions Guide 15

RF to IFBlock AFE8201

DSPDigital

Baseband

12-BIT ADC WITH INTEGRATED DDCAFE8201

Get samples, datasheets, app reports and EVMs at: www.ti.com/sc/device/afe8201

The AFE8201 is an 80-MSPS, 12-bit ADC that includes a digitaldownconverter (DDC) and user-programmable digital filters. It isdesigned to sample IF signals and digitally mix, filter, and deci-mate the signals to baseband. An integrated 12-bit DAC is includ-ed to control the gain of the IF block. This highly integrateddevice simplifies and reduces costs for receiver applications.

Key Features:• 12-bit, 80-MSPS ADC• Integrated digital down converter• 32-bit NCO• Digital filters• User-programmable coefficients• McBSP interface for TI DSPs• 12-bit control DAC• Budgetary pricing: U.S. $25/1 KU

Read more about Wireless Infrastructure solutions at www.ti.com/wisolutionsguide

LOWEST-POWER, LOWEST-COST ADC FORBTS RECEIVERSADS5410

Get samples, datasheets, and EVMs at:www.ti.com/sc/device/ads5410

The 12-bit, 80-MSPS ADC offers the lowest power at this per-formance level. It is a low-cost alternative to expensive 14-bitADCs and can be implemented in cost-reduction programs forexisting systems or startup of 3G systems.

Key Features:• 12 bit, 80 MSPS• SFDR: 75 dB at 100-MHz IF• SNR: 60 dB at 70-MHz IF• Digital outputs from 1.6 V – 3.3 V in 2s complement• Flexible clocking: Single-ended or differential• Power: 360 mW

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–1000 5 10 15 20 30 403525

Pow

er (d

Bm)

f – Frequency (MHz)

f = 76.8 MSPSf = 57.6 MHz

S

IN

W-CDMA Single-Carrier Measurement

Applications:• Performance supports across cellular standards

– W-CDMA / CDMA2000 / GPRS / EDGE / GSM / IS-95• Wireless local loop / LMDS / MMDS• Point-to-point microwave

Applications:• Receivers

IF Sampled Receive Channel

FIR Filter 2A

DOUT2DOUT1DFSODCLKDINDFSI

FIR Filter 2B

FIR Filter 1CIC Filter 1QuadratureMixer

12-BitPipeline

ADC

AuxiliaryDAC

REFM VCM REFP VBG MCLK MCLKB PWD SYNC RST_N SCK MOSI CS_NMISO

PGAS/H

IFPIFM

AUX

NCO

ClockInterface

TimingGenerator

SPI ControlInterface

2 2

2

N

VoltageReference

Dat

a In

terf

ace

Detailed AFE8201 Block Diagram

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Page 16: UMTS Application Notes

16 Wireless Infrastructure Solutions Guide Texas Instruments 4Q 2003

50-MHz TO 400-MHz CASCADEABLE IF AMPLIFIERSTHS9000/THS9001

Get samples, datasheets, app reports and EVMs at: www.ti.com/partnumberReplace partnumber in URL with ths9000 or ths9001

The THS9000 and THS9001 are medium power, cascadeable,gain block optimized for 50-MHz to 400-MHz IF frequencies. Theamplifiers incorporate internal impedance matching to 50 Ω. Thepart mounted on the standard EVM achieves greater than 15 dBinput and output return loss from 50 MHz to 325 MHz with Vs = 5 V, RBIAS = 237 Ω, LCOL = 470 nH. Design requires only 2dc blocking capacitors, 1 power supply bypass capacitor, 1 RFchoke, and 1 bias resistor. The THS9000 comes in a very small2×2-mm leadless MSOP package, and the THS9001 comes in a6-pin SOT23 package. These devices make excellent choices fordriving SAW filters, buffering LOs, or general-purpose IF amplifiers.

Key Features:• OIP3: 37 dBm at 300 MHz• Gain: 15.5 dB• Noise figure: 4.0 dB at 300 MHz• 1 dB compression: 20.6 dBm

21.5 Ω

21.5 Ω392 Ω392 Ω

392 Ω392 Ω

1 nF

V = –5 VCL

100 pF100 pF

0.1 Fµ

0.1 Fµ

PD

+

–In-In+

VCC-

V = 5 VCC-

VIN

VOCMVOCM

THS4503 ADC

HIGH-SPEED, FULLY DIFFERENTIAL OP AMPTHS4502/THS4503

Get samples, datasheets, and EVMs at:www.ti.com/sc/device/partnumberReplace partnumber in URL with ths4502 or ths4503

The THS4502, featuring power-down capability, and theTHS4503, without power-down capability, set new performancestandards for fully differential amplifiers with unsurpassedlinearity, supporting 14-bit operation through 40 MHz.

Key Features:• 370-MHz bandwidth (VCC = ±5 V, Rf = 392 Ω, G = 0 dB)• Slew rate: 2800 V/µs• OIP3 = +38 dBm at 30 MHz (G = 12 dB)• NF = 25 dB (G = 12 dB)• Differential input/differential output• Output common-mode voltage control• Balanced architecture rejects common-mode noise and reduces

even order harmonic distortion

THS4503 Block Diagram

Applications:• Single-ended to differential conversion• Differential ADC driver• Active differential anti-alias filter

General O

verviewSignal Chain

Timing &

InterfaceLogic

Power M

anagement

• VS = 3 V to 5 V• IS is adjustable• Packaging: 6-lead (leadless) MSOP, SOT23-6

Applications:• IF amplifier• TDMA: GSM, IS-136, EDGE/UWE-136• CDMA: IS-95, UMTS, CDMA2000• Wireless local loop• Wireless LAN: IEEE 802.11• Radio links

THS9001 Block Diagram

THS9001

1 6

V = 5 VS

V = 5 VS

RBIAS

COUT

CBYP

CINIFIN

1 nF

1 nF

0.1 Fµ

470 nH

IFOUT

LCOL

237 Ω

3 4

2 5

Page 17: UMTS Application Notes

4Q 2003 Texas Instruments Wireless Infrastructure Solutions Guide 17

Read more about Wireless Infrastructure solutions at www.ti.com/wisolutionsguide

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47 pf 0.1 fµ

NC

V –S

V +S

IF in IF outCblk Cblk

50 Ω

Single-Supply IF Amplifier Application Circuit, G = 8 dB into 50- LoadΩ

50 Ω

30.9 Ω

PD

1213

14

15

16

11 10 98

7

6

54321

-+

FIXED-GAIN, HIGH-SPEED OP AMP WITH POWER DOWNTHS4302

Get samples, datasheets, and EVMs at:www.ti.com/sc/device/ths4302

The THS4302 is an ultra-low-distortion, single-supply-operation,wide-bandwidth, high-speed amplifier ideal for use with high-resolution data converters. These voltage feedback amplifierscan operate from a single 5-V power supply while delivering aperformance level of -88 dBc third-order intermodulation distor-tion (IMD3) at 100 MHz.

Key Features:• 2.4-GHz bandwidth• G = 14 dB (non-inverting)• Slew rate: 5500 V/µs• NF = 16 dB• OIP3 = 39 dBm at 100 MHz (RL = 100 Ω)• High output drive, IO = ±180 mA (typ)• VS = 3 V to 5 V• Evaluation module available• Packaging: Leadless packages

THS4302 Block Diagram

Applications:• High-frequency signal processing• LO drive• High-frequency ADC drivers• High-speed DAC buffers

ULTRA-LOW-DISTORTION, HIGH-SPEED OP AMPS WITH SHUTDOWNTHS4271/THS4275

Get samples, datasheets, and EVMs at:www.ti.com/sc/device/partnumberReplace partnumber in URL with ths4271 or ths4275

The THS4271 and THS4275 are ultra-low distortion and noise,single-ended 5-V operation, wide-bandwidth, high-speed ampli-fiers. They are ideal for use with high-resolution data converters.These voltage-feedback amplifiers have a power supply range of4.5 V to 15 V while delivering a performance level of -90 dB ofharmonic distortion (THD) at 30 MHz.

Key Features:• HD2 = -92 dBc (f = 30 MHz, RL = 150 Ω, VO = IVPP)• HD3 = -95 dBc (f = 30 MHz, RL = 150 Ω, VO = IVPP)• 3-nV/√Hz input noise voltage• 1.4-GHz bandwidth (-3 dB, G = +1)• Slew rate: 1000 V/µs• 25-ns settling time (0.1%)• High output drive, IO = 160 mA (typ)• Wide range of power supplies: ±2.5 V to ±7.5 V

AV = 3.3 VDD V = 5 VCC+

V = –5 VCC–

VOUT

AV = 3.3 VDD

1 nf

THS4271One

Channelof

DAC5686

100 pf

100 pf

+

IOUT1

IOUT2

50 Ω

50 Ω

50 Ω

210 Ω

95.3 Ω

95.3 Ω

301 Ω

301 Ω

0.1 fµ 0.1 fµ

0.1 fµ

Differential to Single-Ended Conversion of High-Speed DAC Output

Applications:• Low-noise differential to single-ended conversion• Differential line receiver• Active anti-alias filtering

For test data, see DAC5686 graph, page 11

Page 18: UMTS Application Notes

3–9-GHz GBW, ULTRA-LOW NOISE, VOLTAGEFEEDBACK OP AMPSOPA846/OPA847

Get samples and datasheets at: www.ti.com/sc/device/partnumber Replace partnumber in URL with opa846 or opa847

The OPA847 combines very-high-gain bandwidth and large signalperformance with an ultra-low input noise voltage (0.85 nV/√Hz),while using only 18 mA of supply current. As a voltage gainstage, the OPA847 is optimized for a flat frequency response ata gain of +20 V/V and is stable down to gain as low as +12 V/V.New external compensation techniques allow the OPA847 to beused at any inverting gain with excellent frequency responsecontrol. Using this technique in a differential ADC interface appli-cation, as shown, can deliver one of the highest dynamic rangeinterfaces available.

+5 V

+5 V

+5 V

ADS542114-Bit

40 MSPS

VIN+

VIN–

VCM

1.7 pF

1.7 pF

100 pF

100 pF

0.001 Fµ

0.1 Fµ

0.001 Fµ

–5 V

–5 V

24.6 dB Gain

1:2

< 5.1 dBNoiseFigure

39 pF

39 pF

100 Ω

2 kΩ

2 kΩ

20 Ω

20 Ω100 Ω

50 SourceΩ850 Ω

850 Ω

OPA847

OPA847

+

+

18 Wireless Infrastructure Solutions Guide Texas Instruments 4Q 2003

General O

verviewSignal Chain

Timing &

InterfaceLogic

Power M

anagement

2-GHz, LOW DISTORTION, CURRENT FEEDBACK AMPLIFIERTHS3202

Get samples, datasheets, app reports and EVMs at:www.ti.com/sc/device/ths3202

The THS3202 is a low-distortion, high slew rate op amp ideallysuited for applications driving loads sensitive to distortion at highfrequencies. It provides well-regulated AC performance charac-teristics with a power supply range of 6.6 to 15 V. The device’slow differential gain/phase error makes it ideal for video linedriver applications, test and measurement systems and RF andIF amplifier stages.

Key Features:• Unity-gain bandwidth: 2 GHz• High slew rate: 9000 V/µs• IMD3 at 120 MHz: –89 dBc (ref measurement circuit)• OIP3 at 120 MHz: 43 dBm (ref measurement circuit)• NF = 17.5 dB (ref measurement circuit)• High output current: ±115 mA into 20 Ω RL• Power supply voltage range: 6.6 V to 15 V• Packaging: 8-lead SO, 8-lead MSOP

536 Ω133 Ω

49.9 Ω

49.9 Ω

0.1 Fµ

0.1 Fµ

V(From 50- source)

IN

Ω

Gain = 8 dB(To 50- load)Ω

+

Measurement Circuit V = ±7.5 VCC

V = –7.5 VCC–

THS3202

THS3202 Block Diagram

44

4240

38

36

34

3230

120

f (MHz)

OIP

(dB

m)

3

140

G = 8 dB (to load)f – f = 200 kHz2 1

160

Output Intercept

180 200 220 240 260

THS3202 Performance Characteristics

Applications:• High dynamic range ADC preamps• Wideband, high gain amplifiers

OPA847 Block Diagram

Minimum Input Noise Offset Voltage Offset Current PriceOperating GBW Voltage Drift (0 to 70°C) Drift (0 to 70°C) Starts

Device Gain (V/V) (MHz) nV/√Hz max (mV/°C) max (nA/°C) at 1KOPA842 1 200 2.60 4 2 $1.45OPA843 3 800 2.00 4 2 $1.49OPA846 7 1750 1.20 1.5 2 $1.59OPA847† 14 3800 0.85 1.5 2 $1.89OPA656* 1 230 7.00 12 0.9 $3.19OPA657* 7 1600 4.80 12 0.9 $3.59

*JFET input trimmed offset drift low grade specifications shown. High grade available with<6 µV/°C max. drift.

2 V , at converter inputPP

Frequency (MHz)10 20 30 40 50

3rd Harmonic

2nd Harmonic

Har

mon

ic D

isto

rtio

n (d

Bc)

–70

–75

–80

–85

–90

–95

–100

–105

–110

Differential OPA847 Driver Distoration

Page 19: UMTS Application Notes

Read Wireless Infrastructure Solutions Guide online at www.ti.com/wisolutionsguide

4Q 2003 Texas Instruments Wireless Infrastructure Solutions Guide 19

Read more about Wireless Infrastructure solutions at www.ti.com/wisolutionsguide

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50

40

30

20

10

Center Frequency (MHz)

0 50 150 250200100

Out

put I

nter

cept

(dB

m)

ULTRA-WIDE BAND, CURRENTFEEDBACK OP AMP WITH DISABLEOPA695

Get samples and datasheets at:www.ti.com/sc/device/opa695

The OPA695 is a very-high bandwidth, current-feedback op ampthat combines 4200-V/µs slew rate and low-input voltage noiseto deliver a precision, low-cost, high-dynamic range IF amplifier.Optimized for high-gain operation, the OPA695 is ideally suitedto buffering SAW filters.

Key Features:• Gain = +2 bandwidth: 900 MHz• Gain = +8 bandwidth: 420 MHz• Ultra-high slew rate: 4200 V/µs• 3rd order intercept: > 40 dBm (f < 50 MHz)

Applications:• Very wideband ADC driver• Video line driver• ARB waveform output driver

2-Tone 3rd-Order Intermodulation Intercept

+12 V

SAWFilter

MatchingNetwork

+OPA695–

P1 P1

P0

P0 = 12 dB – (SAW Loss)

0.1 Fµ

5 kΩ

5 kΩ

50 ΩSource 50 Ω

50 Ω

50 Ω

400 Ω

Low Distortion, 12-dB Gain SAW Driver

50 SourceΩ

100 Ω20 Ω

20 Ω

850 Ω

850 Ω

100 Ω

< 6 dBNoiseFigure

1:2

+5 V

+5 V

OPA687

ADS5422

OPA687

+

+

+5 V

–5 V

–5 V

1.7 pF

80 pF

80 pF

1.7 pF

39 pF

39 pF

VCM

VIN+

VIN–

VCM

WIDEBAND, ULTRA-LOW-NOISE, VOLTAGEFEEDBACK AMPLIFIEROPA687

Get samples and datasheets at:www.ti.com/sc/device/opa687

The OPA687 combines a very high gain bandwidth and large sig-nal performance with an ultra-low input noise voltage while dissi-pating only 18-mA supply current. The low input noise voltageand its very-high, two-tone intercept can be used as a fixed-gainIF amplifier.

Key Features:• High gain bandwidth: 3.8 GHz• Low input voltage noise: 0.95 nV/√Hz• Stable for G ≥ 12• Two-tone, 3rd-order intercept: 43 dBm

Applications:• RF/IF amplifier• Low-distortion ADC driver

Ultra-High Dynamic Range Differential Input ADC Driver

2Vp-p

4Vp-p

0 5 10 20 30 40 50453515 25

Center Frequency (MHz)

3rd-

Orde

r Spu

rious

(dBc

)

–60

–65

–70

–75

–80

–85

Measured 2-Tone, 3rd-Order Distortion for Differential ADCDriver

Page 20: UMTS Application Notes

20 Wireless Infrastructure Solutions Guide Texas Instruments 4Q 2003

General O

verviewSignal Chain

Timing &

InterfaceLogic

Power M

anagement

MSP430F14x Block Diagram

MAB

MDB

ACLK

JTAG

/DeB

UG

SMCLK

ACLK

LFXT1 XT2

8-MHzBasicClock

Flash

32–60kB

Watch-dog

15-Bit

Timer_B7

16-Bit

Timer_A3

16-Bit

ADC12200 kSPS

Auto-ScanV /tempREF

Comp_AUSART0

USART1UART/SPI

UART/SPI

RAM

1/2 kB

Power-On

Reset

Port 1/2withIRQ

Port3/4

Port5/6

RISCCPU

16-Bit

MPY/MAC8-/16-

Bit

SMCLK

MCLK

ACLK

MCLK

SMCLK

8-MHzBasicClock

Flashor ROM1/2/4 kB

RAM128/256 B

Power-On

Reset

Port 1withIRQ

Capability

Port 2withIRQ

Capability

RISCCPU

16-Bit

JTA

G/D

eBU

G

Watch-dog

15-Bit

Timer A316-Bit

Comp_A

16-BIT RISC FLASH MCU FOR ONLY $0.99MSP430F11x1

Get samples, datasheet, application reports, and EVMs at:www.ti.com/sc/msp430

A new class of low-power, advanced RISC-architecture MCUs,TI’s family of Flash-based MSP430 MCUs consume just 250micro-amps at 1 MHz and feature TI’s analog and digital signalprocessing expertise.

Key Features:• Ultra-low-power consumption, 250-µA active, 0.8-µA standby at

2.2 V (typ)• 16-bit RISC architecture enables new applications at a fraction of

the code size • Integrated analog comparator is ideal for precise mixed-signal

measurement• Multifunctional, 16-bit multichannel timer with PWM, capture,

and compare capability• In-system programmable Flash permits last-minute code

changes, field upgrades, and data logging to Flash• The MSP-FET430X110 offers a completely integrated

development environment for only U.S. $49• New, small 4×4-mm QFN packaging available 4Q 2003

Applications:• Monitoring and control

MSP430F11x1 Block Diagram

Applications:• Monitoring and control• Can support initialization of CDC7005 clock synchronizer

16-BIT RISC FLASH MCU WITH INTEGRATED12-BIT ADC, MULTIPLIER, AND USARTsMSP430F14x

Get samples, datasheets, application reports, and EVMs at:www.ti.com/sc/msp430

Experience the ultimate SoC solution for low-power applications.The MSP430F14x features the combination of ultra-low powerconsumption and integrated high-performance analog peripheralsideal for cost, power, and space-sensitive applications.

Key Features:• Ultra-low power consumption: 250-µA active mode, 0.8-µA

standby mode at 2.2 V (typ)• 16-bit RISC architecture enables new applications at a fraction of

the code size• High-performance integrated analog and digital peripherals

including a 200-ksps, 12-bit A/D converter, to reduce system costand speed time-to-market

• Serial communication interface (USART) functions asasynchronous UART or synchronous SPI interface

• Two 16-bit PWM timers allow highly flexible multichannelcapture and compare

• In-system programmable Flash permits last-minute codechanges, field upgrades, and data logging to Flash

• The MSP-FET430P140 offers a completely integrateddevelopment environment for only U.S. $99

Page 21: UMTS Application Notes

4Q 2003 Texas Instruments Wireless Infrastructure Solutions Guide 21

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ArchitectureACL Slew Settling Time to THD Differential VOS Ib Is/amp IOUT

Part Number Supply Voltage Min BW Rate 0.1% / 0.01% 1 MHz Gain/Phase VN mV µA mA mA Single Dual Triple Quad 3 V 5 V ± 5 V ± 15 V V/V MHz V/µs ns (typ) dBc (typ) %/° V/√Hz (max) (max) (typ) (typ) Price1

Voltage-Feedback Op AmpsTHS4001 • • • • 1 270 400 40 – -72 0.04 0.15 12.5 8 5 7.8 100 2.19 THS4011 THS4012 • • • 1 290 310 37 90 -80 0.01 0.01 7.5 6 6 7.8 110 2.29/3.81THS4021 THS4022 • • • 10 350 470 40 145 -72 0.02 0.08 1.5 2 6 7.8 100 1.67/2.79THS4031 THS4032 • • • 2 100 100 60 90 -90 0.015 0.025 1.6 2 6 8.5 90 2.23/3.68THS4041 THS4042 • • • • 1 165 400 120 250 -89 0.01 0.01 14 10 6 8 100 1.25/2.49THS4051 THS4052 • • • 1 70 240 60 130 -89 0.01 0.01 14 10 6 8.5 100 1.20/1.55THS4061 THS4062 • • • 1 180 400 40 140 -72 0.02 0.02 14.5 8 6 7.8 115 1.52/1.92THS4081 THS4082 • • • 1 175 230 43 233 -79 0.01 0.05 10 7 6 3.4 85 1.79/2.78THS4271 • * * 1 1400 970 25 38 <-120 0.007 0.004 2.8 10 18 22 90 2.69THS4275 • * * * 1 1400 970 25 38 <-120 0.007 0.004 2.8 10 18 22 90 2.69THS4601 • • • • 1 440 100 135 170 -77 5.4 4 100 pA 10 80 9.95OPA355 OPA2355 OPA3355 • • • • • 1 450 300 30 120 -81 0.02 0.05 5.8 9 50 pA 8.3 60 1.20/1.99/2.82OPA356 OPA2356 • • • • 1 450 300 30 120 -81 0.02 0.05 5.8 9 50 pA 8.3 60 1.10/1.90OPA627 • • • • 1 16 55 450 550 – – – 4.5 0.1 5 pA 7 45 8.28OPA637 • • • • 2 80 135 300 450 – – – 4.5 0.1 5 pA 7 45 8.28 OPA642 • • 1 450 380 11.5 13 -95 0.007 0.008 2.3 1 45 22 60 3.75

OPA2652 • • 1 700 335 – – -77 0.05 0.03 8 7 15 11 140 1.19 OPA655 • • • 1 400 290 8 17 -92 0.006 0.009 6 2 125 pA 25 60 9.13 OPA656 • • • 1 500 290 10 – -85 0.02 0.05 7 1.8 20 pA 14 70 5.85 OPA657 • • • 7 350 700 10 – -78 – – 4.8 1.8 20 pA 14 70 7.29OPA686 OPA2686 • • • 7 250 600 16 18 -83 0.02 0.02 1.3 1 17 12.4 80 2.89 OPA687 12 600 900 15 17 -85 – – 0.95 1 33 18.5 80 3.49 OPA688 • • • 1 530 1000 – 7 – 0.02 0.01 6.3 6 12 15.8 100 2.65 OPA689 • • • 4 280 1600 – 7 -64 0.02 0.01 4.6 5 12 15.8 100 2.95 OPA690 OPA2690 OPA3690 • • • • 1 500 1700 8 – -83 0.06 0.01 4.5 4 8 5.5 190 1.50/2.32/3.19

OPA2822 • • • 1 400 170 32 – -95 0.02 0.03 2 1.2 12 4.8 150 2.17THS4303 • 5 2500 1000 5 -92 – – 2.4 0.5 6 34 100 –THS4304 • 1 2500 1000 5 -92 – – 2.4 0.5 6 18 100 –OPA842 • • 1 350 400 15 ns – 0.003 0.006 2.6 0.3 20 20.2 ±100 1.35OPA843 • • 3 500 1000 7.5 ns – – 0.001 0.012 2 0.3 20 20.2 ±100 1.39OPA846 • • 7 500 625 10 ns – 0.02 0.02 1.2 0.15 10 12.6 ±80 1.59OPA847 • • 12 600 950 10 ns – – – 0.85 0.1 19 18.1 100/’-75 1.49THS9000 • • 5.8 500 – – – - – – 0.6 – – 100 – –THS9001 • • 5.8 500 – – – - – – 0.6 – – 100 – –OPA698 • • 1 450 1100 8 ns 0.012 0.008 5.6 2 3 15.5 ±120 1.79OPA699 • • 6 285 1500 7 ns 4.1 0.5 8 15.5 ±100 1.85Current-Feedback Op AmpsTHS3001 • • • 1 420 6500 40 – -96 0.01 0.02 1.6 3 10 7.5 120 3.37THS3061 THS3062 • • • 1 300 7000 30 125 – 0.02 0.01 2.6 0.7 2 8.3 145 2.95/4.25

THS3112 • • • 1 110 1550 63 – -78 0.01 0.011 2.2 8 23 4.9 270 3.03 THS3115 • • • • 1 110 1550 63 – -78 0.01 0.011 2.2 8 23 4.9 270 3.03 THS3122 • • • 1 160 1550 64 – -80 0.01 0.011 2.2 6 23 8.4 440 3.75 THS3125 • • • • 1 160 1550 64 – -80 0.01 0.011 2.2 6 23 8.4 440 3.75

OPA658 OPA2658 • • 1 900 1700 11.5 15 -82 0.025 0.02 2.7 4.5 18 4.5 80 1.95/3.12/4.99OPA684 OPA2684 OPA3684/ • • • 1 170 780 – – -82 0.04 0.02 3.7 1.5 5 3.4 160 1.3/1.97

OPA46841Suggested resale price in U.S. dollars in quantities of 1,000. Preview devices are listed in blue.

New devices are listed in red.Continued on next page

HIGH-SPEED AMPLIFIERS

VFB

CFB

Diff

I/OFE

TPG

AC-

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22 Wireless Infrastructure Solutions Guide Texas Instruments 4Q 2003

General O

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Power M

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D/A CONVERTERSUpdate Settling Power DNL INL

Device Resolution Supply Rate Time Number Typ Max Max Pin/Name (Bits) (V) (MSPS) (ns) of DACs (mW) (±LSB) (±LSB) Package Price1

DAC904 14 3.0 to 5.0 165 30 1 170 1.75 2.5 28 SOP 6.2528 TSSOP

THS5671A 14 3.0 to 5.0 125 35 1 175 3.5 7 28 SOP 8.0028 TSSOP

DAC902 12 3.0 to 5.0 165 30 1 170 1.75 2.5 28 SOP 6.2528 TSSOP

THS5661A 12 3.0 to 5.0 125 35 1 175 2.0 4 28 SOP 6.2528 TSSOP

DAC900 10 3.0 to 5.0 165 30 1 170 0.5 1 28 SOP 4.2528 TSSOP

THS5651A 10 3.0 to 5.0 125 35 1 175 0.5 1 28 SOP 4.2528 TSSOP

DAC2904 14 3.3 to 5.0 125 30 2 310 48TQFP 20.19DAC2902 12 3.3 to 5.0 125 30 2 310 2.5 3 48 TQFP 15.41DAC2900 10 3.3 to 5.0 125 30 2 310 1 1 48 TQFP 9.19DAC5675 14 3 400 5 1 820 2 4 48 HTQFP 29.75DAC5686 14 1.8/3.3 500 12 2 400 TBD TBD 100 HTQFP 42.00DAC2932 12 2.7 to 3.3 40 25 2 29 0.5 2 48 TQFP 7.95DAC5674 12 1.8/3.3 400 20 1 420 2 3.5 48 HTQFP 21.00

1Suggested resale price in U.S. dollars in quantities of 1,000. Preview devices are listed in blue.

A/D CONVERTERSSample Power Analog DNL INL

Device Resolution Rate Supply Analog Typ Input BW Max Max SNR Pin/Name (Bits) (MSPS) (V) Inputs (mW) (MHz) (±LSB) (±LSB) (dB) Package Price1

ADS5410 12 80 1 360 1000 1 2 67 48 TQFP 23.00ADS5422 14 62 5 1 1200 300 1 72 64 TQFP 29.00

64 LQFPADS809 12 80 5 1 880 1000 1.7 6 65 48 TQFP 23.75AFE8201* 12 80 2.7 to 3.3 1 450 1000 1 2 67 48 TQFP 25.00

1Suggested resale price in U.S. dollars in quantities of 1,000.* AFE8201 integrates programmable DDC, PG4, and Control DAC. Directly interfaces to TI TMS320C5000™ and TMS320C6000™ DSP platforms with McBSP port.

ArchitectureACL Slew Settling Time to THD Differential VOS Ib Is/amp IOUT

Part Number Supply Voltage Min BW Rate 0.1% / 0.01% 1 MHz Gain/Phase VN mV µA mA mA Single Dual Triple Quad 3 V 5 V ± 5 V ± 15 V V/V MHz V/µs ns (typ) dBc (typ) %/° V/√Hz (max) (max) (typ) (typ) Price1

Current-Feedback Op Amps (Continued)THS3201/ THS3202 • • • 1 1800 5100 19 118 -65 0.004 0.006 1.65 4 85 15 115 1.87/2.89OPA685 • • • • 1 1200 4200 3 4 -80 0.1 0.01 1.7 3.5 90 12.9 90 1.89OPA691 OPA2691 OPA3691 • • • • 1 400 2100 10 – -81 0.001 0.01 2.5 2.5 35 5.1 190 1.45/2.32/3.15OPA693 • • 2 800 2400 3 -85 0.02 0.01 1.6 0.7 10 13 120 1.35 OPA695 • • 1 1200 2400 3 -85 0.02 0.01 1.6 0.7 10 13 120 –THS3201 • 1 1800 6200 20 -85 0.006 0.03 1.65 0.7 13 14 115 1.59Fixed-Gain AmplifiersTHS4302 • • • 5 2400 5500 1.5 6 <-120 2.8 4.25 10 37 180 1.97BUF634 • • • 1 180 2000 200 – – 0.4 0.1 4 100 20 15 250 2.84 OPA633 • • 1 260 2500 50 – – 0.1 0.1 15 35 21 100 5.15 OPA692 OPA3692 • • • 1 225 2000 8 – – 0.07 0.02 1.7 0.5 5 5.1 190 1.35/2.98THS9000 • • 6 900 1.00THS9001 • • 6 900 1.00Variable-Gain AmplifiersTHS7530 • • • 230 >1750 – – -63 1.27 44 35 20 3.65

1Suggested resale price in U.S. dollars in quantities of 1,000. Preview devices are listed in blue.New devices are listed in red.

HIGH-SPEED AMPLIFIERS (CONTINUED)

VFB

CFB

Diff

I/OFE

TPG

AC-

Stab

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4Q 2003 Texas Instruments Wireless Infrastructure Solutions Guide 23

Read more about Wireless Infrastructure solutions at www.ti.com/wisolutionsguide

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MSP430 ULTRA-LOW-POWER MICROCONTROLLERS

ProgramDevice1 (kB) SRAM I/O ADC DAC Pins/Package Price2

Flash-Based F1xx Family3 (VCC 1.8 to 3.6 V)MSP430F1101A 1 128 14 Slope 20 DGV, DW, PW, 24 RGE 0.99MSP430C1101 1 128 14 Slope 20 DW, PW, 24 RGE 0.60MSP430F1111A 2 128 14 Slope 20 DGV, DW, PW, 24 RGE 1.34MSP430C1111 2 128 14 Slope 20 DW, PW, 24 RGE 1.10MSP430F1121A 4 256 14 Slope 20 DGV, DW, PW, 24 RGE 1.66MSP430C1121 4 256 14 Slope 20 DW, PW, 24 RGE 1.34MSP430F1122 4 256 14 5-ch ADC10 20 DW, PW, 32 RHB 1.99MSP430F1132 8 256 14 5-ch ADC10 20 DW, PW, 32 RHB 2.23MSP430F122 4 256 22 1 Slope 28 DW, PW, 32 RHB 2.11MSP430F123 8 256 22 1 Slope 28 DW, PW, 32 RHB 2.26MSP430F1222 4 256 22 1 8-ch ADC10 28 DW, PW, 32 RHB 2.36MSP430F1232 8 256 22 1 8-ch ADC10 28 DW, PW, 32 RHB 2.49MSP430F133 8 256 48 1 8-ch ADC12 64 PM, RTD, PAG 2.98MSP430F135 16 512 48 1 8-ch ADC12 64 PM, RTD, PAG 3.59MSP430C1331 8 256 48 1 Slope 64 PM, RTD 1.97MSP430C1351 16 512 48 1 Slope 64 PM, RTD 2.27MSP430F147 32 1024 48 2 8-ch ADC12 64 PM, RTD, PAG 5.01MSP430F1471 32 1024 48 2 Slope 64 PM, RTD, PAG 4.60MSP430F148 48 2048 48 2 8-ch ADC12 64 PM, RTD, PAG 5.71MSP430F1481 48 2048 48 2 Slope 64 PM, RTD 5.30MSP430F149 60 2048 48 2 8-ch ADC12 64 PM, RTD, PAG 6.03MSP430F1491 60 2048 48 2 Slope 64 PM, RTD 5.60MSP430F1554 16 512 48 1 8-ch ADC12 2-ch DAC12 64 PM 4.95MSP430F1564 24 1024 48 1 8-ch ADC12 2-ch DAC12 64 PM 5.65MSP430F1574 32 1024 48 1 8-ch ADC12 2-ch DAC12 64 PM 5.85MSP430F1674 32 1024 48 2 8-ch ADC12 2-ch DAC12 64 PM 6.73MSP430F1684 48 2048 48 2 8-ch ADC12 2-ch DAC12 64 PM 7.45MSP430F1694 60 2048 48 2 8-ch ADC12 2-ch DAC12 64 PM 7.95MSP430F16104 32 5120 48 2 8-ch ADC12 2-ch DAC12 64 PM 8.45MSP430F16114 48 10240 48 2 8-ch ADC12 2-ch DAC12 64 PM 8.95

1C = ROM, F = Flash2Suggested resale unit price in U.S. dollars in quantities of 1,000.3All devices support industrial temperature range.4Planned release 1Q 2004.

WD

T

Tim

er A

Tim

er B

USA

RT

I2 C SVS

BO

R

MPY

Com

p A

DIGITAL DOWNCONVERTERS/UPCONVERTERS (DDC/DUC)Max Automatic Power

Clock Conversion Narrowband Wideband Gain Input Output (max) /Device Rate Type Channels2 Channels3 Control Resolution Resolution SFDR Channel Special Features Price1

GC5016 150 Up and/or down 4 4 16 16 115 250 RSSI meters, 65.00programmable filters, real or complex data formats

GC4016 100 Down 4 2 16 24 115 115 Resampler, serial, or 48.00parallel output formats

GC4116 105 Up 4 2 NA 16 22 115 150 Resampler, 48.00IS-95/CDMA phase equalization

GC1012B 100 Down – 1 12 16 75 850 Fixed decimate by –2, 4, 8, 16, 32, or 64

1Suggested resale price in U.S. dollars in quantities of 1,000.2DAMPS, GSM, IS-95, CDMA2001X3UMTS, DOCSIS, QAM

Page 24: UMTS Application Notes

24 Wireless Infrastructure Solutions Guide Texas Instruments 4Q 2003

General O

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InterfaceLogic

Power M

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TIMING AND INTERFACE PRODUCTSWireless Infrastructure (WI) systems will accommodate a wider range of technologiesthan ever before as the industry moves from 2G to 2.5G and 3G. Advanced wirelesstechnologies like Bluetooth™ personal area networking (PAN), wireless local area net-working (WLAN) with IEEE 802.11 technology, and leading wireless protocols like GSM,CDMA, and UMTS all place higher demands on WI systems for greater processing per-formance without jeopardizing power consumption or cost characteristics.

Designers realize that the increased data rates must be supported by base station andcontroller backplanes and the interconnections between these systems. Typically, thismeans the standard backplane either has to speed up or become wider, moving from16-bit to 32-bit and beyond.

TI’s timing and interface components simplify the generation of timing signals that areused to synchronize system activity and meet today’s stringent clock-signal timingrequirements. A wide selection of high-fan-out drivers, repeaters, and translatorsprovide benefits like low propagation delay, low jitter, and reduced skew, in addition todriving high-performance clocking systems.

TI timing and interface products that support wireless infrastructure applicationsinclude:

• Serializer/Deserializer (SerDes) devices ranging from 100 Mbps to 3.125 Gbps, based onLVDS or LVPECL technology

• Repeaters, translators, and multiplexers transmitting at speeds up to 2.0 Gbps with lessthan 65-ps total jitter

• Single-ended and differential bi-directional transceivers supporting multipoint topologies• Clock solutions that buffer, synchronize, divide, and multiply with low-phase noise• PHY and link 1394 (FireWire™) solutions*• Low-noise GTLP solutions

*See www.ti.com/connectivity for information

TO KNOW MOREFor detailed information about timingand interface ICs for wirelessinfrastructure:

Transceivers and receivers 25

Clock drivers 28

GTLP 30

Product selection guides 31

SerializerSerial Gigabit

SerializerSerial Gigabit

SerializerSerial Gigabit

SerializerSerial Gigabit

SerializerSerial Gigabit

SerializerSerial Gigabit

(BasebandProcessing)

DSP(Baseband

Processing)

ASIC

Serializer

SN65LVDS1021or

SN65LVDS1023

Serializer

SN65LVDS1021or

SN65LVDS1023

Radio Card

(BasebandProcessing)

DSP(Baseband

Processing)

ASIC

Radio Card

(BasebandProcessing)

DSP(Baseband

Processing)

ASIC

Radio Card

NetworkProcessor

Control Card

TX/RXAmps &Filters

TX/RXAmps &Filters

TX/RXAmps &Filters

Memory

Memory

Memory Memory

ClockCircuitry

ClockCircuitry

ClockCircuitry

ClockCircuitry

Serializer

SN65LVDS1021or

SN65LVDS1023

Serializer

SN65LVDS1021or

SN65LVDS1023

Serializer

SN65LVDS1021or

SN65LVDS1023

Serializer

SN65LVDS1021or

SN65LVDS1023

100-MHz to 600-MHz, 10-Bit LVDS Serializer/Deserializer (SerDes) Chipsets

Page 25: UMTS Application Notes

4Q 2003 Texas Instruments Wireless Infrastructure Solutions Guide 25

TX

TLK2208

RX

Linecards

MACASICFPGA

ABCDEFGH

ABCDEFGH

HIGH-SPEED, POINT-TO-POINT 8-CHANNELGIGABIT ETHERNET TRANSCEIVERSTLK2208

Get datasheets at:www.ti.com/sc/device/tlk2208

The TLK2208 is TI’s third generation of gigabit Ethernet trans-ceivers that combines high-port density and ultra-low power in asmall-form-factor footprint. The device provides for high-speed,full-duplex, point-to-point data transmissions based on the IEEE802.3z 1000-Mbps Ethernet specification.

Key Features:• New: eight-channel gigabit Ethernet transceiver• Selectable 8-B/10-B encoding/decoding• Two data sampling modes (multiplex mode or nibble mode)

enable a reduced pin count for interfacing MAC, ASIC, or FPGA• Each channel operates from 1.0 – 1.3 Gbps• Provides a maximum total aggregated data bandwidth of

8.32 Gbps over a copper or optical media interface

GIGABIT ETHERNET- AND FIBRE CHANNEL-COMPLIANT TRANSCEIVERSTLK1201/TLK2201

Get datasheets, samples, and application reports at:www.ti.com/sc/device/partnumberReplace partnumber in URL with tlk1201 or tlk2201

TI’s TLK1201 and TLK2201 gigabit Ethernet- and fibre channel-compliant transceivers require 8-B/10-B encoded data on the par-allel side. The devices can be run in either normal 10-bit mode ora reduced 5-bit mode, which clocks in data on the rising andfalling clock edges (DDR mode).

Key Features:• Low power consumption: <200 mW at 1.25 Gbps• LVPECL-compatible differential I/O on high-speed interface• Single monolithic PLL design• Receiver differential input thresholds 200 mV (min)• IEEE 802.3 gigabit Ethernet compliant• 2.5-V supply voltage for lowest-power operation• 3.3-V tolerant on LVTTL inputs• Hot-plug protection• Industrial temperature range from -40°C to 85°C• Packaging: 64-pin VQFP, thermally enhanced (PowerPAD™)

TLK1201TLK2201

Serial GigabitTLK1201TLK2201

Serial Gigabit

1010101010101010101

101010101010101010110-Bit 10-Bit

10-Bit 10-Bit

CLK CLK

CLK CLK

TLK1201 Block Diagram

TLK2208 Application Diagram

Applications:• Building blocks for developing point-to-point baseband data

transmission over controlled impedance media of 50 Ω• BTS backplane• Radio card-to-controller interconnect

Applications:• High-port-density applications where board space and power are

limited• Point-to-point base station and controller backplane links (shown

above)

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26 Wireless Infrastructure Solutions Guide Texas Instruments 4Q 2003

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LVDS SerDes BACKPLANE TRANSMITTER/RECEIVER CHIPSETSSN65LV1021, SN65LV1023, SN65LV1212, SN65LV1224

Get datasheet and samples at:www.ti.com/sc/device/partnumberReplace partnumber in URL with sn65lv1021, sv65lv1023,sn65lv1212, or sn65lv1224

TI’s SN65LV1021/1023 transmitter and SN65LV1212/1224 receiverfamily of devices is designed to provide BTS backplane solutionsbetween 100 Mbps and 660 Mbps. The chipset has a 10-bitLVTTL parallel-side input/output and a high-speed LVDS serial-side input/output.

Key Features:• 100-Mbps to 400-Mbps serial LVDS data payload bandwidth at

10-MHz to 40-MHz system clock (SN65LV1021/23)• 300-Mbps to 660-Mbps serial LVDS data payload bandwidth at

30-MHz to 66-MHz system clock (SN65LV1212/24) • Pin-compatible superset of NSM DS92LV1021/1212, NSM

DS92LV1023/1224• Chipset (serializer/deserializer) power consumption: <250 mW

(typ) (Tx) and <400 mW (typ) (Rx)• Synchronization mode for faster lock

16:1 SERIALIZER/DESERIALIZERTRANSCEIVERS WITH PRBS TESTABILITYTLK1501, TLK2501, TLK2701, TLK2711, TLK3101, TLK4015

Get datasheets, samples, EVMs, and application reports at:www.ti.com/sc/device/partnumberReplace partnumber in URL with tlk1501, tlk2501, tlk2701,tlk2711, tlk3101, or tlk4015

TI’s TLK1501, TLK2501, TLK2701, TLK2711, TLK3101, and TLK4015provide a 16-to-1 serializer/deserializer (SerDes) function withsupported data rates from 600 Mbps to 3.125 Gbps. The devicesfeature built-in 8-B/10-B encoding/decoding for easier design.

Key Features:• Hot-plug protection• 2.5-V power supply for low-power operation• Programmable voltage output swing on serial output• Interfaces to backplane, copper cables, or optical converters• Rated for industrial temperature range• On-chip 8-bit/10-bit encoding/decoding• On-chip PLL provides clock synthesis from low-speed reference• Receiver differential input thresholds 200 mV (min) • Loss-of-signal (LOS) detection• Packaging: 64-pin VQFP (PowerPAD™) (TLK1501, TLK2501,

TLK2701, TLK3101), 80-pin Microstar Junior™ BGA (GQE)(TLK2711), BGA (TLK4015)

Single-Channel and Multichannel Devices for Radio-to-ControllerCard Interfaces

TXSN65LV1021/1023

Data Data

Clock

PLL PLLTiming/Control

Timing/Control

ClockRecovery

Clock

10 10

RXSN65LV1212/1224

Outp

ut L

atch

Seria

l-to-

Para

llel

Inpu

t Lat

ch

Para

llel-t

o-Se

rial

Radio Card Controller Card

Radio Card

Radio Card

TLK1501

TLK1501

TLK1501

TLK4015

SN65LV1021 Block Diagram

Applications:• Radio-to-controller card links• Antenna-to-receiver link• BTS backplane

Applications:• Radio-to-controller card• Antenna-to-receiver card• BTS backplane

Page 27: UMTS Application Notes

4Q 2003 Texas Instruments Wireless Infrastructure Solutions Guide 27

100

mV/

div.

100 ps/div.

LVDS1002 Gbps 2 –123

Less Than65 ps Total

Jitter

SN65LVDS93: 28:4 (1.820 Gbps)SN65LVDS95: 21:3 (1.365 Gbps)

SN65LVDS94: 4:28 (1.820 Gbps)SN65LVDS96: 3:21 (1.365 Gbps)

Interface

28-bitor

21-bit

Interface

28-bitor

21-bit

Parallelto

Serial

Serialto

Parallel

Serialto

Parallel

Serialto

Parallel

Serialto

Parallel

Phase-Locked

Loop

Parallelto

Serial

Parallelto

Serial

Parallelto

Serial

Phase-Locked

LoopCLK CLK

Data(LVDS)

Clock(LVDS)

D

A

T

A

D

A

T

A

D

A

T

A

D

A

T

A

RD 140 – 455 Mbps

RD 140 – 455 Mbps

RD 140 – 455 Mbps

RD 140 – 455 Mbps

RD 140 – 455 Mbps

3- OR 4-CHANNEL, POINT-TO-POINTTRANSMITTER AND RECEIVER PAIRSN65LVDS96, SN65LVDS95, SN65LVDS93, SN65LVDS94

Get datasheet, samples, EVMs, and application reports at:www.ti.com/sc/device/partnumberReplace partnumber in URL with sn65lvds96, sn65lvds95,sn65lvds93, or sn65lvds94

The SN65LVDS9x family of devices is a 3- or 4-channel (3 or 4data channels, plus 1 clock channel) point-to-point transmitterand receiver pair which supports up to 1.365/1.820 Gbps of datathroughput. It accepts 21/28 LVTTL inputs and outputs 3 or 4LVDS lines in parallel with a clock signal.

Key Features:• Operates with a single 3.3-V supply • 5-V tolerant input • Rising-clock-edge-triggered outputs• Wide phase-lock input frequency range • Low-voltage TTL (LVTTL) logic output levels• Pin compatible with NSC:

– DS90CR213 → SN65LVDS95 DS90CR214 → SN65LVDS96– DS90CR285 → SN65LVDS93 DS90CR286 → SN65LVDS94

• Industrial temperature qualified: TA = -40°C to 85°C

LVPECL/CML/LVDS REPEATERS/TRANSLATORSAND CROSSPOINT SWITCHESSN65LVDS100, SN65LVDS101, SN65CML100SN65LVDS122, SN65LVDS125, SN65LVCP22, SN65LVCP23

Get samples, datasheets, and EVMs at:www.ti.com/sc/device/partnumberReplace partnumber in URL with sn65lvds100, sn65lvds101,sn65cml100, sn65lvds122, sn65lvds125, sn65lvcp22, orsn65lvcp23

These high-speed repeaters/translators and crosspoint switchesfeature internal differential signal paths maintain for very lowpulse and channel-to-channel skews.

Key Features:• Total jitter < 65 ps• Pulse skew < 50 ps• All devices accept LVDS, CML, and LVPECL inputs• 1:1 Translator repeaters

– LVDS100 with LVDS output– LVDS101 with LVPECL output– CML100 with CML output

• Crosspoints– LVDS122 2×2 – LVDS output– LVDS125 4×4 – LVDS output– LVCP22 2×2 – LVDS ouput– LVCP23 2×2 – LVPECL ouput

SN65LVDS9x Block Diagram

Eye Pattern of LVDS100

Applications:• CML/LVPECL-to-LVDS translator• LVDS/CML-to-LVPECL translator• 2×2 Crosspoint and 2:1 Mux• 4×4 Crosspoint, 4:1 Muxs

Applications:• Base station backplane• Radio-to-controller card links

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28 Wireless Infrastructure Solutions Guide Texas Instruments 4Q 2003

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100 Ω

Clock Sourcee.g., 8 kHz, 19 MHz ... X < 100 MHz

100 Ω...

M-LVDS for Clock Distribution Over a Backplane

Applications:• Clock distribution• Base station control and data bus• Synchronization signals• PICMG 3.0 ATCA telephony clock interface

CLK0

CLK0

CLK_SEL

CLK1

CLK1

Q9

Q9

Q8

Q8

Q0

Q0

0

1

9 8 7 6 5 4 3 2 1 0

MUX

MUX

10

CK

SI

EN

11-Bit Shift Register

11-Bit Control Register 12-BitCounter

0 1

CDCLVxx Block Diagram

Applications:• Base stations, BB card, LTU• Cable modem headend

MULTIPOINT-LVDS FOR BACKPLANES ANDCABLESSN65MLVD080, SN65MLVD082, SN65MLVD200,SN65MLVD201, SN65MLVD202, SN65MLVD203, SN65MLVD204,SN65MLVD205, SN65MLVD206, SN65MLVD207

Get samples, datasheets, application notes, and EVMs at:www.ti.com/sc/device/partnumberReplace partnumber in the URL with sn65mlvd080, sn65mlvd082,sn65mlvd200, sn65mlvd201, sn65mlvd202, sn65mlvd203,sn65mlvd204, sn65mlvd205, sn65mlvd206, or sn65mlvd207

TI introduces the industry’s first family of transceivers compliantwith the Multipoint Low-Voltage Differential Signaling (M-LVDS)specification TIA/EIA-899. The SN65MLVD20x parts are half- andfull-duplex single-channel transceivers. The SN65MLVD08xdevices are 8-channel half-duplex transceivers that can operateat 125 MHz with up to 32 devices.

Key Features:• Half power, 10× speed of RS-485• Complies with M-LVDS Standard (TIA/EIA-899) – also supported

by alternative vendors• Supports wired-OR configuration – ideal for control lines• Hot-plugging capability enhances reliability and robustness• Controlled rise times for longer stub lengths

LOW-VOLTAGE CLOCK DRIVERS FOR CLOCK-DISTRIBUTION APPLICATIONSCDCLVP110/CDCLVD110

Get datasheets and application reports at:www.ti.com/sc/device/partnumberReplace partnumber in the URL with cdclvp110 or cdclvd110

TI’s CDCLVP110 and CDCLVD110 low-voltage clock drivers sup-port low-skew, low-jitter differential LVDS/LVPECL or HSTL(selectable) inputs (CLK0, CLK1) to 10 pairs of differentialLVPECL clock outputs with minimum skew.

Key Features:CDCLVP110• 2.5-V or 3.3-V support• Selectable clock input through CLK_SEL• Low-output skew (15 ps) max• Cycle-to-cycle jitter less than 1 ps (rms)• Packaging: 32-pin TQFP

CDCLVD110• Accepts LVDS, LVTIL, HSTL, CML, or LVPECL signaling levels• Signaling-rate capability up to 1.1 GHz• Full rail-to-rail common-mode range• Low output skew (30 ps)• Packaging: 32-pin LQFP (VF)

Page 29: UMTS Application Notes

4Q 2003 Texas Instruments Wireless Infrastructure Solutions Guide 29

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LOW-JITTER CLOCK MULTIPLIER WITHPROGRAMMABLE DELAY AND PHASEALIGNMENTCDCF5801

Get application notes and datasheets at:www.ti.com/sc/device/cdcf5801

The CDCF5801 provides clock multiplication from a referenceclock (REFCLK) signal. It also allows delay or advance of theCLKOUT/CLKOUTB with steps of 2.6 mUI through a uniquealigner.

Key Features:• Low-jitter clock multiplier ×1, ×2, ×4 or ×8

– Input frequency: 12.5 to 240 MHz– Output frequency: 25 to 280 MHz

• Low-jitter clock divider /2, /4 or /8– Input frequency: 12.5 to 240 MHz– Output frequency: 25 to 280 MHz

• 2.6-mUI programmable bidirectional delay steps• One single-ended input and one differential output pair• Output can drive LVPECL, LVDS and LVTTL• Spread spectrum clock tracking ability to reduce EMI• Industrial temperature range: –40°C to 85°C

CDCF5801

StopBP0PWRDNB

Phase Aligner

DelayPLL

Control

CLK

DLY+ DLY–

GNDO

GNDP

00

Div2

Div 2

Div 16

Div4

Div8

11

22

P[1:2]LEADLAGDLYCTRLMULT[0:1]

REFCLK12.5 ... 240 MHz)

10

10

0101

V ODD

V PA/2DD

V PDD

(240 ... 640MHz)

VRE

F/2

DD

CLKOUT(25 ... 280 MHz)CLKOUTB

00 Div 4

Div 811

CDCF5801 Functional Diagram

25

25

25

25

25

25

25

25

InputSelect

Decoding

PLL MUX

8

16

1

2

3

14

15

6

7

10

11

1Y0

1Y1

1Y2

1Y3

2Y0

2Y1

2Y2

2Y3

S2

FBIN

CLKIN

S1 9

CDCVF25084 Block Diagram

Applications:• Phase adjustment• Low-jitter multiplier

3.3-V X4 CLOCK MULTIPLIER WITH 8 OUTPUTSCDCVF25084

Get application notes and datasheets at:www.ti.com/sc/device/cdcvf25084

The CDCVF25084 is a high-performance, low-skew, low-jitter,phase-lock loop clock multiplier. It uses a PLL to precisely align,in both frequency and phase, the output clocks to the input clocksignal including a multiplication factor of four. The CDCVF25084operates from a nominal supply voltage of 3.3 V. The device alsoincludes integrated series-damping resistors in the output driv-ers that make it ideal for driving point-to-point loads.

Key Features:• Phase-locked loop-based zero-delay buffer• Operating frequency range: 10 MHz to 200 MHz• Low jitter (cycle-cycle)• Distributes one clock input to two banks of four outputs• Auto frequency detection to disable device (power-down mode)• Consumes less than 20 µA in power-down mode• Packaging: 16-pin TSSOP

Applications:• Telecom• Datacom

Page 30: UMTS Application Notes

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Slot 20Slot 19Slot 18Slot 3Slot 2Slot 1

0.25”

ZO†

ZO‡

0.94”0.94”0.94”0.94”0.25”22 Ω22 Ω

VTTVTT

Conn

1”

Rcvr

Conn

1”

Rcvr

Conn

1”

Rcvr

Conn

1”

Rcvr

Conn

1”

Rcvr

Conn

1”

Drvr

† Unloaded backplane trace natural impedance (Z ) is 45 . 45 to 60 is allowed with 50 being ideal.‡ Card stub natural impedance (Z ) is 60 .

O

O

ΩΩ

Ω Ω

Single-Bit Representation of a Multipoint Parallel Backplane

2

1

1.98E-08 4.48E-08 6.98E-08

Volts

0.5

0

1.5

TICompetitor A

Signal Integrity: TI vs. Competition

GUNNING TRANSCEIVER LOGIC PLUSGTLP Family

Get samples, datasheets, and application reports at:www.ti.com/sc/gtlp

TI provides backplane interface solutions for telecom/datacommend equipment with the open-drain GTLP technology, which pro-vides better signal integrity and overall system improvement overtraditional logic, allowing you to drive heavily loaded backplanes.

Key Features:• GTLP low-output-voltage swing reduces EMI• Reduced-input GTLP threshold provides adequate noise margin• TI-OPC and OEC circuitry provide improved signal integrity• Ioff, power-up 3-state, and BIAS VCC support live insertion• Bi-directional interface between GTLP and LVTTL signal levels• 5-V tolerant LVTTL I/Os allow mixed-voltage systems• Up to 100-mA drive capability to drive heavily loaded backplanes• Packaging: Space-saving TSSOP (DGG), TVSOP (DGV), and

LFBGA (GKE/GKF) packages

Applications:• Base stations• Networking

Page 31: UMTS Application Notes

4Q 2003 Texas Instruments Wireless Infrastructure Solutions Guide 31

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SERIAL GIGABIT SOLUTIONSDevice Function Data Rate Serial I/F Parallel I/F Power Special Features Price1

TLK1501 Single-ch. 0.6–1.5 Gbps 1 CML ch. 16 LVTTL lines 200 mW Built-in testability Web16:1 SerDes

TLK2501 Single-ch. 1.6–2.5 Gbps 1 CML ch. 16 LVTTL lines 300 mW Built-in testability Web16:1 SerDes

TLK2701 Single-ch. 1.6–2.5 Gbps 1 CML ch. 16 LVTTL lines 300 mW Built-in testability and Web16:1 SerDes K character control

TLK2711 Single-ch. 1.6–2.5 Gbps VML 16 LVTTL lines 350 mW MicroStar Jr.TM BGA packaging Web16:1 SerDes

TLK3101 Single-ch. 2.5–3.125 Gbps 1 VML ch. 16 LVTTL lines 350 mW Built-in testability Web16:1 SerDes

TLK1201 Single-ch. 0.6–1.3 Gbps 1 LVPECL ch. 10 LVTTL lines 200 mW Industrial temperature Web10:1 gigabitEthernet xcvr

TLK2201 Single-ch. 1.0–1.6 Gbps 1 LVPECL ch. 10 LVTTL lines 200 mW JTAG; 5-bit DDR mode WebTLK2201I Single-ch. 1.2–1.6 Gbps 1 LVPECL ch. 10 LVTTL lines 200 mW JTAG; 5-bit DDR mode, industrial Web

10:1 gigabit temp. qualifiedEthernet xcvr

TLK2201JR Single-ch. 1.0–1.6 Gbps 1 LVPECL ch. 10 LVTTL lines 200 mW MicroStar Jr. 5 × 5 Land Grid Web10:1 gigabit Array (LGA)Ethernet xcvr

TLK2208 Eight-ch. of 1.0–1.3 Gbps 8 CML ch. 4/5-bit/ch (nibble 1 W JTAG, MDIO supported Web10:1 or 8:1 gigabit DDR mode), 8/10-Ethernet xcvr bit/ch (multiplex

ch. mode)TLK4015 Four ch. of 16:1 0.8–1.56 Gbps 4 CML ch. 16 LVTTL/ 1 W Four-channel version of TLK1501 Web

xcvr channelSN65LVDS93/94 Four-ch. 140–455 Mbps/ch. 4 LVDS 28 × LVTTL 250 mW/ Supports up to 1.82-Gbps throughput Web

28:4 TX/RX chipset chipSN65LVDS95/96 Four-ch. 140–455 Mbps/ch. 4 LVDS 28 × LVTTL 250 mW/ Supports up to 1.3-Gbps throughput Web

21:3 TX/RX chipset chipSN65LV1021/ Single-ch. 100–400 Mbps 1 LVDS 10 × LVTTL <400 mW/ Low-power solution WebSN65LV1212 10:1 TX/RX chipset totalSN65LV1023/ Single-ch. 300–660 Mbps 1 LVDS 10 × LVTTL <400 mW/ Low-power solution WebSN65LV1224 10:1 TX/RX chipset totalSLK2501/ Single-ch. 4:1 OC-3/12/24/48 1 LVPECL 4 × 622 LVDS 900 mW Auto-rate detection, WebSLK2511 multirate SONET local and remote

xcvr with CDR loop backSLK2701/ Single-ch. 4:1 OC-3/12/24/48 PECL 4 × LVDS 900 mW FEC rate is compatible, WebSLK2721 multirate SONET SLK2721 is optimized for jitter

xcvr with CDR tolerance1Please check www.ti.com for current pricing on these products.

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LVDS LINE DRIVERS AND RECEIVERSMax Max HBM

Drvr/Rcvr Max Supply ESD Output Pulsetpd Speed Current Protection Skew Skew Package

Device (ns) (Mbps) (mA) (kV) # Inputs # Outputs (ps)2 (ps)2 Options Comments Price1

SN65LVDS1 3.1 630 8 15 1 LVTTL 1 LVDS – 300 typ 5-pin SOT-23, Single driver 0.668-pin SOIC

SN65LVDS2 3.6 400 7 15 1 LVDS 1 LVTTL – 600 max 5-pin SOT-23, Single receiver 0.668-pin SOIC

SN65LVDS22 6 400 20 12 2 LVDS 2 LVDS – 200 typ 16-pin SOIC 2:2 MUX (crosspoint) 3.0116-pin TSSOP

SN65LVDS31 2.5 400 35 8 4 LVTTL 4 LVDS 300 max 300 max 16-pin SOIC Quad driver 1.8516-pin TSSOP

SN65LVDS323 3 400 18 8 4 LVDS 4 LVTTL 300 max 400 max 16-pin SOIC Quad receiver 1.8516-pin TSSOP

SN65LVDS333 6 400 23 15 4 LVDS 4 LVTTL 150 typ 200 typ 16-pin SOIC, Quad receiver 2.2216-pin TSSOP

SN65LVDS047 2.8 400 26 8 4 LVTTL 4 LVDS 300 max 300 max 16-pin SOIC, Quad driver 1.8316-pin TSSOP

SN65LVDS048A 3.7 400 15 10 4 LVDS 4 LVTTL 500 max 450 max 16-pin SOIC, Quad receiver 1.8316-pin TSSOP

SN65LVDS3863 4 300 70 4 16 LVDS 16 LVTTL 400 max 600 max 64-pin TSSOP 16-ch. receiver 5.55SN65LVDS387 2.9 630 95 15 16 LVTTL 16 LVDS 150 max 500 max 64-pin TSSOP 16-ch. receiver 5.55SN75LVDS388A3 4 300 40 4 8 LVDS 8 LVTTL 400 max 600 max 38-pin TSSOP Octal receiver 3.25SN65LVDS389 2.9 300 70 4 8 LVTTL 8 LVDS 150 max 500 max 38-pin TSSOP Octal driver 3.25

1Suggested resale price in U.S. dollars in quantities of 1,000.2RL = 100 Ω, CL = 10 pF with max. spec.3Integrated termination option.

LVDS/LVPECL/CML REPEATERS/TRANSLATORS AND CROSSPOINTSMax Max HBM

Drvr/Rcvr Max Supply ESD Output Pulsetpd Speed Current Protection Skew Skew

Device (ns) (Mbps) (mA) (kV) # Inputs # Outputs (ps) (ps) Packaging Comments Price1

SN65LVDS100 0.9 2000 90 5 1 LVDS/CML/LVPECL 1 LVDS – 50 8-pin SOIC, VSSOP Translator/Repeater 2.52SN65LVDS101 0.9 2000 90 5 1 LVDS/CML/LVPECL 1 LVPECL – 50 8-pin SOIC, VSSOP Translator/Repeater 2.52SN65CML100 0.8 1500 30 5 1 LVDS/CML/LVPECL 1 CML – 50 8-pin SOIC, VSSOP Translator/Repeater 2.52SN65LVDS122 0.9 1500 100 4 2 LVDS/CML/LVPECL 2 LVDS 40 50 16-pin SOIC, TSSOP 2×2 Crosspoint 4.75SN65LVCP22 0.8 1000 85 8 2 LVDS/CML/LVPECL 2 LVDS 20 20 16-pin SOIC, TSSOP 2×2 Crosspoint 3.89SN65LVCP23 1 2000 65 5 2 LVDS/CML/LVPECL 2 LVPECL 20 20 16-pin SOIC, TSSOP 2×2 Crosspoint 4.95SN65LVDS125 1 1500 100 8 4 LVDS/CML/LVPECL 4 LVDS 50 50 38-pin TSSOP 4×4 Crosspoint 8.70

1Suggested resale price in U.S. dollars in quantities of 1,000.

Page 33: UMTS Application Notes

4Q 2003 Texas Instruments Wireless Infrastructure Solutions Guide 33

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GTLP TRANSCEIVERSDevice Description Status Price1

SN74GTLP1394 2-bit LVTTL-to-GTLP adjustable-edge-rate bus Xcvr w/ split LVTTL port, Active 2.73feedback path, and selectable polarity

SN74GTLP1395 Two 1-bit LVTTL/GTLP adjustable-edge-rate bus Xcvrs w/ split LVTTL port, feedback path, and Active 1.75selectable polarity

SN74GTLP2033 8-bit LVTTL-GTLP adjustable-edge-rate registered transceiver with split LVTTL port and Active 3.85feedback path

SN74GTLP2034 8-bit LVTTL-GTLP adjustable-edge-rate registered transceiver with split LVTTL port and Active 3.85feedback path

SN74GTLP21395 Two 1-bit LVTTL/GTLP adjustable-edge-rate bus Xcvrs with split LVTTL port, feedback path, and Active 1.75selectable polarity

SN74GTLP22033 8-bit LVTTL-GTLP adjustable-edge-rate registered transceiver with split LVTTL port and Active 3.85feedback path

SN74GTLP22034 8-Bit LVTTL-GTLP adjustable-edge-rate registered transceiver with split LVTTL port and Active 3.85feedback path

SN74GTLP817 GTLP-to-LVTTL 1-to-6 fanout driver Active 2.45SN74GTLPH1612 18-bit LVTTL-to-GTLP adjustable-edge-rate universal bus transceiver Active 5.95SN74GTLPH1616 17-bit LVTTL-to-GTLP adjustable-edge-rate universal bus transceiver with buffered clock outputs Active 5.95SN74GTLPH1645 16-bit LVTTL-to-GTLP adjustable-edge-rate bus transceiver Active 2.45SN74GTLPH1655 16-bit LVTTL-to-GTLP adjustable-edge-rate universal bus transceiver Active 5.95SN74GTLPH16612 18-bit LVTTL-to-GTLP universal bus transceiver Active 4.62SN74GTLPH16912 18-bit LVTTL-to-GTLP universal bus transceiver Active 4.90SN74GTLPH16916 17-bit LVTTL-to-GTLP universal bus transceiver with buffered clock outputs Active 4.90SN74GTLPH16945 16-bit LVTTL-to-GTLP bus transceiver Active 2.10SN74GTLPH306 8-bit LVTTL-to-GTLP bus transceiver Active 3.08SN74GTLPH3245 32-bit LVTTL-to-GTLP adjustable-edge-rate bus transceiver Active 3.71SN74GTLPH32912 36-bit LVTTL-to-GTLP universal bus transceiver Preview CallSN74GTLPH32916 34-bit LVTTL-to-GTLP universal bus transceiver with buffered clock outputs Active 7.00SN74GTLPH32945 32-bit LVTTL-to-GTLP bus transceiver Active 3.15

1Suggested resale price in U.S. dollars in quantities of 1,000.

M-LVDS TRANSCEIVERSPart-to- Signal- Tx Rx

No. No. RX Part ing tpd tpd ICC ESD SupplyDevice of of Input Output Type Skew Rate Typ Typ Max HBM Voltage Pin/Name Description Tx Rx Signal Signal 1 or 2 Max (ps) (Mbps) (ns) (ns) (mA) (kV) (V) Package Price1

SN65MLVD200 Half-duplex 1 1 LVTTL, LVTTL, 1 2500 100 2.3 4.6 26 3 3.3 8-pin SOP 1.84M-LVDS xcvr M-LVDS M-LVDS

SN65MLVD201 Half-duplex 1 1 LVTTL, LVTTL, 1 1000 200 1.5 4.0 24 3 3.3 8-pin SOP 2.10M-LVDS xcvr M-LVDS M-LVDS

SN65MLVD202 Full-duplex 1 1 LVTTL, LVTTL, 1 2500 100 2.3 4.6 26 3 3.3 14-pin SOP 1.84M-LVDS xcvr M-LVDS M-LVDS

SN65MLVD203 Full-duplex 1 1 LVTTL, LVTTL, 1 1000 200 1.5 4.0 24 3 3.3 14-pin SOP 2.10M-LVDS xcvr M-LVDS M-LVDS

SN65MLVD204 Half-duplex 1 1 LVTTL, LVTTL, 1 2500 100 2.3 4.6 26 3 3.3 8-pin SOP 1.84M-LVDS xcvr M-LVDS M-LVDS

SN65MLVD205 Full-duplex 1 1 LVTTL, LVTTL, 1 2500 100 2.3 4.6 26 3 3.3 14-pin SOP 1.84M-LVDS xcvr M-LVDS M-LVDS

SN65MLVD206 Half-duplex 1 1 LVTTL, LVTTL, 2 1000 200 1.5 4.0 24 3 3.3 8-pin SOP 2.10M-LVDS xcvr M-LVDS M-LVDS

SN65MLVD207 Full-duplex 1 1 LVTTL, LVTTL, 2 1000 200 1.5 4.0 24 3 3.3 14-pin SOP 2.10M-LVDS xcvr M-LVDS M-LVDS

SN65MLVD080 Half-duplex 8 8 LVTTL, LVTTL, 1 600 250 1.5 4 180 8 3.3 64-pin TSSOP 4.50M-LVDS xcvr M-LVDS M-LVDS

SN65MLVD082 Half-duplex 8 8 LVTTL, LVTTL, 2 600 250 1.5 4 180 8 3.3 64-pin TSSOP 4.50M-LVDS xcvr M-LVDS M-LVDS

1Suggested resale unit price in U.S. dollars in quantities of 1,000. Please check www.ti.com for current pricing on these products.

Page 34: UMTS Application Notes

34 Wireless Infrastructure Solutions Guide Texas Instruments 4Q 2003

CLOCK DISTRIBUTION CIRCUITSOutput Skew

Package I/O Levels Frequency VCC tsk(o) maxDevice Description Options (Input/Output) (MHz) (V) (ns) Price1

Buffer-Based Clock DistributionCDCVF111 1:9 diff LVPECL 28-pin PLCC LVPECL/LVPECL 0–650 3.3 0.05 WebCDC318A 1:18 clock driver with I2C control interface 48-pin SSOP LVTTL/LVTTL, TTL 0–100 3.3 0.25 WebCDC341 1:8 w/ fast tpd fanout 20-pin SOIC TTL/TTL 0–80 5 0.6 WebCDC351/2351 1:10 w/ fast tpd fanout, 3-state outputs 24-pin SOIC/SSOP LVTTL/LVTTL 0–100 3.3 0.5 WebCDC391 1:6 clock driver with selectable polarity 16-pin SOIC TTL/TTL 0–100 5 0.5 Web

and 3-state outputsCDCLVD110 1:10 programmable 32/TQFP LVDS/LVDS 900 2.5 30 ps typ

low-voltage LVDS clock driverCDCLVP110 1:10 low-voltage 32/LQFP LVPECL or 3.5 GHz 2.5/3.3 30 ps

LVPECL HSTL with HSTL/LVPECLselectable input clock driver

CDCV304 1:4 fanout for PCI-X and general apps. 8-pin TSSOP LVTTL/CMOS 0–140 3.3 0.17 WebCDCVF2310 1:10 clock driver w/ 2 banks for general- 24-pin TSSOP LVTTL/LVTTL 0–170 (VDD=2.3–2.7 V) 2.5/3.3 170 ps @ 2.5 V Web

purpose applications 0–200 (VDD=3–3.6 V) 100 ps @ 3.3 VCDCM1804 1:3 LVPECL clock buffer and addl. LVCMOS 24/MLF LVPECL/ to 800 MHz for LVPECL 3.3 – Web

output and programmable divider LVPECL or LVCMOS to 200 MHz for LVCMOSSN65LVDS104 1:4 diff LVDS 16-pin SOIC/TSSOP LVDS/LVDS 0-315 3.3 0.1 2.22SN65LVDS105 1:5 diff LVDS 16-pin SOIC/TSSOP LVDS/LVDS 0-315 3.3 0.1 2.22SN65LVDS108 1:8 diff LVDS 38-pin TSSOP LVDS/LVDS 0-311 3.3 0.3 4.55SN65LVDS116 1:16 diff LVDS 64-pin TSSOP LVDS/LVDS 0-311 3.3 0.3 5.97

PLL-Based Clock DistributionCDC516/25162 1:16 PLL clock driver 48-pin TSSOP LVTTL/LVTTL 25–125 3.3 0.2 WebCDC536/25362 1:6 PLL clock driver w/ (3) at 1/2× or 2× 28-pin SSOP LVTTL/LVTTL 25–100 3.3 0.5 Web

output, 3-state outputsCDC582/25822 1:12 LV diff PECL PLL clock driver w/ (9) 52-pin TQFP LVPECL/LVTTL 25–100 3.3 0.5 Web

at 1/2× or 2× outputCDC586/25862 1:12 PLL clock driver w/ (9) at 1/2× or 2× 52-pin TQFP LVTTL/LVTTL 25–100 3.3 0.5 Web

output, 3-state outputsCDC5801 Clock multiplier/divider 24/SSOP LVTTL/ 150–500 / 3.3

w/ programmable delay LVPECL or 12.5–62.5and phase alignment LVDS or LVTTL

CDC7005 High-performance clock synthesizer 64/BGA LVTTL/LVPECL 10–650 3.3 200 psCDCF5801 Multiplier/divider with programmable 24/SSOP LVCMOS/ 12.5 to 240 3.3 – Web

delay and phase alignment LVPECL or LVDS 25 to 280or LVTTL

CDCVF2505 1:5 PLL clock driver for general 8-pin TSSOP/SOIC LVTTL/LVTTL 24–200 3.3 0.15 Webpurpose, SSC

CDCVF2508 1:8 low-power PLL clock driver with 16-pin TSSOP/SOIC LVTTL/LVTTL 10–170 2.5/3.3 0.15 Webtwo banks, SSC

CDCVF25084 1:8 low-power 4´ multiplier with two 16-pin TSSOP LVTTL/LVTTL 10 to 180 3.3 150 Webbanks, SSC

CDCVF2509 1:9 low-power PLL clock driver for PC 133 24-pin TSSOP LVTTL/LVTTL 50–175 3.3 0.1 Weband beyond application, SSC

CDCVF2510 1:10 low-power PLL clock driver for PC 133 24-pin TSSOP LVTTL/LVTTL 50–175 3.3 0.1 Weband beyond application, SSC

PLL-Based Clocks for Memory ApplicationsCDCV850 1:10 PLL clock driver for DDR SDRAM 48-pin TSSOP HCSL, Universal 60–140 2.5/3.3 0.075 Web

application, SSC compatible with (except ECL)/SSTL-IItwo-line serial interface

CDCV855 1:4 (plus feedback pair) PLL differential 28-pin TSSOP SSTL-II/ 60–180 2.5 0.075 Webclock driver for DDR applications, SSC SSTL-II, LVTTL

CDCV857B 1:10 PLL differential clock driver for 48-pin TSSOP SSTL-II/SSTL-II 60–200 2.5 0.075 WebDDR applications, SSC

1Suggested resale price in U.S. dollars in quantities of 1,000. Please check www.ti.com for current pricing on these products. Preview devices are listed in blue.2With series output resistors.Notes: For more information regarding test conditions used to obtain measurements, see datasheet.Converted from V/ns datasheet value to ns value, based on 0.4- to 2-V voltage rise/fall.

General O

verviewSignal Chain

Timing &

InterfaceLogic

Power M

anagement

Page 35: UMTS Application Notes

4Q 2003 Texas Instruments Wireless Infrastructure Solutions Guide 35

Read more about Wireless Infrastructure solutions at www.ti.com/wisolutionsguide

LOGICAs wireless infrastructure designers look to increase data throughput, reduce powerconsumption, and shrink form factors, TI’s logic portfolio is constantly advancing while,at the same time, the company is dedicated to providing legacy logic devices.

As the leading provider of logic, TI’s latest technologies are targeted for the fast movingmarket of wireless infrastructure systems. Advanced CMOS families and functions, likethe LVC and ALVC are optimized at 3.3-V VCC. And the CBT and CBTLV families of busswitches offer designers a broad portfolio to meet diverse switching needs.

IntroductionVME

SSTVLittle Logic

TVC

AUC

AVC

ALVTAHC

CBT LV

LVCLVC

ABT

ACL

BCT HC ALSF

AS

CD4000

LS

S

TTL

LVT

FCT

CBTLV

ALVC

GTLP

Growth Maturity Decline Obsolescence

BipolarCMOSBiCMOS

TO KNOW MOREFor detailed information about logic forwireless infrastructure:

Buffer/driver 36

Bus switch 36

Product selection guides 37

Logic Product Life Cycle

Gen

eral

Ove

rvie

wSi

gnal

Cha

inTi

min

g &

Inte

rfac

eLo

gic

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36 Wireless Infrastructure Solutions Guide Texas Instruments 4Q 2003

General O

verviewSignal Chain

Timing &

InterfaceLogic

Power M

anagement

16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTSSN74ALVC16244A/SN74LVC16244A

Get samples and datasheets at:www.ti.com/sc/device/partnumberReplace partnumber in the URL with sn74alvc16244a orsn74lvc16244a

Ideal for base station and networking applications, both the LVCand ALVC families of logic technologies offer solutions for speed-critical 3.3-V system designs. The LVC family is a high-performance version with 0.8-µ CMOS process technology. Withtypical propagation delays of less than 2 ns, ALVC provides24 mA of current drive and static power consumption.

Key Features:• 3.6-ns max tpd

at 3.3 V (ALVC)• 5.2-ns max tpd

at 3.3 V (LVC)• Ioff circuitry (LVC)• Packaging: BGA

LOW-VOLTAGE QUADRUPLE-FET BUS SWITCHSN74CBTLV3125

Get samples and datatsheets at:www.ti.com/sc/device/sn74cbtlv3125

The CBTLV family of bus switches operate at the low-voltage3.3-V operating node. These high-speed bus-connect devicesbenefit designs with greater system speed and reduced powerconsumption. The SN74CBTLV3125 quadruple-FET bus switch fea-tures independent line switches. Each switch is disabled whenthe associated output-enable (OE\) input is high.

Key Features:• Standard SN74CBTLV3125-type pinout• 5-Ω switch connection between two ports• Isolation under power-off conditions• Latch-up performance exceeds 100 mA per JESD 78, Class II

Applications:• Base stations• Networking

ALVC PARAMETRICSParameterName SN74ALVC16244AVoltage nodes (V) 3.3, 2.7, 2.5, 1.8VCC range (V) 2.3 to 3.6Input level LVTTLOutput level LVTTLOutput drive (mA) -24/24tpd max (ns) 3.6Static current 0.04

1OE

1A1 1Y1

1Y2

1Y3

1Y4

1A2

1A3

1A4

1

2

3

5

6

47

46

44

43

3OE

3A1 3Y1

3Y2

3Y3

3Y4

3A2

3A3

3A4

25

13

14

16

17

36

35

33

32

4OE

4A1 4Y1

4Y2

4Y3

4Y4

4A2

4A3

4A4

24

19

20

22

23

30

29

27

26

2OE

2A1 2Y1

2Y2

2Y3

2Y4

2A2

2A3

2A4

Pin numbers shown are for the DGG and DL packages.

48

8

9

11

12

41

40

38

37

2

1

31BSW1A

1OE

9

12

10

13

8

11

3B

4B

A B

(OE)

2B

SW

SW

3A

4A

3OE

4OE

5

4

62BSW2A

2OE

SN75ALVC16244A Logic Diagram (Positive Logic)

SN74CBTLV3125 Block Diagram

Applications:• Base stations• Networking

CBTLV3125 PARAMETERSParameterName SN74CBTLV3125Voltage nodes (V) 3.3, 2.5VCC range (V) 2.3 to 3.6No. of bits 4ron max (ohms) 7tpd max (ns) 0.25

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4Q 2003 Texas Instruments Wireless Infrastructure Solutions Guide 37

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LVC PRODUCTSPack

Orderable Device Package Pins Temp (°C) Status Quantity Price1

SN74LVC16244ADGGR DGG 48 -40 to 85 Active 2000 1.01SN74LVC16244ADGVR DGV 48 -40 to 85 Active 2000 1.01SN74LVC16244ADL DL 48 -40 to 85 Active 25 1.01SN74LVC16244ADLR DL 48 -40 to 85 Active 1000 1.01SN74LVC16244AGQLR GQL 56 -40 to 85 Active 1000 1.12

1Suggested resale price in U.S. dollars.

SN74CBTLV31x BUS SWITCHESPack

Orderable Device Package Pins Temp (°C) Status Quantity Price1

SN74CBTLV3125D D 14 -40 to 85 Active 50 0.81SN74CBTLV3125DBQR DBQ 16 -40 to 85 Active 2500 0.81SN74CBTLV3125DGVR DGV 14 -40 to 85 Active 2000 0.81SN74CBTLV3125DR D 14 -40 to 85 Active 2500 0.81SN74CBTLV3125NSR NS 14 -40 to 85 Active 2000 0.88SN74CBTLV3125PWR PW 14 -40 to 85 Active 2000 0.81

1Suggested resale price in U.S. dollars.

ALVC BUFFER/DRIVERSPack

Orderable Device Package Pins Temp (°C) Status Quantity Price1

SN74ALVC16244ADGGR DGG 48 -40 to 85 Active 2000 1.12SN74ALVC16244ADL DL 48 -40 to 85 Active 25 1.12SN74ALVC16244ADLR DL 48 -40 to 85 Active 1000 1.12SN74ALVC16244AGQLR GQL 56 -40 to 85 Active 1000 1.23

1Suggested resale price in U.S. dollars.

Read more about Wireless Infrastructure solutions at www.ti.com/wisolutionsguide

Page 38: UMTS Application Notes

38 Wireless Infrastructure Solutions Guide Texas Instruments 4Q 2003

LogicG

eneral Overview

Signal ChainTim

ing &Interface

Power M

anagement

AC/DC -48 V 5 V

(Sync. buck/boost/sepic, dual, inverter)

-5 V

Controllers

Synchronous BuckConverters

LDOs

Supervisors

HotSwap

IsolatedDC/DC

Converter

Non-IsolatedPoint of Load

Non-IsolatedPoint of Load

Non-IsolatedPoint of Load

Non-IsolatedPoint of Load

Chassis Level

PFC/PWMControllers

120VAC220VAC

Hot SwapControllers

PWM Controllers,Loadshare Controllers

and FET Drivers

Board-Level Isolation Board-Level Non-Isolated

POWER MANAGEMENT PRODUCTSFor detailed information, visit:power.ti.com

Wireless infrastructure (WI) systems require that designers consider a wide range ofpower management technology. From discrete devices to modular approaches, WIdesigners must select technology that addresses the technical challenge of the systemand offers ancillary benefits in terms of ease-of-use and supply chain reliability andefficiency.

Much of TI’s broad range of power management products has been targeted at wirelessinfrastructure applications. Based on extensive experience with power technology, TI’ssolutions address application challenges that designers face daily. With solutions forboth portable and board power applications, TI has a comprehensive array of powermanagement solutions. In addition, its market-proven record of expertise has made TI’spower technology very easy to use for designers. A wide range of both discrete devicesand isolated and non-isolated modular power technology is available.

Some of the products specific to wireless infrastructure applications include the following:

• DC/DC Controllers and Converters: These devices will generate regulated supply rails. TheTPS54xxx (SWIFT™) family of converters integrates the output FETs to simplify designand the family provides output currents up to 9 A. New controllers, such as theTPS40K™ series, are ideal for a broader range of input voltages and output currents.

• Isolated Plug-In Modules: A number of products are specifically designed for 48-V busapplications. Many devices feature multiple channels for improved integration and lowersystem cost.

• Non-Isolated Plug-In Modules: Modules specifically designed for point-of-load applicationscome in high-performance packaging. A broad range of voltage and current options makethese devices ideal for wireless infrastructure systems.

• Hot Swap Power Managers: New TPS2490, TPS2491 and TPS2350 hot swap devices arespecifically designed for the 48-V bus used in infrastructure systems. These new devicesadd to the family of TPS239x hot swap devices.

• MOSFET Gate Drivers: A powerful family of gate driver ICs, featuring a combined bipolarand MOSFET manufacturing process, delivering fast switching transitions and highcurrent output capability

• PWM Controllers and Special Functions: The industry’s largest selection of controllers andan extensive selection of support ICs facilitate the efficient design of discrete powersupplies.

• Linear Regulators: For the lowest-cost power solution, a broad range of LDOs supportcurrents ranging from 10 mA to 7 A.

TO KNOW MORE For detailed information about powermanagement ICs for wirelessinfrastructure:

DC/DC converters 39

Controllers 40

MOSFET driver 43

LoadShare controller 43

LDOs 44

Product selection guides 45

Board Power Point-of-Load Power Solutions

Page 39: UMTS Application Notes

4Q 2003 Texas Instruments Wireless Infrastructure Solutions Guide 39

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LoadPT4410

+Vsns

–Vsns

21

17–20

13–16

127 118 109VID0 – VID4

4, 5

2, 3

1

RemoteOn/Off

Programming Pins #– Remote Sense

+ Remote Sense

CO

+

+VIN+Vin +Vout

+VOUT

–VOUT

–VIN –Vin –Vout

75-W/100-W CONVERTERS OFFER 90% EFFICIENCYPT4410

Get samples and datasheets at:www.ti.com/sc/device/pt4410

The PT4410 series of power modules are single-output isolatedDC/DC converters housed in a compact 21-pin low-profile (12-mm) package. These modules are rated up to 75 W with loadcurrents as high as 30 A. The output voltage is set within a pre-defined range via a 5-bit input code and is adjustable.

Key Features:• 90% efficiency• Output power: 75 W or 100 W• 36-V to 75-V input• 5-bit programmable output voltage• 1500-V DC isolation• On/off control• Over-current protection• Differential remote sense• Output over-voltage protection• Over-temperature shutdown• Under-voltage lockout• Space-saving solderable copper case• Packaging: Low profile, 12 mm

POINT-OF-LOAD POWER MODULES OFFERAUTO-TRACK™ SEQUENCINGPTH Series of Point-of-Load Modules

Get samples and datasheets at:www.ti.com/sc/device/part numberReplace partnumber in the URL with pthxx000, pthxx050,pthxx060, pthxx010, pthxx0020, pthxx030 where xx = input voltage = 03, 05, or 12

The PTHxx series of plug-in power modules will support step-downDC/DC conversion from a 3.3 V, 5 V or 12 V input with adjustableoutput voltages from 0.8 V to 5.5 V at output currents up to 30 A.The power modules incorporate an innovative new Auto-Tracksequencing technology, which allows multiple modules to bepowered up and down in sequence without external circuitry.

Key Features:• Auto-Track sequencing• Margin-up/down controls• Pre-bias startup capability• Output current up to 30 A• Efficiencies up to 96%• Point-of-Load Alliance (POLA) compatible• Packaging: Low-profile DIP module

PTH05010 Block Diagram

PT4410 Block Diagram

PTH05010(Top view)

89101

1

2

3 4 5

6

7

VIN VOUT

VO Adjust

VO Sense

CIN470 F(Required)

µCOUT330 F(Optional)

µ

RSET (Required)0.1 W, 1%

GND GND

Inhibit

Track

Margin Down

Margin Up

+ +

Load

Applications:• Wireless infrastructure• Telecom• Networking

Applications:• Wireless infrastructure• Telecom• Networking• Servers

Page 40: UMTS Application Notes

40 Wireless Infrastructure Solutions Guide Texas Instruments 4Q 2003

LogicG

eneral Overview

Signal ChainTim

ing &Interface

Power M

anagement

-48V_RTN

TPS2390/91

DC/DCConverterModule

FAULT

EN

RTN

GATE

ISENSE

-VIN

FLTTIME

IRAMP

-48V_IN

R310 k1 W

Ω

R2100 kΩ

R10.02 k1/4 , 1%

ΩΩ

C10.1 Fµ

C2100 F100 V

µ

VOUT-

VOUT+

COUT

Q1IRF530

1

2

3

4 5

6

7

8

C23900 pF

D2

Applications:• On-card hot swap• -48-V distributed power systems

TPS2390/91 Block Diagram

+

+

+

Co1

Co2

Co3

+

DSL, DSP,or ASICChipset

I/O

Logic

Core

18

PT4820

EN 2

EN 1

+Vo1

+Vo2

+Vo3

COM

12, 13

11

16, 17

15

20, 21

19

9,10

3

1

2

4

COM

COM

14

+VIN

CIN

+VIN

–VIN–VIN V Adj3

V Adj2

V Adj1

PT4820/50 Block Diagram

Applications:• Wireless infrastructure• Telecom• Networking

-48 V, 8-PIN, HOT SWAP CONTROLLERSTPS2390/TPS2391

Get samples and datasheets at:www.ti.com/sc/device/partnumberReplace partnumber in the URL with tps2390 or tps2391

The TPS2390 and TPS2391 Hot Swap power managers are opti-mized for use in nominal -48-V systems. Designed for supplyvoltage ranges up to -80 V, they are rated to withstand spikes to-100 V. In conjunction with an external N-channel FET and senseresistor, these controllers can be used to enable the live inser-tion of plug-in cards and modules in powered systems.

Key Features:• Wide input supply range: -36 V to -80 V• Transient rating to -100 V• Programmable current limit and current slew rate• Enable input (EN)• Fault timer to eliminate nuisance trips• Open-drain fault output • Requires few external components• Packaging: 8-pin MSOP

TRIPLE-OUTPUT MODULES FEATURE 50%SMALLER FOOTPRINT PLUS SEQUENCINGPT4820/PT4850

Get samples and datasheets at:www.ti.com/sc/device/partnumberReplace partnumber in the URL with pt4820 or pt4850

The PT4820 and PT4850 Excalibur™ power modules are a seriesof isolated triple-output DC/DC converters that operate from astandard (-48 V) central office supply. These modules are ratedfor a combined output of up to 12 A or 25 A and are designedfor powering mixed-logic applications. Output voltage optionsinclude a low-voltage output for a DSP or ASIC core and twoadditional supply voltages for the I/O and other functions.

Key Features:• Three independently regulated outputs• Internal power-up and power-down sequencing• Output power: 35 W or 75 W• Input voltage range: 36 V to 75 V• 1500-V DC isolation• Dual logic-on/off control• Short-circuit protection (all outputs)• Over-temperature shutdown

Device Auto-Retry OutputTPS2350 Yes PGTPS2390 No FaultTPS2391 Yes FaultTPS2392 No PG/FaultTPS2393 Yes PG/FaultTPS2398 No PGTPS2399 Yes PGTPS2490 No PGTPS2491 Yes PG

Page 41: UMTS Application Notes

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4Q 2003 Texas Instruments Wireless Infrastructure Solutions Guide 41

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VIN

VOUT

ILIM BOOT

HDRV

LDRV

SW

VDD

TPS4000x1 10

9

8

7

6

2

3

4

5

FB

COMP

SS/SD

GND

HIGH-EFFICIENCY SYNCHRONOUS BUCKDC/DC CONTROLLERSTPS4000x

Get samples and datasheets at:power.ti.com

The TPS4000x are controllers for low-voltage, non-isolated syn-chronous buck regulators and drive N-channel power MOSFETs.They control the delays from main switch-off to rectifier turn-onand from rectifier turn-off to main switch turn-on, minimizingdiode losses (both conduction and recovery) in the synchronousrectifier with TI’s proprietary Predictive Gate Drive™ technology.

Key Features:• Input voltage range: 2.25 V to 5.5 V• Output voltage as low as 0.7 V• 1% internal 0.7-V reference• Predictive Gate Drive N-channel MOSFET drivers for higher

efficiency• Externally adjustable soft-start and overcurrent limit• Fixed-frequency, 300-kHz or 600-kHz voltage-mode control• Packaging: 10-lead MSOP PowerPAD™ for higher performance

TPS4000x Block Diagram

Applications:• Wireless infrastructure• Networking equipment• Telecom equipment• Base stations• DSP power

TPS54916 Block Diagram

Input+5 V

TPS54916VIN PH

BOOTPGND

VSENSEVBIAS

AGND

220 µF10 V

10 µF16 V

0.1 µF

0.047 µF

470 µF4 V

6.8 µHOutput+3.3 V

Part IOUT VIN VOUTNumber (A) (V) (V) Price1

TPS54910 9 3–4 Adj. to 0.9 V 5.20TPS54810 8 4–6 Adj to 0.9 V 4.90TPS5461x 6 3–6 0.9, 1.2, 1.5, 1.8, 4.65

2.5, 3.3 V adj.TPS5431x* 3 3–6 0.9, 1.2, 1.5, 1.8 3.45

2.5, 3.3 V adj.*20-pin HTSSOP package1Suggested resale price in U.S. dollars in quantities of 1,000.

SYNCHRONOUS BUCK DC/DC CONVERTERSWITH INTEGRATED MOSFETSTPS54916

For datasheets, samples, app notes, EVMs, and software, go to: power.ti.com/swift

Key Features:• Input voltage range: 3.0 V to 6.0 V• Internal MOSFET switches for high efficiency at full load output

current• Adjustable output voltage range down to 0.9 V with 1.0%

accuracy• Wide PWM frequency: Fixed 350 kHz, 550 kHz, or adjustable

280 kHz to 700 kHz• Load protected by peak current limit and thermal shutdown• PowerGood, enable, and slow-start• Reduces board area and component count• Packaging: 28-pin HTSSOP

Applications:• Low-voltage, high-density distributed power• Point-of-load regulation for high-performance DSPs, FPGAs,

ASICs, and microprocessors• Broadband, networking, and optical communications

infrastructure

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42 Wireless Infrastructure Solutions Guide Texas Instruments 4Q 2003

LogicG

eneral Overview

Signal ChainTim

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Power M

anagement

PG

V = 0.8 VOto VI

VIN

ILIM

SYNCGND FC

EN

L

PGND

PG

FB

TPS6200x

V = 2 VIto 5.5 V

10 µF 10 µF

10 µH

0.1 µF

95% EFFICIENT, 600-mA, STEP-DOWNCONVERTERSTPS6200x

Get datasheets and samples at:www.ti.com/sc/device/partnumberReplace partnumber in URL with tps62000, tps62001, tps62002,tps62003, tps62004, tps62005, tps62006, tps62007, ortps62008

The TPS6200x high-efficiency, synchronous step-down convert-ers are ideal for high-efficiency power conversion in sub-systemswith input voltages between 2.0 V and 5.5 V.

Key Features:• 2.0-V to 6.0-V input voltage range• Adjustable-output voltage range from 0.8 V to VI• Fixed-output voltage options available• Up to 600-mA output current• Synchronizable to external clock signal up to 1 MHz• Highest efficiency over wide-load current range due to PFM

power-save mode• 50-µA quiescent current (typ)• Packaging: 3 × 5 mm2 MSOP-10

TPS6200x Application Diagram

Applications:• DSP• µC processor core• System voltage supply

Power Up

t – Time (ms)0

3

2.5

2

1.5

1

0.5

0

2 4 6 8 10 12 14 16 18 20

Volta

ge (V

)

V = 3.3 VO1

V = 2.5 VO2

V = 1.8 VO3

Ch 4 = PWRGD

Sequential Startup Waveform

Applications:• DSPs, FPGAs, ASICs, and microprocessors that require

simultaneous start up• Broadband, datacom, and optical communications

infrastructure• Precision point-of-load regulation

TRACKING SWITCHER WITH INTEGRATEDFETS FOR SEQUENCINGTPS54680

Get datasheets, EVMs, samples, application notes, and softwaretools at:www.ti.com/sc/device/tps54680

System designers must consider the timing and voltage differ-ences between core and I/O power supplies (i.e., power supplysequencing) during power up and power down. The TPS54680solution easily accomplishes simultaneous power-up and power-down without the need of additional complex sequencing circuitry.

Key Features:• Power-up/down tracking• Input voltage range: 3.0 V to 6.0 V• Internal 30-mΩ, 12-A peak MOSFET switches for high efficiency

at 6-A continuous output • Switching frequency fixed at 350 kHz or adjustable from 280 kHz

to 700 kHz• PowerGood and enable functions• Load protected by peak current limit and thermal shutdown• Packaging: 28-pin HTSSOP PowerPAD™

Page 43: UMTS Application Notes

4Q 2003 Texas Instruments Wireless Infrastructure Solutions Guide 43

Read more about Wireless Infrastructure solutions at www.ti.com/wisolutionsguide

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1Inverting

Inverting

Non-Inverting

Non-Inverting

N/C N/C

INA

OUTB

OUTA

INB

GNDVDD

2

3

45

6

7

8

UCC27323 Block Diagram

Applications:• Switch-mode power supplies:

– Off-line power supplies– DC/DC converters– Board mount power supplies

DUAL, 4-AMP, MOSFET GATE DRIVERUCC27323

Get samples and datasheets at:www.ti.com/sc/device/ucc27323

The UCC27323/4/5 family of high-speed dual-MOSFET driverscan deliver large peak currents into capacitive loads, typical of apower MOSFET gate. Three standard logic options are offered –dual-inverting, dual-noninverting, and one inverting and one non-inverting driver.

Key Features:• High current drive capability of ±4 A at the Miller Plateau region• Industry-standard pin-out• Efficient constant-current sourcing using a unique bipolar and

CMOS output stage• TTL-/CMOS-compatible inputs independent of supply voltage• 4-V to 15-V supply voltage• Packaging: Thermally enhanced MSOP PowerPAD™ with

4.7 C/W θjc

PowerSupplyWith

RemoteSense

V+

S+

1 CS- CS0

LS

EAO

ADJ

CS+

GND

VDD

2

3

4 5

6

7

8

RSENSE

LoadUCC29002

RADJ

V–

S–

UCC29002 Typical Low-Side Current-Sensing Application

System Configurations:• Modules with remote sense capability• Modules with adjust input• Modules with both remote sense and adjust input• In conjunction with the internal feedback E/A of OEM power

supply units

Applications:• Paralleled solution for DC/DC distribution

– Redundant power supplies– SMPS for (web) servers– Server, workstation, and telecom systems

LOADSHARE CONTROLLER FOR PARALLELPOWER SUPPLIESUCC29002

Get samples and datasheets at:www.ti.com/sc/device/ucc29002

The UCC29002 is an advanced, high-performance, low-costLoadShare controller that provides all necessary functions to par-allel multiple independent power supplies or DC-to-DC modules.Targeted for high-reliability applications in telecom distributed-power systems, the controller is suitable for N+1 redundantsystems or high-current applications where off-the-shelf powersupplies need to be paralleled.

Key Features:• High accuracy, better than 1% current share error at full load• High-side or low-side (GND reference) current-sense capability• Ultra-low offset current-sense amplifier• Single-wire LoadShare bus• Full scale adjustability• Intel® SSI LoadShare specification compliant• Disconnect from LoadShare bus at stand-by• LoadShare bus protection against shorts to GND or to the

supply rail• Packaging: 8-pin MSOP minimizes space• Lead-free assembly

Page 44: UMTS Application Notes

TPS725xx Application Diagram

TPS791xx PSRR Performance

3.3-V Bus DC/DCSwitcher

DSP/FPGA

ASIC/DSPDC/DC Switcher

Replacedby TPS72515

1.8-V Bus

1.5 V, 1 A/RESET

TPS72515

PowerManagement

Ripp

le R

ejec

tion

(dB)

100

90

80

70

60

50

40

30

2010 100 1 k

f – Frequency (Hz)10 k 100 k 1 M 10 M

I = 10 mAO

V = 4.3 VIC = 10 FOC = 0.01 F(byp)

I = 100 mAO

LOW-INPUT-VOLTAGE, OUTPUT-CAP-FREE, 1-A LDOS FOR SIMPLE, HIGHLY EFFICIENTREGULATIONTPS725xx/TPS726xx

Get samples, datasheets, and EVMs at: power.ti.com

The TPS725xx/726xx families of Low-Dropout Regulators (LDOs)help you achieve as high as 83% efficiency with the low-input-voltage feature, rivaling a switch-mode solution. These devicesoffer simplicity, minimized component count, and low-noise per-formance in post-regulation applications, as shown in the diagram.

Key Features:• Supports input voltages as low as 1.8 V (and up to 5.5 V),

allowing up to 83% efficiency• No output capacitor required for stability• 1-A LDO with integrated SVS (50-ms delay), TPS725xx• 1-A LDO with integrated SVS (200-ms delay), TPS726xx• 1.5-/1.6-/1.8-/2.5-V fixed-output, and adjustable-output versions

available• Dropout voltage typically 170 mV at 1 A• Less than 1-µA quiescent current in shutdown mode• Packaging: SOT-223-5, DDPAK

ULTRA-LOW-NOISE, HIGH-PSRR, FAST-RF LDOIN SOT-23TPS791xx/TPS792xx/TPS793xx/TPS794xx/TPS795xx/TPS796xx/TPS786xx

Get samples, datasheets, and EVMs at:power.ti.com

The TPS79xxx family of Low-Dropout Regulators (LDOs) featuresextremely high PSRR and ultra-low-noise performance to supportnoise-sensitive applications such as powering RF amplifiers.

Key Features:• Output current: 100 mA to 1.5 A (see table at right)• Input voltage: 2.7 V to 5.5 V• Output capacitor: 1.0-µF or 2.2-µF ceramic• High PSRR: 70 dB at 10 kHz• Ultra-low noise: 15 µVRMS (TPS791xx)• Fast start time: 50 µs (TPS792xx)• Dropout voltage: 38 mV at 100 mA (TPS791xx)• Packaging: SOT-23-5, MSOP-8, SOT-223-5, DDPAK

Applications:• RF• VCOs• DSP/FPGA/ASIC/microprocessor supplies

44 Wireless Infrastructure Solutions Guide Texas Instruments 4Q 2003

LogicG

eneral Overview

Signal ChainTim

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Power M

anagement

Applications:• Post-regulation of switch-mode supplies• Powering core voltages of DSPs, FPGAs, ASICs, and

microprocessors

Io Vo Peak CurrentDevice1 (mA) (V) (mA)TPS791xx 100 1.8/3.3/4.7/adj. 285TPS792xx 100 2.5/2.8/3.0/adj. 285TPS793xx 200 1.8/2.5/2.8/2.85/ 285

3.0/3.3/4.75/adj.TPS794xx 250 1.8/2.5/2.8/3.0/3.3/adj. 700TPS795xx 500 1.6/1.8/2.5/3.0/3.3/adj. 2400TPS796xx 1000 1.8/2.5/2.8/3.0/3.3/adj. 2400TPS786xx 1500 1.8/2.5/2.8/3.0/3.3/adj. 2400

1xx represents the 2 digits of output voltage.

Page 45: UMTS Application Notes

4Q 2003 Texas Instruments Wireless Infrastructure Solutions Guide 45

Read more about Wireless Infrastructure solutions at www.ti.com/wisolutionsguide

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DC/DC CONVERTERS (INTEGRATED SWITCH)Features Packaging

SwitchCurrent

Limit VOUT VOUTIOUT (max) VIN Adj Fix

Device (mA) (mA) (V) (V) (V) Price2

Low Power Step Down (Buck) Converters — up to 1.2 ATPS62200 300 670 2.5 to 6.0 0.7 to 6.0 — 97 1000 0.015 0.1 6 1.29TPS62201 300 670 2.5 to 6.0 — 1.5 97 1000 0.015 0.1 6 1.29TPS62202 300 670 2.5 to 6.0 — 1.8 97 1000 0.015 0.1 6 1.29TPS62203 300 670 2.5 to 6.0 — 3.3 97 1000 0.015 0.1 6 1.29TPS62204 300 670 2.5 to 6.0 — 1.6 97 1000 0.015 0.1 6 1.29TPS62205 300 670 2.5 to 6.0 — 2.5 97 1000 0.015 0.1 6 1.29TPS62206 300 670 2.5 to 6.0 — 2.6 97 1000 0.015 0.1 6 1.29TPS62000 600 1600 2.0 to 5.5 0.8 to 5.0 — 95 1000 0.05 0.1 10 1.49TPS62001 600 1600 2.0 to 5.5 — 0.9 95 1000 0.05 0.1 10 1.49TPS62002 600 1600 2.0 to 5.5 — 1.0 95 1000 0.05 0.1 10 1.49TPS62003 600 1600 2.0 to 5.5 — 1.2 95 1000 0.05 0.1 10 1.49TPS62004 600 1600 2.0 to 5.5 — 1.5 95 1000 0.05 0.1 10 1.49TPS62005 600 1600 2.0 to 5.5 — 1.8 95 1000 0.05 0.1 10 1.49TPS62006 600 1600 2.0 to 5.5 — 2.5 95 1000 0.05 0.1 10 1.49TPS62007 600 1600 2.0 to 5.5 — 3.3 95 1000 0.05 0.1 10 1.49TPS62008 600 1600 2.0 to 5.5 — 1.9 95 1000 0.05 0.1 10 1.49SWIFTTM Step Down (Buck) Converters — up to 9 ATPS54310 3000 6500 3.0 to 6.0 0.9 to 4.5 — 90 700 6.2 1000 20 3.45TPS54311 3000 6500 3.0 to 6.0 — 0.9 90 700 6.2 1000 20 3.45TPS54312 3000 6500 3.0 to 6.0 — 1.2 90 700 6.2 1000 20 3.45TPS54313 3000 6500 3.0 to 6.0 — 1.5 90 700 6.2 1000 20 3.45TPS54314 3000 6500 3.0 to 6.0 — 1.8 90 700 6.2 1000 20 3.45TPS54315 3000 6500 3.0 to 6.0 — 2.5 90 700 6.2 1000 20 3.45TPS54316 3000 6500 3.0 to 6.0 — 3.3 90 700 6.2 1000 20 3.45TPS54372 3000 6500 3.0 to 6.0 0.2 to 4.5 — 90 700 6.2 1000 20 3.45TPS54610 6000 10000 3.0 to 6.0 0.9 to 4.5 — 90 700 11 1000 28 4.65TPS54611 6000 10000 3.0 to 6.0 — 0.9 90 700 11 1000 28 4.65TPS54612 6000 10000 3.0 to 6.0 — 1.2 90 700 11 1000 28 4.65TPS54613 6000 10000 3.0 to 6.0 — 1.5 90 700 11 1000 28 4.65TPS54614 6000 10000 3.0 to 6.0 — 1.8 90 700 11 1000 28 4.65TPS54615 6000 10000 3.0 to 6.0 — 2.5 90 700 11 1000 28 4.65TPS54616 6000 10000 3.0 to 6.0 — 3.3 90 700 11 1000 28 4.65TPS54672 6000 10000 3.0 to 6.0 0.2 to 4.5 — 90 700 11 1000 28 4.65TPS54673 6000 10000 3.0 to 6.0 0.9 to 4.5 — 90 700 11 1000 28 4.65TPS54680 6000 10000 3.0 to 6.0 0.9 to 4.5 — 90 700 11 1000 28 4.65TPS54810 8000 11000 4.0 to 6.0 0.9 to 4.5 — 85 700 11 1000 28 4.90TPS54872 8000 11000 4.0 to 6.0 0.2 to 4.5 — 85 700 11 1000 28 4.90TPS54873 8000 11000 4.0 to 6.0 0.9 to 4.5 — 85 700 11 1000 28 4.90TPS54880 8000 11000 4.0 to 6.0 0.9 to 4.5 — 85 700 11 1000 28 4.90TPS54910 9000 15000 3.0 to 4.0 0.9 to 2.5 — 90 700 11 1000 28 5.20TPS54972 9000 15000 3.0 to 4.0 0.2 to 2.5 — 90 700 11 1000 28 5.20TPS54973 9000 15000 3.0 to 4.0 0.9 to 2.5 — 90 700 11 1000 28 5.20TPS54974 9000 15000 2.2 to 4.0 0.2 to 2.5 — 90 700 11 1000 28 5.20TPS54980 9000 15000 3.0 to 4.0 0.9 to 2.5 — 90 700 11 1000 28 5.20

1Disabled sinking during start-up. New devices are listed in red.2Suggested resale price in U.S. dollars in quantities of 1,000.

Effic

ienc

y (%

)

Switc

hing

Fre

quen

cy(m

ax) (

kHz)

Quie

scen

t Cur

rent

(typ)

(mA)

Shut

dow

n Cu

rrent

(typ)

(µA)

Shut

dow

n

LDO

(mA)

Low

Bat

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Pow

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ood

Pow

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ncin

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Dual

Inpu

t Bus

(3.3,

2.5 V

)

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P

QFN

TSSO

P

SOIC

EVM

PLUG-IN POWER SOLUTIONSInput Bus POUT Isolated VO Range VO

Device1 Voltage (V) or IOUT Outputs (V) Adjustable Price2

Non-Isolated Single Positive OutputPTH03010/20/30/50/60 3.3 15 A, 22 A, 30 A, 6 A, 10 A No 0.8 to 2.5 Yes 14.00, 18.13, 24.63, 9.10, 11.20PTH05010/20/30/50/60 5 15 A, 22 A, 30 A, 6 A, 10 A No 0.8 to 3.6 Yes 14.00, 18.13, 24.63, 9.10, 11.20PTH12010/20/30/50/60 12 12 A, 18 A, 26 A, 6 A, 8 A No 1.2 to 5.5 Yes 14.00, 18.13, 24.63, 9.10, 11.20

1See power.ti.com for a complete product offering. New devices are listed in red.2Suggested resale price in U.S. dollars in quantities of 1,000.

Page 46: UMTS Application Notes

46 Wireless Infrastructure Solutions Guide Texas Instruments 4Q 2003

LOW DROPOUT REGULATORS (LDOs)Output Options Packages

VDO Iq @IO @ IO IO Negative

Device (mA) (mV) (µA) Out Voltage (V) Adj. Features1 CO2 Comments Price3

TPS797xx 10 105 1.2 1.8, 3, 3.3 1.8 5.5 4 PG 0.47 µF C MSP430; lowest Iq 0.32TPS715xx 50 415 3.2 2.5, 3, 3.3, 5 2.5 24 4 0.47 µF C Ultra-low Iq 0.32TPS770xx 50 35 17 1.2, 1.5, 1.8, 2.5, 2.7, 2.8, 3, 3.3, 5 2.7 10 3 /EN 4.7 µF T Low Iq 0.34TPS722xx 50 50 80 1.5, 1.6, 1.8 1.8 5.5 3 EN 0.1 µF C Low noise & low VIN 0.39TPS760xx 50 120 90 3, 3.2, 3.3, 3.8, 5.0 3.2 16 2 EN 2.2 µF T Bipolar, low cost 0.34TPS769xx 100 70 18 1.2, 1.5, 1.8, 2.5, 2.7, 2.8, 3, 3.3, 5 2.7 10 3 /EN 4.7 µF T Low cost 0.29REG101 100 60 400 2.5, 2.8, 2.85, 3, 3.3, 5 2.6 10 1.5 EN, BP No Cap Low noise 0.88TPS791xx 100 38 185 1.8, 3.3, 4.7 2.7 5.5 2 /EN, BP 1 µF C RF low noise, high PSRR 0.38TPS792xx 100 38 185 2.5, 2.8, 3 2.7 5.5 2 EN, BP 1 µF C RF low noise, high PSRR 0.38TPS761xx 100 170 90 3, 3.2, 3.3, 3.8, 5 3.4 16 2 EN 4.7 µF T Bipolar, low cost 0.35TPS763xx 150 180 85 1.6, 1.8, 2.5, 2.7, 2.8, 3, 3.3, 3.8, 5 2.7 10 3 EN 4.7 µF T Low cost 0.29TPS764xx 150 300 85 2.5, 2.7, 2.8, 3, 3.3 2.7 10 3 EN, BP 4.7 µF T TPS763xx + low noise 0.29TPS771xx 150 75 90 1.5, 1.8, 2.7, 2.8, 3.3, 5 2.7 10 2 /EN, SVS 10 µF T Low noise 0.56TPS731xx 150 60 450 1.5, 1.8, 2.5, 3.0, 3.3, 5.0 1.8 5.5 2 EN, BP No Cap Reverse leakage protection 0.45SN105125 150 1 V 150 1.2 — 3 5.25 2 EN, PG 1 µF C Low cost 0.29TPS788xx 150 150 18 2.5, 3.3 2.7 10 3 /EN 4.7 µF T USB inrush control 0.36TPS721xx 150 150 90 1.5, 1.6, 1.8 1.8 5.5 3 EN 0.1 µF C Low noise & low VIN 0.39TL750/1Lxx 150 600 1 mA 5, 10, 12 6 26 4 /EN 10 µF T 60-V load dump 0.45TPS793xx 200 77 180 1.8, 2.5, 2.8, 2.85, 3, 3.3, 4.75 2.7 5.5 2 EN, BP 2.2 µF C RF low noise, high PSRR 0.40TPS794xx 250 145 172 1.8, 2.5, 2.8, 3, 3.3 4 2.7 5.5 3 EN, BP 2.2 µF C RF low noise, high PSRR 0.62TPS732xx 250 100 450 1.5, 1.8, 2.5, 3, 3.3, 5.0 1.8 5.5 2 EN, BP No Cap Reverse leakage protection 0.65TPS773xx 250 125 90 1.5, 1.6, 1.8, 2.7, 2.8, 3.3, 5 2.7 10 2 /EN, SVS 10 µF T Low noise 0.65TPS779xx 250 250 90 1.8, 2.5, 3 2.7 10 2 EN, SVS 10 µF T Low noise 0.65REG102 250 150 400 2.5, 2.8, 2.85, 3, 3.3, 5 2.6 10 1.5 EN, BP No Cap Capacitor free, DMOS 1.00TPS736xx 400 160 450 1.5, 1.8, 2.5, 3.0, 3.3 1.8 5.5 2 EN, BP No Cap Reverse leakage protection 0.80REG113 400 250 400 2.5, 2.85, 3, 3.3, 5 2.6 10 1.5 EN, BP No Cap Capacitor free, DMOS 1.04TPS795xx 500 105 265 1.6, 1.8, 2.5, 3, 3.3 2.7 5.5 3 EN, BP 1 µF C RF low noise, high PSRR 0.95TPS775xx 500 169 87 1.5, 1.6, 1.8, 2.5, 3.3 2.7 10 2 /EN, SVS 10 µF T Fast transient response 0.87TPS776xx 500 169 87 1.5, 1.8, 2.5, 2.8, 3.3 2.7 10 2 /EN, PG 10 µF T Fast transient response 0.83REG103 500 115 500 2.5, 2.7, 3, 3.3, 5 2.6 15 2 EN, PG No Cap Capacitor free, DMOS 2.00TPS777xx 750 260 85 1.5, 1.8, 2.5, 3.3 2.7 10 2 /EN, SVS 10 µF T Fast transient response 0.96TPS725xx 1000 170 75 1.5, 1.6, 1.8, 2.5 1.8 6 2 EN, SVS No Cap Low noise; SVS delay 50 ms 1.04TPS726xx 1000 170 75 1.5, 1.6, 1.8, 2.5 — 1.8 6 2 EN, SVS No Cap Low noise; SVS delay 200 ms 1.04TPS796xx 1000 200 310 1.8, 2.5, 2.8, 3, 3.3 2.7 5.5 2 EN, BP 1 µF C RF low noise, high PSRR 1.04TPS767xx 1000 230 85 1.5, 1.8, 2.5, 2.7, 2.8, 3, 3.3, 5 2.7 10 2 /EN, SVS 10 µF T Fast transient response 1.04TPS768xx 1000 230 80 1.5, 1.8, 2.5, 2.7, 2.8, 3, 3.3, 5 2.7 10 2 /EN, PG 10 µF T Fast transient response 1.00UCCx81-x 1000 500 400 3.3, 5 1.8 9 2.5 EN 2.2 µF T Reverse leakage protection 1.80REG104 1000 230 600 2.5, 2.7, 3, 3.3, 5 2.6 15 2 EN No Cap Capacitor free, DMOS 2.22TLV1112 1000 1200 5 mA 1.2 — 2.7 18 2.5 10 µF T Low cost regulator 0.35TLV1117 1000 1200 5 mA 1.5, 1.8, 2.5, 2.85, 3.3, 5 2.7 18 2.5 10 µF T Low cost regulator 0.32TPS786xx 1500 390 310 1.8, 2.5, 2.8, 3, 3.3 2.7 5.5 3 EN, BP 1 µF C RF low noise, high PSRR 1.28TPS751xx 1500 160 75 1.5, 1.8, 2.5, 3.3 2.7 5.0 2 /EN, PG 47 µF T Fast transient response 1.52TPS752xx 2000 210 75 1.5, 1.8, 2.5, 3.3 2.7 5.0 2 /EN, SVS 47 µF T Fast transient response 1.71TPS754xx 2000 210 75 1.5, 1.8, 2.5, 3.3 2.7 5.0 2 /EN, PG 47 µF T Fast transient response 1.65UC382-x 3000 350 6 mA 1.5, 2.1, 2.5 1.7 7.5 1 100 µF T Fast LDO with reverse leak. 2.57UCC383-x 3000 400 400 3.3, 5 1.8 9 2.5 /EN 22 µF T Reverse leakage protection 2.57TPS758xx 3000 150 110 1.5, 1.8, 2.5, 3.3 2.8 5.5 3 EN 47 µF T Fast transient response 2.57UC385-x 5000 350 8 mA 1.5, 2.1, 2.5 1.7 7.5 1 100 µF T Fast LDO with reverse leak. 3.00TPS756xx 5000 250 110 1.5, 1.8, 2.5, 3.3 2.8 5.5 3 EN 47 µF T Fast transient response 2.83TPS759xx 7500 400 110 1.5, 1.8, 2.5, 3.3 2.8 5.5 3 /EN, PG 47 µF T Fast transient response 3.04

Min

V IN

Max

VIN

Accu

racy

(%)

SC70

SOT2

3

MSO

P

SO8

SOT2

23

PWP

TO26

3

TO22

0

PW DDPA

K

1PG = PowerGood, EN = Active High Enable, /EN = Active Low Enable, SVS = Supply Voltage Supervisor 2C = Ceramic, T = Tantalum, No Cap = Capacitor Free LDO3Suggested resale price in U.S. dollars in quantities of 1,000. New devices are listed in red.

LogicG

eneral Overview

Signal ChainTim

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Power M

anagement

MOSFET DRIVERIO Rise/Fall VCC Prop Dead

No. of Output Output Source/Sink Time Range Delay Input Time Protection InternalDevice Outputs Configuration Type (A) (ns) (V) (ns) Threshold Enable Control Features Regulator Price1

UCC37323 2 Inverting TrueDrive 4.0/4.0 25/25 4 to 15 35 TTL/CMOS No No — No 0.991Suggested resale price in U.S. dollars in quantities of 1,000.

LOADSHARE CONTROLLERSDevice VIN (min) VIN (max) Reference Accuracy (%) Share Bus Pin Count Supply Current (mA) Price1

UCC29002 4 15 — Single Ended 8 2.5 0.891Suggested resale price in U.S. dollars in quantities of 1,000.

Page 47: UMTS Application Notes

4Q 2003 Texas Instruments Wireless Infrastructure Solutions Guide 47

Read more about Wireless Infrastructure solutions at www.ti.com/wisolutionsguide

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PLUG-IN POWER SOLUTIONSInput Bus POUT Isolated VO Range VO

Device1 Voltage (V) Description or IOUT Outputs (V) Adjustable Price2

Isolated Multiple OutputPT4820 48 35-W 48-V Input Triple Low-Voltage Isolated DC/DC Converter 35 W Yes 1.2 to 5.0 Yes 64.83PT4850 48 75-W 48-V Input Triple Low-Voltage Isolated DC/DC Converter 75 W Yes 1.2 to 3.3 Yes 96.64Isolated Single OutputPT4410 48 100-W 30-A 48-V Input Isolated Programmable DC/DC Converter 100 W Yes 1.05 to 5.7 5-bit programmable 70.20

1See power.ti.com for a complete product offering.2Suggested resale price in U.S. dollars in quantities of 1,000.

HOT SWAP CONTROLLERS (EXTERNAL FET)Power Good Average

Target VIN Enable/ or UVLO Automatic PowerDevice Applications Channels (V) Shutdown Reporting Ramp Retry/Latch Limiting Price1

TPS2390 –48-V Telecom 1 –36 to –80 1H UVLO Current Latch No 1.15TPS2391 –48-V Telecom 1 –36 to –80 1H UVLO Current AutoRetry No 1.15

1Suggested resale price in U.S. dollars in quantities of 1,000.

DC/DC CONTROLLERSVO VO Vref Driver Output Adaptive

VIN (max) (min) Tol Current Current Multiple VoltageDevice (V) (V) (V) (%) (A) (A)1 Outputs Positioning Protection2 Comments Price3

Performance Processor Power Supply Controllers (Synchronous Rectification)TPS40000 2.25 to 5.5 4 0.7 1.5 1 15 No No OCP, UVLO 300-kHz low input sync buck, source only 0.99TPS40001 2.25 to 5.5 4 0.7 1.5 1 15 No No OCP, UVLO 300-kHz low input sync buck, source/sink 0.99

except SSTPS40002 2.25 to 5.5 4 0.7 1.5 1 15 No No OCP, UVLO 600-kHz low input sync buck, source only 0.99TPS40003 2.25 to 5.5 4 0.7 1.5 1 15 No No OCP, UVLO 600-kHz low input sync buck, source/sink 0.99

except SSTPS40050 8 to 40 30 0.7 1 1 20 No No OCP, UVLO Wide input range sync buck, source only 1.32TPS40051 8 to 40 30 0.7 1 1 20 No No OCP, UVLO Wide input range sync buck, source/sink 1.32TPS40053 8 to 40 30 0.7 1 1 20 No No OCP, UVLO Wide input range sync buck, source/sink 1.32

except SSTPS40060 10 to 55 40 0.7 1 1 10 No No OCP, UVLO Wide input range sync buck, source only 1.32TPS40061 10 to 55 40 0.7 1 1 10 No No OCP, UVLO Wide input range sync buck, source/sink 1.32

1Current levels of this magnitude and beyond can be supported. New devices are listed in red.2OCP — over-current protection; UVLO — under-voltage lockout3Suggested resale price in U.S. dollars in quantities of 1,000.

DUAL-OUTPUT LDOsOutput Options Features

VDO1 VDO2 Iq @IO1 IO2 @ IO1 @ IO2 IO Voltage Accuracy PWP Min Max Low Min Max

Device (mA) (mA) (mV) (mV) (µA) (V) Adj. (%) Package VO VO /EN PG SVS Seq Noise VIN VIN CO1 Description Price2

TPS707xx 250 150 83 — 95 3.3/2.5, 3.3/1.8, 2 1.2 5 2.7 5.5 10 µF T Dual-output LDO with 1.913.3/1.5, 3.3/1.2 sequencing

TPS708xx 250 150 83 — 95 3.3/2.5, 3.3/1.8, 2 1.2 5 2.7 5.5 10 µF T Dual-output LDO with 1.913.3/1.5, 3.3/1.2 independent enable

TPS701xx 500 250 170 — 95 3.3/2.5, 3.3/1.8, 2 1.2 5 2.7 5.5 10 µF T Dual-output LDO with 2.173.3/1.5, 3.3/1.2 sequencing

TPS702xx 500 250 170 — 95 3.3/2.5, 3.3/1.8, 2 1.2 5 2.7 5.5 10 µF T Dual-output LDO with 2.173.3/1.5, 3.3/1.2 independent enable

TPS767D3xx 1000 1000 230 — 170 3.3/2.5 2 1.2 5 2.7 10 10 µF T Dual-output FAST LDO with 2.173.3/1.8 integrated SVS

TPPM0110 1500 300 1000 2500 1000 3.3/1.8 2 1.8 3.3 4.7 5.3 100 µF T Outputs track within 2 V 1.62TPPM0111 1500 300 1000 2800 1000 3.3/1.5 2 1.5 3.3 4.7 5.3 100 µF T Outputs track within 2 V 1.60TPS703xx 2000 1000 160 — 185 3.3/2.5, 3.3/1.8, 2 1.2 5 2.7 5.5 22 µF T Dual-output LDO with 2.30

3.3/1.5, 3.3/1.2 sequencingTPS704xx 2000 1000 160 — 185 3.3/2.5, 3.3/1.8, 2 1.2 5 2.7 5.5 22 µF T Dual-output LDO with 2.30

3.3/1.5, 3.3/1.2 independent enable1T = Tantalum New devices are listed in red.2Suggested resale price in U.S. dollars in quantities of 1,000.

Page 48: UMTS Application Notes

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Page 49: UMTS Application Notes

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