under the hood of flyback smps designs ppt presentation
TRANSCRIPT
Power Supply Design Seminar
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Topic 1 Presentation:
Under the Hood of Flyback SMPS Designs
Reproduced from2010 Texas Instruments Power Supply Design Seminar
SEM1900, Topic 1TI Literature Number: SLUP254
© 2010, 2011 Texas Instruments Incorporated
SLUP254
Topic 1
Under the Hood of Flyback SMPS DesignsFlyback SMPS Designs
Jean Picard
SLUP254
Agenda
1. Basics of Flyback Topology
2 Impact of Transformer Design on Power Supply2. Impact of Transformer Design on Power Supply Performance
3. Power Supply Current Limiting
4. Summary4. Summary
Texas Instruments—2010 Power Supply Design Seminar 1-2
SLUP254
Transfer of Energy• FET turns ON
– Voltage across primary magnetizing inductance ≅ Vi
E i t d i fl b k
IP• Energy is stored in flyback
transformer: Function of L, D and Ts
– Secondary diode in blocking state +Vi
Io
y g
• FET turns OFF– During commutation: Leakage
energy absorbed by clamp circuit
1:n2
+Vi
Vo
amp
Iout
-+-
IPenergy absorbed by clamp circuit– Stored energy transferred to output
through diode– If DCM operation all the stored
Cla
Vdrain
Iout+P
If DCM operation, all the stored energy is transferred
• Pulsating input and output t
Texas Instruments—2010 Power Supply Design Seminar 1-3
current
SLUP254
Transfer of Energy• FET turns ON
– Voltage across primary magnetizing inductance ≅ Vi
Energy is stored in flybackIP
• Energy is stored in flyback transformer: Function of L, D and Ts
– Secondary diode in blocking state
V
Io
• FET turns OFF– During commutation: Leakage
energy absorbed by clamp circuit
1:n2
+Vi
Vo
mp
I+I
Io
circuit – Stored energy transferred to
output through diode– If DCM operation all the stored
Cla
m
Vdrain
Iout-IP
If DCM operation, all the stored energy is transferred
• Pulsating input and output t
Texas Instruments—2010 Power Supply Design Seminar 1-4
current
SLUP254
Transfer of EnergyO• FET turns ON
– Voltage across primary magnetizing inductance ≅ Vi
Energy is stored in flybackIP
• Energy is stored in flyback transformer: Function of L, D and Ts
– Secondary diode in blocking state
O +V
Io
• FET turns OFF– During commutation: Leakage
energy absorbed by clamp circuitSt d t f d t
1:n2
+Vi
Vo
mp
I+
Io
– Stored energy transferred to output through diode
– If DCM operation, all the stored energy is transferred
Cla
Vdrain
Iout-
energy is transferred
• Pulsating input and output current
Texas Instruments—2010 Power Supply Design Seminar 1-5
SLUP254
Transfer of Energy• FET turns ON
– Voltage across primary magnetizing inductance ≅ Vi
• Energy is stored in flyback transformer: Function of L, D and Ts
– Secondary diode in blocking state 1:n2
+Vi
Vo
• FET turns OFF– During commutation: Leakage energy
absorbed by clamp circuit
Cla
mp
Vdrain
Iout
– Stored energy transferred to output through diode
– If DCM operation, all the stored energ is transferred
drain
energy is transferred
• Pulsating input and output current
Texas Instruments—2010 Power Supply Design Seminar 1-6
SLUP254
CCM versus DCM• Continuous conduction mode (CCM)
T
VContinuous conduction mode (CCM)– Small ripple and rms current– Lower MOSFET conduction and
turn-off loss
PrimaryMOSFET
IPrimaryC
Vdrain
D x Ts(1 – D) x TsVo + Vin2
– Lower core loss– Lower capacitors loss– Can have better “full load” efficiency
S ll EMI d t t filt
IpkIpkminCurrent
m2SSecondaryCurrent
IIo_avg
IP ΔIL
ΔILS– Smaller EMI and output filters
• Discontinuous conduction mode (DCM)
Time (t)
Io_ gS
Vdrain
Ts
V– No diode reverse recovery loss– Lower inductance value
• May result in a smaller transformerBetter “no load” efficiency
drainD × Ts
Vi
Ipk
(1 D) × T
PrimaryMOSFET
PrimaryCurrent
Vo + Vin2
– Better no load efficiency– First-order system
• Inherently stable– No RHPZ problem
IP(1 – D) × TsCurrent
Secondary
IdlePeriod
Texas Instruments—2010 Power Supply Design Seminar 1-7
p– Slope compensation not needed
in CMCTime (t)
Io_avgIo
SecondaryCurrent
SLUP254
+Vi
Right-Half-Plane Zero, CCM Operation
1:n2
+Vi
Vo
lam
p
Iout-
+-IP
• Energy is delivered during 1 – D– Effect of control action during ON
time is delayed until next switch
Cl
Vdrain
out+y
turn OFF
• Initial reaction is in opposite direction of desired correction
1+Vi Io
direction of desired correction
⇒ RHP Zero
Phase decreases with increasing
FET ON
1:n2 Vo
Clam
p
Iout+-
o– Phase decreases with increasing gain
( )2 o1 D V− ×Vdrain
( ) oRPHZ 2
out 2
1 D Vf
2 L D I n×
=π × × ×
FET OFFD M i it h d t l
Texas Instruments—2010 Power Supply Design Seminar 1-8
D ↔ Main switch duty-cycle
SLUP254
RCD Clamp Circuit• During commutation primary to• During commutation primary-to-
secondary, the leakage energy is absorbed by the clamp circuit
R dissipates the leakage
+Vi
Diode orSynchronous
Rectifier VoN1:N2– Rclamp dissipates the leakage energy and some magnetizing energy
– The clamp capacitor ensures a
Rclamp Vclamp+
–Vo
IP
N1:N2
The clamp capacitor ensures a low voltage ripple
– Use short connection with minimum loop area
Vdrain
RS
• Vclamp is maximum at full load and minimum input voltage– Rclamp selected for a maximum
S
V V
Clamp-DiodeForward Recovery Leakage-Inductance
DemagnetizationVclamp
drain voltage in worst case– Tradeoff between efficiency,
peak drain voltage, output
VdrainPrimaryMOSFET
V + Vi clamp V +V n
oi
Texas Instruments—2010 Power Supply Design Seminar 1-9
current limit and cross regulation (see ringing effect)
SLUP254
Agenda
1. Basics of Flyback Topology
2 Impact of Transformer Design on Power2. Impact of Transformer Design on Power Supply Performance
3. Power Supply Current Limiting
4. Summary4. Summary
Texas Instruments—2010 Power Supply Design Seminar 1-10
SLUP254
Transformer’s Leakage Inductance• Transformer’s leakage
Lleak2N1:N2IS
During Primary-to-Secondary Commutation• Transformer s leakage
inductance represented by Lleak2– Primary winding is the closest to
center gap
Clamp+
øVi
IP
+
+–+
+–
–
–Vmag1 Vmag2Lm
VDVleak2
FET
Vout
+
–W1
W2
Secondary Commutation
• When FET turns OFF– Lleak2 opposes to IP decrease and
IS increase
W2
Clamp DiodeForward Recovery
LeakageInductance
Demagnetization
Current Circulates inSecondary Winding(s) Vi + Vclamp
Leakage InductanceResonates with Drain
Capacitance
– Magnetizing inductance works to maintain magnetizing current
• Voltage spike on FET during
Vi + Vclamp
VclampVFET
Cl C it V lt
y g( )
VFET ClampCapacitor
commutation
• Rate of rise of current is influenced by leakage inductance
0 V
Vmag2 – VD – Vout
Vmag2
Vleak2
Clamp Capacitor Voltage Voltage
Reduction in Magnetizing CurrentDue to Faster Commutationy g
• Commutation primary-to-secondary is not instantaneous and depends on Vclamp
IP
IS
IP
IS
Due to Faster Commutation
Texas Instruments—2010 Power Supply Design Seminar 1-11
p clamp– Loss of volt-seconds Lost Volt-Seconds
Low Clamp Voltage High Clamp Voltage
Dtr Dtr
SLUP254
Effects of Leakage Inductance
• Clamp circuits and snubbers needed for primary FET and secondary rectifier(s)
• Lower power-supply efficiency
• Impact on gate-drive strategy if synchronous rectifier is p g gy yused
• Higher duty cycle and magnetizing current than expectedg y y g g p
• Higher H-field radiated emission
Hi h i t l ti• High impact on cross-regulation
Texas Instruments—2010 Power Supply Design Seminar 1-12
SLUP254
How Leakage Can Be Minimized• Leakage inductance is a function of winding geometry number of turns• Leakage inductance is a function of winding geometry, number of turns
and separation between primary and secondary– Minimize the separation between the primary and main secondary
winding(s)winding(s) – Interleave the primary and main secondary– Select a core with a long and narrow window
L L
W2 W1W1 W2W2 W2W1 W1
W1 W1W2 W2W1 W2W2 W1
• Leakage inductance is not lowered with a high permeability coreOption 1 Option 2
Texas Instruments—2010 Power Supply Design Seminar 1-13
• Having the winding tightly coupled to the core will not reduce it
SLUP254
Cross-Regulation – Overview
• Multiple-output flyback topology is popular because of its simplicity and low cost
• If the coupling is perfect, the turns ratio directly defines output voltages
• In the real world, “perfect” coupling is not possible
• This often results in poor cross-regulation
Texas Instruments—2010 Power Supply Design Seminar 1-14
SLUP254
Cross-Regulation Physical Model
• Transformer windings cannot all be equally well coupled to the gap because of physical separation between them
• Magnetic energy stored between the windings represented as leakage inductances
• Model not applicable to any transformer geometry
C b l if i t l i i d if lti l• Can become complex if interleaving is used, or if multiple secondary windings are wound simultaneously (multifilar)
• Not accurate in situation of lightly loaded secondary outputs
• Good tool to understand how the common flyback
Texas Instruments—2010 Power Supply Design Seminar 1-15
transformer geometries work
SLUP254
Cross-Regulation Physical ModellW4
+
+–
+–
lp
lW3
W1
mar
y
W2
W3
W4
N4 V4
N3 V3
++
+–
–
V2
Basic Flyback Circuit Transformer Construction
Clamp
Vi
FET
N1:N2
lW2
WPr
i W W W
+
–
lp Lleak12 Lleak23 Lleak34
+
Basic Flyback Circuit Transformer Construction
LmVmag1Vi
ClampN2:N3 N2:N4
I2I3
IW3IW4
I4i
V2FET
N1:N2
+
–
+
–
+
–
3
V3 V4
• This circuit is only applicable to the transformer windings stackup shown
Each leakage inductance considered is between two consecutive secondaries
Transformer Physical Model
Texas Instruments—2010 Power Supply Design Seminar 1-16
• Each leakage inductance considered is between two consecutive secondaries
• Also called “Ladder model”
SLUP254
Flux Lines during CommutationEach Secondary Winding with Nominal Load
• φm decreases during commutation
• dφ/dt (decreasing) in each secondary winding is limited by its output voltage
φm
d g s ted by ts output o tage– Increasing current
induced in W2 to W4 to maintain φm in the gap
mde Ndtφ= − ×
W1 W3 W4
W2
L
m
• Leakage between W2 and W1– W1’s voltage limited by clamp
• W1 closest to gapDuring Primary-to-Secondary Commutation
Current in All Windings• W1 closest to gap– Vclamp limits dφm/dt in the gap during
commutation
• W2 is next to W1 I
I2lp
W2 is next to W1– W2 limits the dφ/dt seen by W3 and W4– W3 and W4 output voltage lower than
without leakage
I4
I3
Secondary Currents DuringC t ti B d Ph i l M d l
Texas Instruments—2010 Power Supply Design Seminar 1-17
• Current commutates progressively from near to remote secondary windings
Commutation Based on Physical Model
SLUP254
Ringing EffectHi h dV/dt h i it h t ff if i t t i h il l d d• High dV/dt when main switch turns off if main output is heavily loaded
• Transformer leakage inductance and parasitic capacity ⇒ auxiliary secondary voltage tends to “ring” y g g
• If auxiliary output fully loaded ⇒ this ringing is clamped
• If lightly loaded ⇒ voltage overshoot with peak detector effectIf lightly loaded ⇒ voltage overshoot with peak detector effect
• Much higher (sometimes > 2 x nominal value!) auxiliary output voltage at light load – Primary clamp voltage has high impact on result
• Most existing transformer models fail to predict this
• This effect can be mitigated (but not eliminated)– Minimize leakage inductance between secondary windings– Locate the highest power secondary(ies) closest to the primary
Texas Instruments—2010 Power Supply Design Seminar 1-18
• Other solutions include a post-regulator, series resistor or minimum load
SLUP254
Cross-Regulation ExampleAuxiliary Output Lightly Loaded
• W2 (high current output) heavily loaded, W4 lightly loaded
– W4’s output received too much energy during
IW4
I4_pk
I3_pkIW3gy gPhase 1 due to ringing
– W2’s output did not receive enough energy
• At end of commutation (Phase 1):
Effect of V3Capacitors ESR
I2_pkIW2
V3
( )– Σ{reflected secondary currents} magnetizing
current
• V4 went too high IP_pkIP
Vmag1
g– Phase 2: high dφ/dt (decreasing) in W4
• IW4 ⇒ 0 A rapidly– IW2 increases to maintain φm in the gap
Time (t)Phase1
Phase2
Phase3
IP
φm
• After IW4 crosses 0 A, W2’s and W3’s di/dtchange to maintain the downslope of the magnetizing current and flux
φ
W1 W3 W4
W2
Texas Instruments—2010 Power Supply Design Seminar 1-19
mH N IAφ×δ = ×δ = ××μ ∑
Phase 2: No Primary Current
SLUP254
Test Results10 R
Ω I W6
Current ProbeV6VDD
V I 100 1Current Transformer
6.8 µFW6(9T)
W3(9T)
RW3W6
I
CurrentProbe
V4
DD
R6VAW3
W3
W1A
W1B W2
W4
W6
V_Iprim 100:1
+Vi
6.8 µFW4(14T)
I W4 V4
R436 Ω
300 Ω
5 V
W2(4T)W1
(21T)
I W2I PMURS120
0.1 µFR15 k
clampΩ Vclamp
V_Isec1:100Current Transformer
6.8 Ω249 Ω
• Input voltage: 48 V
5 V t t l d 0 A t 5 A
To 5-V Filterand Load
Primary MOSFET
SyncRectifier
To CS InputI5 V
• 5-V output load: 0 A to 5 A
• Auxiliary outputs: V6 (10 V at 0 to 140 mA) and
Rectifier
• Switching frequency: 250 kHz
• Primary magnetizing
Texas Instruments—2010 Power Supply Design Seminar 1-20
( )V4 (18 V at 0 to 200 mA)
Primary magnetizing inductance: 70 µH
SLUP254
Cross-Regulation Test Results with Main Output Fully Loadedp y
2
IW6(0.5 A/div)
2
IW6 (0.5 A/div)
4
2
IW4 (1 A/div)4
2
IW4 (1 A/div)
IW2(2.94 A/div)
IW2(2.94 A/div)
V6 at 1 6 W V4 at 2 5 W
1
Time (0.5 µs/div)
1
Time (0.5 µs/div)
V6 at 0 5 W V4 at 3 6 WV6 at 1.6 W, V4 at 2.5 W, I5 V = 5 A
• The two auxiliary outputs operate in DCM
V6 at 0.5 W, V4 at 3.6 W, I5 V = 5 A
Texas Instruments—2010 Power Supply Design Seminar 1-21
• Notice the change of slope of IW2 when IW4 or IW6 crosses 0 A
SLUP254
Cross-Regulation Test Results: Lightly Loaded Auxiliary with Main Output Fully Loadedy p y
12.4 VV6 (10 V/div)I5 V = 5 A,
V4 at 0.3 W,Vclamp = 70 V
20.6 VI5 V = 5 A,V4 at 0.3 W,Vclamp = 70 V
V6 (10 V/div)
VW6
clamp p
VW6(10 V/di )(10 V/div) (10 V/div)
Time (1 µs/div)Time (1 µs/div)
IW6(200 mA/div)
• At minimum load V6 (10 V nominal) goes up to 20 6 V
V6 at 0.5 W V6 at < 5 mW
( µ )( µ )
Texas Instruments—2010 Power Supply Design Seminar 1-22
• At minimum load, V6 (10 V nominal) goes up to 20.6 V
SLUP254
Cross-Regulation Test Results with Main Output Fully Loaded : Impact of Clamp Voltage
26 V14.4 VV6 (10 V/div)I5 V = 5 A,
V4 at 0.3 W,Vclamp = 83 V
V6 (10 V/div)I5 V = 5 A,V4 at 0.3 W,
V l = 83 V
VW6(10 V/di )
VW6(10 V/div)
Vclamp = 83 V
(10 V/div)
IW6
(10 V/div)
Time (1 µs/div)Time (1 µs/div)
IW6(200 mA/div)
• RCD resistor has been increased for higher Vclamp: 70 V ⇒ 83 V
V6 at 0.5 W V6 at < 5 mW
Texas Instruments—2010 Power Supply Design Seminar 1-23
⇒V6 increased significantly in both cases
SLUP254
Overload Test at Auxiliary Output: Impact of Leakagep g
• There was no hiccup I5 V = 0 A,There was no hiccup mode even at more than 3 A!
Th l d d i di
4
3
IW4 (1 A/div)5 VV4 at 2.5 W,R6 = 1 Ω
• The overloaded winding is unable to take all the energy because of leakage W3 having in
3VAW3 (20 V/div)
IW6 (2 A/div) 6.2-A Peakleakage, W3 having in fact a better coupling to primary than W6
Enough energy
2
IW6 (2 A/div)
– Enough energy delivered by W3 to VDDto maintain switching
Time (0.5 µs/div)
Texas Instruments—2010 Power Supply Design Seminar 1-24
SLUP254
Benefits of Good Cross-Regulation
• Good control of auxiliary outputs in spite of load variations
Better control of gate drive voltage amplitude less gate• Better control of gate drive voltage amplitude, less gate drive losses
• Lower rms current in output capacitors, lower dissipation
• May allow the controller to reach hiccup mode more easilyMay allow the controller to reach hiccup mode more easily when the main output is short-circuited for better protection– Not necessarily true if the short-circuit is applied to an auxiliary
output!
Texas Instruments—2010 Power Supply Design Seminar 1-25
SLUP254
How Cross-Regulation can be Improved• The high current winding must have the best coupling to primary
• Minimize leakage between all secondary windings
• Optimize, not minimize, the leakage inductance of auxiliary windings to primaryp , , g y g p y
• Use winding placement to control leakage inductance– Winding stackup– Spread each winding over the full width of the bobbin for better coupling
Prim
ary
A
Prim
ary
A
Prim
ary
A
Prim
ary
B
Prim
ary
B
Prim
ary
B
W2A
W2A
W2A
W2B
W2B
W2BW3
W3
W3or Better
than
If W3 is lightlyloaded and W2
is the high-current main
• Operate main output in CCM
• Try to avoid operating the auxiliary outputs in DCM. In some cases, consider using resistance in series with the diode
output.
using resistance in series with the diode
• Consider winding more than one auxiliary secondary simultaneously (multifilar)
• Lower clamp voltage may help
Texas Instruments—2010 Power Supply Design Seminar 1-26
– Trade-off between cross regulation, efficiency, peak drain voltage and current limit– Some other types of clamp circuits may provide better results than the RCD clamp
SLUP254
Impact of Transformer Design on Flyback EfficiencyTh f ll i id li b d d i t f• The following guidelines can be used during transformer design to optimize the converter efficiency– Minimize leakage inductance from primary
to main (high current) secondary
300
275
250
300
d (A
)2
d (A
)2
Secondary RMSto main (high-current) secondary– Minimize transformer high frequency
conduction loss• Multifilar or Litz wires when necessary
225
200
175
150
125
200
MS
Cur
rent
Squ
ared
S C
urre
nt S
quar
ed
Secondary RMSCurrent Squared
at 48 V
Good Duty-CycleTrade-Off with
48-V Inputy• Interleaving• Select core shape for minimum number of layers
– Optimize the transformer turns ratio for
125
100
75
50
25
100
20x
Prim
ary
RM
Sec
onda
ry R
MS
20 x Primary RMSCurrent Squared at 48 V
p
best efficiency– Select CCM operation
0 00 20 80 10040 60
Duty Cycle (%)
• Other factors also have an indirect impact on efficiency• Other factors also have an indirect impact on efficiency– Cross-regulation
• VDD rail used for gate drive• Output capacitors rms current
Texas Instruments—2010 Power Supply Design Seminar 1-27
– Impact of fringing flux from gap• Worse with planar transformers
Flyback and EMI• Flyback ⇒ IP and IS pulsate ICMFlyback ⇒ IP and IS pulsate
– Use low Z caps, minimize loop areas – Output filter often required
• Interwinding capacitance ⇒ CM CE–+
Vi VoutIDM
ICM2
P S
N1:N2
IP IS
• Interwinding capacitance ⇒ CM CE
• Transformer and diode configuration impact effective capacitance
Less if facing indings at same AC
++––
Clamp VDDM
ICM2
FETOutput to
Chassis CM– Less if facing windings at same AC potential
– Diode versus synchronous rectifier– Flyback ≠ Forward
+Vi
Chassis CM
econ
dary
ndar
yB
ndar
yA
y
mar
yC
mar
yB
mar
yA
• Better to start with end connected to primary MOSFET– Shields Vdrain E-field
R d i t i di it ff t CE
Oth
erS
Seco
n
Seco
n
Prim
Prim
Prim– Reduces interwinding capacity effect on CE
• Minimize leakage for low H-field RE
• Interleaving reduces H-field RE but may increase ff ti P S i t i di it
Texas Instruments—2010 Power Supply Design Seminar 1-28
FET
VD +
–Vout
effective P-S interwinding capacitance
• Center-gap transformer
SLUP254
Flyback and EMI• Flyback ⇒ IP and IS pulsate ICMFlyback ⇒ IP and IS pulsate
– Use low Z caps, minimize loop areas – Output filter often required
• Interwinding capacitance ⇒ CM CE–+
Vi VoutIDM
ICM2
P S
N1:N2
IP IS
• Interwinding capacitance ⇒ CM CE
• Transformer and diode configuration impact effective capacitance
Less if facing indings at same AC
++––
Clamp VDDM
ICM2
FETOutput to
Chassis CM– Less if facing windings at same AC potential
– Diode versus synchronous rectifier– Flyback ≠ Forward
+Vi
Chassis CM
econ
dary
ndar
yB
ndar
yA
y
mar
yC
mar
yB
mar
yA
• Better to start with end connected to primary MOSFET– Shields Vdrain E-field
R d i t i di it ff t CE
Oth
erS
Seco
n
Seco
n
Prim
Prim
Prim– Reduces interwinding capacity effect on CE
• Minimize leakage for low H-field RE
• Interleaving reduces H-field RE but may increase ff ti P S i t i di it
Texas Instruments—2010 Power Supply Design Seminar 1-28
FET
VD +
–Vout
effective P-S interwinding capacitance
• Center-gap transformer
SLUP254
Agenda
1. Basics of Flyback Topology
2 Impact of Transformer Design on Power Supply2. Impact of Transformer Design on Power Supply Performance
3. Power Supply Current Limiting
4. Summary4. Summary
Texas Instruments—2010 Power Supply Design Seminar 1-29
SLUP254
Power Supply Current Limiting – Overview
• Current-limiting characteristic of power supply defines:– Output power beyond which output voltage falls out
of regulation. Corresponds to the “output load-current li it” (I )limit” (Iout_LIM)
– Output current in overload situations• including short-circuitsincluding short circuits
• Current-limiting characteristic is influenced by parasiticsparasitics– Turn-off delays, leakage inductance,…
Texas Instruments—2010 Power Supply Design Seminar 1-30
SLUP254
Understanding Current Limit –Flyback Power Supply with Peak CMC in CCM
Ipk_LIMIA _LIM
PrimaryCurrent
ΔILD x Ts
Clock Ramp
+Vi Io
Iout
Vo
ClampSlope Comp
R
1:n2
Time (t)
m2S
SecondaryCurrent Io_avg(1 – D) x Ts
Power Supply Controller
PWM
COMP(From Error
I_SENSE
VC R s
R
C
RSC
+
–
I i th i k
Just at Current Limit, Output Begins to Fall Out of Regulation
Ipk_LIMPrimaryCurrent D x T
(Amp) VC_LIM Current-
SenseFilter
• Ipk_LIM is the primary peak current limit
• Io avg is the output currentSecondary
CurrentIo_avg
(1 – D) x Ts
D x Ts
o_avg p
• If short-circuit, Io_avg can be much higher than when current limit has just been
Output Short CircuitTime (t)
( )AII I 1 D×
Texas Instruments—2010 Power Supply Design Seminar 1-31
current limit has just been reached
( )Aout o _ avg
2I I 1 D
n= = × −
SLUP254
Current-Limit Model – Basic Representation• Peak CMC in CCM, fixed switching frequency
VCI
ΔIL
m2
m1
I (Average MagnetizingCurrent)
A
IRpk
S=
Gate Control
ΔIL
D × Ts
)
Gate Control
Neglecting DC voltage drops:
( )oL
2VIm
1 D T LΔ= ≈ oVD
V V=
Neglecting DC voltage drops:
Texas Instruments—2010 Power Supply Design Seminar 1-32
( )2S 21 D T n L− × × 2 i on V V× +
SLUP254
Influence of Input DC Voltage on Output Load Current Limit – Impact of Feedforward
imit
(A)
10
9Without FeedforwardClock Ramp
+Vi Io
Iout
Vo
Clamp
Slope Comp
1:n2
FeedforwardRff
ad C
urre
nt L
8
7
Without FeedforwardPower Supply Controller
PWM
COMP
Clock Ramp
I_SENSE
VC R s
R
C
RSC
+
–
Out
put L
oa
6With Feedforward
COMP(From Error
Amp) VC_LIM
20 25 3530 40 45 50 55Input Voltage (V)
5
• With feedforward, output load current limit becomes almost independent of
If Vi ↑ ⇒ (1 – D) ↑ ⇒ Iout_LIM increases
input voltage⇒ Better control during overload, less stress on power circuitry ⇒ Power limit
C t d/ i d ti
Texas Instruments—2010 Power Supply Design Seminar 1-33
⇒ Cost and/or size reduction
• Feedforward also improves line noise rejection
SLUP254
Current Limit Model – With Feedforward
K × Vff i
VC
R × Magnetizing
S
R × mS 2R × IpkS
R × IASR × mS 1
ff i
Gate Control
D × Ts
g gCurrent)
• Kff x Vi is the feedforward contribution
Gate Control
ff i– Subtracting it from Vc is identical to adding it to current feedback
Texas Instruments—2010 Power Supply Design Seminar 1-34
SLUP254
Current Limit Model – Adding Slope Compensation
VCm0 K Vff i×
Slope Compensation (Clock Ramp)
m x0 2(T – T )s dis
R × mS 2 R × m
R × IAS
2
D × T2
s
S 2 R × mS 1
D × Ts
Tdis
R × IL_pkminS
• Slope compensation to avoid subharmonic oscillation at duty-cycle close to or
Gate Control
s
Slope compensation to avoid subharmonic oscillation at duty cycle close to or higher than 50%
• For easier understanding, slope compensation contribution subtracted from Vc.– Equivalent to slope compensation added to current feedback
Texas Instruments—2010 Power Supply Design Seminar 1-35
– Equivalent to slope compensation added to current feedback– In that circuit representation, the slope compensation is capacitively-coupled
SLUP254
Current Limit Model – With all Delays, Slope Compensation and Feedforwardp
• For a more accurate, parasitics must be included in the analysisanalysis
• Parasitic delaysRC filter time delay– RC filter time delay
– Turn off delay, including current comparator and gate drive – FET turn-on delay from onset of slope compensation ramp
• See Topic 1, Appendix A, in the Seminar Manual for detailed equations
Texas Instruments—2010 Power Supply Design Seminar 1-36
SLUP254
Influence of Transformer Leakage on Output Load Current Limitp
• Rate of rise of current is influenced by leakage, commutation primary-to-secondary is not instantaneous
Lleak2
+– +– –Vmag1 VL
VDVleak2 +
Ideal XfmrN1:N2
IS
secondary is not instantaneous⇒ Loss of volt-seconds (also influenced
by the clamp voltage)⇒ Duty-cycle and average magnetizing
Clamp+Vi
IP
+ + –Vmag1 Vmag2Lm
FET
Vout
–
⇒ Duty-cycle and average magnetizing current have to increase to maintain the output voltage
⇒ Higher conduction loss
FET
g⇒ Higher transformer peak current than
expected-> Iout_LIM lower than expected
IP
IS
• Leakage inductance helps however to keep control of the output current in output ( )oVV D V D 1 D D
Lost Volt-SecondsDtr
Texas Instruments—2010 Power Supply Design Seminar 1-37
the output current in output short-circuit situation ( )o
i new clamp tr new tr2
V D V D 1 D Dn
× ≈ × + × − −
SLUP254
Current Limit During Overload – Example with Combined Effects
• In overload: Output current increases ⇒ output voltage decreases
Assuming no hiccup mode25
decreases– Short-circuit: output current
much higher than at onset of current limit 15
20
utC
urre
nt(A
)
Without Leakage
With Leakage
• Parasitic turn off delays may result in an out of control current if volt-seconds
10Out
pubalance is not possible at the transformer– Transformer’s leakage
i d t h l t i t i
00.511.522.533.544.555
Vo1 Vo2Output Voltage (V)Short Circuit
inductance helps to maintain that balance
– If no leakage, the imbalance occurs starting at Vo1
( )o _ shortS del _ OFF tr S
2
i d l OFF l S
VT t D T
nV t V D T
× − − × =
× − × ×
Texas Instruments—2010 Power Supply Design Seminar 1-38
g o1– With leakage, the imbalance
occurs only from Vo2
i del _ OFF clamp tr S V t V D T× × ×
SLUP254
SummaryTh fl b k t f i th k l t f th• The flyback power transformer is the key element of the converter, for optimum efficiency and cross-regulation
Parasitics ha e a strong infl ence on fl back con erter’s• Parasitics have a strong influence on flyback converter’s behavior, particularly under overload or short-circuit conditions
• The primary clamp circuit design is a trade-off between:– Efficiency – Peak drain voltage– Output current limit – Cross-regulationCross regulation
• Simple feedforward technique can be used to optimize the converter and the system, lowering worst-case components
Texas Instruments—2010 Power Supply Design Seminar 1-39
converter and the system, lowering worst case components stress and reducing the overall cost and size
SLUP254
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