Utilization Of The Power Losses Map In The Design Of DC/DC ConvertersSystem-on-Chip and efficient electronic circuit integration techniques
Carlos III University of Madrid, Spain
Electronics Technology Department
5. References of currents and voltages
3
rout ≈ rout ≈ 221
considering the size ratio between M1 and M2.
Error sources in the ratio iout/Iin:
Channel modulation:

Short channel devices → higher error.
Solution? → Increasing rout.
VT variation:
Two devices placed close in layout → maximum VT variation of 10 mV.
Oxide gradients may suppose variations in the µCox product.

Aspect ratio between the devices in layout:
For W and L > 10 µm → error negligible.
Symmetric designs interleaving devices minimize differences in the aspect
ratio.
7
Current mirror with cascode: = 2 + 4 + 442
Current mirror with cascode and higher Vout variation possible:
8
Wilson current mirror: ≈ 3 + 2 1 + 33 + 1133
1 + 22
2 = 2
1 + 22
Higher output swing because we have one
single device at the output stage.
9
The higher the current the less error due to VT.
The bigger the devices the less error due to aspect ratio.
Longer L → less error due to channel modulation.
To minimize the error due to VT → multiple W/L aspect ratios.
Symmetric layout designs.
Higher output swing because we have one
single device at the output stage.
Tips for current mirror design:
11
Vmin = VON = 1.42 – 0.8 = 0.62 V
Aprox. 0.6 V
The lower the current the lower the
required VON
Aprox. 0.26 VVGS = 0.4 V, VT = 0.28V
Vmin = 2*VON = 0.24 V
14
Error current due to
Iref=20 µA
All transistors has the same size, and therefore the same VT and VDS,sat→VGSi=VDS,sat+VT
VG3=VG4=VGS3+VGS1=2VDS,sat+2VT→ VDS2=VG4-VGS4=VDS,sat+VT (VT more than needed!!!)
The minimum Vo to set M4 in sat is: Vo,min=VDS2+VDS,sat=2VDS,sat +VT=1.3V
16
We need a minimum voltage of 1.3V!
17
Iref=10 µA All transistors are equally sized
Negative feedback
19
MOS devices can be used to implement switches
iD = Coxμn W
L VGS − Vth −
Variable RON
|VGS|>>|VDS|
Enhanced version to increase analog dynamic range:
r, = 1
Active resistor: connecting the gate to the drain:
R = 1
22
This voltage strongly depends on
VDD → not a good reference.
How to improve it? → We may use the pn junction of a BJT device:
≈
23
Power-supply independent current reference:
24
Bibliography
Allen, P. E., & Holberg, D. R. (2002). CMOS analog circuit design. New York: Oxford
University Press.
R. Jacob Baker. 2010. CMOS Circuit Design, Layout, and Simulation (3rd. ed.). Wiley-IEEE
Press.
Simulations are performed through software LTSPice, provided courtesy of Analog Devices
and authored by Mike Engelhardt.
Spice models of transistors come from http://cmosedu.com/, website maintained by R. Jacob