Universal RF Communication System Final Report

Submitted: May 08, 2002

Client:

ECPE Senior Design Faculty Advisors:

John Lamont Ralph Patterson

Team May02-06 Members:

Tony Poon - Leader Daniel Fox Usman Tariq John Kenkel Daniel Dobson – Reporter

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Table of Contents Table of Contents............................................................................................................................. i List of Figures ................................................................................................................................. ii List of Tables ................................................................................................................................. iii Executive Summary ........................................................................................................................ 1

Need for Project .......................................................................................................................... 1 Project Description...................................................................................................................... 1 Project Results ............................................................................................................................ 2

Definition of Terms......................................................................................................................... 2 Introduction..................................................................................................................................... 3

General Background ................................................................................................................... 3 Technical Problem ...................................................................................................................... 3 Operating Environment............................................................................................................... 3 Intended Users and Uses............................................................................................................. 4 Assumptions and Limitations ..................................................................................................... 4

Design Requirements ...................................................................................................................... 5 Design Objectives ....................................................................................................................... 5 Functional Requirements ............................................................................................................ 5 Design Constraints ...................................................................................................................... 6 Measurable Milestones ............................................................................................................... 7

End Product Description ................................................................................................................. 7 Approach and Design...................................................................................................................... 8

Technical Approaches................................................................................................................. 8 Technical Design - Hardware ..................................................................................................... 8 Technical Design – Software .................................................................................................... 11 Testing Description................................................................................................................... 13 Risks and Risk Management..................................................................................................... 16 Recommendation for Continued Work..................................................................................... 16

Financial Budget ........................................................................................................................... 17 Personnel Effort Budget................................................................................................................ 18 Project Schedule............................................................................................................................ 20

Evaluation of Project Success................................................................................................... 23 Commercialization........................................................................................................................ 23 Recommendation for Future Work ............................................................................................... 24 Lessons Learned............................................................................................................................ 24 Project Team Information ............................................................................................................. 25 Summary ....................................................................................................................................... 26 References..................................................................................................................................... 27 Appendix A – Hardware Schematics............................................................................................... I Appendix B – PCB Layout Masks..................................................................................................II Appendix C – Software Code for Microcontroller ....................................................................... VI Appendix D – Build of Materials............................................................................................ XXXI Appendix E – MCU I/0 Configuration .................................................................................XXXIII

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List of Figures Figure 1 – RF Module and Wiring Harness.................................................................................... 7 Figure 2 – Hardware Block Diagram.............................................................................................. 8 Figure 3 – Software Flow Diagram .............................................................................................. 11 Figure 4 - Component Level Test Form ....................................................................................... 14 Figure 5 - Integration Test Form................................................................................................... 14 Figure 6 - Functionality Test Form............................................................................................... 15 Figure 7 - Reliability Test Form ................................................................................................... 15 Figure 8 - User Test Form............................................................................................................. 15 Figure 9 – Original Schedule ........................................................................................................ 20 Figure 10 – Revised Schedule....................................................................................................... 21 Figure 11 – Actual Schedule......................................................................................................... 22

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List of Tables Table 1 – Original vs. Revised Estimated Cost ............................................................................ 17 Table 2 – Original Estimated Project Time in Hours ................................................................... 18 Table 3 – Revised Estimated Project Time in Hours.................................................................... 19 Table 4 – Actual Project Time in Hours ....................................................................................... 19

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Executive Summary Need for Project Senior design projects developed in the past have required the use of wireless communication. Due to the limited resources available to non-sponsored groups, commercially available units are too expensive to buy. Additionally, the time required to design and build a wireless system internally would heavily detract from time spent on realizing the group’s overall project. Accordingly, an off-the-shelf and inexpensive wireless system is needed to realistically integrate wireless technology into senior design projects. Project Description The “Universal RF Communication System” is the solution to the problem previously described. The goal of SDMay206 was to design, build, test, and document a wireless system that would: meet the wireless needs of future senior projects, integrate easily into future projects, and cost a fraction of commercially available units. These goals were met through the following strategies: Functionality As the applications this project would be integrated into were not defined prior to project inception, a detailed analysis of common applications in which wireless communication is necessary for senior project implementation was completed. Then a list of the functionality necessary to assure the device will comply with the requirements of the chosen applications was compiled. Finally, the list was narrowed to a set determined by the group to be essential and possible.

Implementation Every effort was made to create a final product that is intuitive in its functionality and implementation. To this end, development documentation was drafted to help the future team fully debug and develop the module.

Cost Due to budget constraints, a large effort was directed towards cutting the cost of this project. These efforts included the following:

• Obtained vendor samples free of charge • Obtained sponsor for PCB fabrication • Found technician willing to populate boards • Sought advice from campus professors

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Project Results The project, while experiencing several roadblocks, has been a success. At the point of this document’s printing the following has been accomplished:

• Detailed project definition drafted • Selection and acquisition of discrete components at minimal cost • Printed circuit board layout, routing, and fabrication completed • Boards populated • Initial revision of software developed • Preliminary usage and functional documentation

The project currently resides in testing. Once this is completed, the design will be ready for a rerun (if needed) and user documentation. Through the successful completion of this project, future senior design groups will have wireless technology at their fingertips. This technology will be available to such groups for no cost and minimal implementation effort. In short, this project will facilitate the successful realization of future senior design efforts.

Definition of Terms ECPE Electrical and computer engineering ESD Electrostatic discharge FM Frequency modulation – protocol for analog transmission over the air FSK Frequency shift keying – protocol for digital transmission over the air ISM Band of frequencies available for industrial, scientific, and medical use JTAG IEEE defined connection standard OOK On-off keying PCB Printed circuit board QFP Quad flat pack – integrated circuit packaging technology RS-232 Serial interface protocol SMA Type of connector commonly used for high frequency data Transceiver Wireless component incorporating both transmit and receive functionality TX/RX Transmit/receive

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Introduction General Background The universal RF communication project is to design a wireless information exchange system for a broad spectrum of applications. Accordingly, the design will consume little power to accommodate applications where power will be supplied through batteries to ensure longevity of operation. The design will be compact in size (in the order of cm^2 ) to accommodate portable applications. The end product will be such that implementation into a system is intuitive and well documented as the goal is to simplify the design process of future projects. Technical Problem The technical problem is to implement the following:

1. Use a microcontroller-based design with minimal supporting components

2. Transmit user information with an RF transceiver through a reliable connection

3. Create a flexible user interface capable of handling multiple data configurations

4. Create a modular design in which power, system, and antenna exist as separate, interchangeable components

5. Develop transmission protocol capable of multi-unit communication and identification

Operating Environment The operating environment of this device depends on the nature of the application and distance between communicating modules. The guidelines are as follows:

1. Capable of indoor and outdoor operation 2. Minimal traffic density in close proximity

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Intended Users and Uses This project primarily serves an academic purpose but may be extended to the following users and uses: Intended users are:

1. Current and future senior design teams 2. Academic researchers 3. ECPE departmental course students (e.g. CPRE 211)

Intended uses include:

1. Handheld device data transport (e.g. PDA, cell phone) 2. Short distance data acquisition (e.g. medical, industrial, wireless voting machines) 3. Computer peripherals (e.g. keyboard, mouse) 4. Voice radio system (e.g. hand-held radios, intercoms)

Assumptions and Limitations Important assumptions are:

1. Users have a general ECPE background. 2. Operating frequency spectrum will have minimal noise. 3. Assembly will be completed by departmental staff free of charge.

Important limitations are:

1. RF channels are limited to unlicensed radio frequencies (915MHz, 2.4GHz)

2. Transmission range: 0 to 100 meters 3. Temperature range: -20 oC to 60 oC 4. Relative humidity: 0% to 90% 5. Low power operation 6. Small size

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Design Requirements Design Objectives The design objectives listed below are guidelines that directed the project.

1. Design a wireless solution for applications needed frequently in senior design projects. The design includes:

• Power supply • Microprocessor • RF components for transmitting and receiving • User interface • Antenna

2. Fabricate a compact and low cost solution that can be easily assembled.

• Low cost, off-the-shelf RF transceiver with suitable functionalities • Low cost, off-the-shelf microcontroller with adequate computing power • Minimal count of passive components

3. The system will support transmission between 902 – 928 MHz. 4. The design will contain a flexible interface capable of multiple modes of user I/O.

5. The link will support a modular design in which power, system, and antenna exist as

separate, interchangeable components. Functional Requirements The functional requirements define the functionality that the end product performs.

1. The design supports multiple operating modes: • Transmit only • Receive only • Bi-directional communication

2. Two transmission schemes are available:

• FM for analog communication • FSK for digital communication and state monitoring

3. The design provides for device identification, recognition, and reception screening. 4. The project incorporates a compact design, low power consumption, and a sleep (power-

saving) mode.

5. The link allows for broadcasting to multiple nodes.

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Design Constraints Examination of the design requirements led to a compilation of constraints that limited the form and function of the design. These constraints are listed below.

1. Parts: Components including the transceiver chip, microcontroller, antenna, and power supply must be interoperable for reliable communication.

2. Time:

Shipping and availability of parts constrained the time period for this project. Care will be taken to ensure parts are acquired in a timely fashion.

3. Operating frequency:

The operation frequency must fall within the allowable RF range for the transceiver chip of 850 MHz to 950 MHz.

4. Operational modes:

At least three modes need to be implemented: • FM for analog • FSK for digital • Sleep mode for low power consumption

5. Resolution frequency:

The output frequency resolution is limited, based on the transceiver chip, to an output frequency of 230 Hz.

6. Programming:

The microcontroller will be programmed in assembly language for the different operating modes.

7. Portability:

The product will fit on a small PCB while being able to contain all the components as modules or as one unit. Also, all components must be portable and lightweight so they can be taken to on-site locations.

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Measurable Milestones The success of this project will be based upon the timely completion of key events the project team sees as fundamental to completing the design. These milestones are listed and discussed below. 1. Project definition:

As this project is to be implemented in currently unknown applications, the project definition must be well defined for successful completion. A stringent analysis of wireless dependent applications will be completed. A list of functionality capable of encompassing the applications discovered will be compiled. A plan for realizing all functionality listed will be drafted. A market analysis of commercially available components will be conducted.

2. Project design:

A project design will be completed including schematics, PCB layout, build-of-material and hardware/software functional diagrams. This milestone is the “path to success”. Ideally, by following the project design a working device will be built.

3. Working prototype:

A functional prototype will be built and operational based on the project design draft. Component, software, and integration testing will be completed.

4. Product completed:

Fully operational product will be released including all supporting documentation. End Product Description The end product will be an inexpensive, off-the-shelf, user-configurable RF link. It will support several modes of operation and allow for different types of input/output in order to adapt to the application’s needs. Development documentation is included to aid in future system debugging and development.

Figure 1 – RF Module and Wiring Harness

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Approach and Design Technical Approaches The approach to this project was to design a system that takes a user input and modulates the input data into appropriate schemes to be transmitted over a high carrier frequency. The design accommodates interfaces for different data types. The approach is as follows:

1. Create functionality list that will encompass the needs of a broad range of applications. 2. Select discrete components that will realize the needed functionality. 5. Design hardware to allow for proper data and control flow. 4. Design software to control data flow.

5. Integrate unit and test prototype functionality. 6. Design and test production unit. 7. Create extensive usage documentation.

Technical Design - Hardware

Figure 2 – Hardware Block Diagram

Hardware/User Interface

Microcontroller

Antenna

Power Supply

Transceiver

Buffers / Line Drivers

JTAG Programming

Interface

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1. Hardware/User Interface: The following interfaces are supported to comply with the application requirements:

• RS-232 • OOK (On-off keying) • Analog

User applications exchange data and control information with the microcontroller through a standardized RS-232 port commonly found on most commercial computers. This interface enables half-duplex wireless communication between the local computer and remote devices equipped with the same RF modules.

On-off keying will incorporate Boolean inputs to change the state of reserved I/O lines on the microcontroller. Once these inputs are detected, internal logic of the microcontroller will determine application specific functions according to software state machines. This exchange is realized through FSK transmission

Analog inputs are allowed to bypass the digital portion of the design, namely the microcontroller, to be directly broadcast through the air by the transceiver. DIP switches on the module are used to set the operating mode, unit identification, and transmission frequency.

2. Transceiver:

The transceiver chip TRF6900 from Texas Instruments (TI) implements the communication link between RF modules based on control information passed by the microcontroller. This transceiver is intended for linear (FM) and digital (FSK) modulated applications in the 868-MHz European and 915-MHz North American ISM bands for wireless communication data transfer. The TRF6900 is in a 48-lead QFP package and is designed as a fully functional multi-channel FM transceiver. The single chip operates down to 2.2 V, and is specifically designed for low power consumption. The synthesizer has typical channel spacing of approximately 230 Hz to accommodate both narrow and wide band applications. Because of the high frequency resolution of the direct digital synthesizer (DDS), the DDS can be used to fine tune the TX/RX frequency and allows the use of inexpensive reference crystals.

3. Microcontroller:

The selected microcontroller MSP430F413 from Texas Instruments is an ultra low-power microcontroller consisting of different sets of functions targeted to various applications. The 64-lead QFP package is low profile and occupies little PCB real estate. The microcontroller is compatible to be battery operated for use in extended-time applications. The digitally controlled oscillator provides wake up from low-power mode to active mode in less than 6µs. The MSP430F413 microcontroller is configured with one built-in 16-bit timer, a comparator, and 48 I/O pins to accommodate various I/O adaptations based on specific user applications.

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The MSP430F413 provides the control and data information required by the TRF6900 transceiver chip to switch between different modes of operation. Control and data information between the two chips will be exchanged serially. Additional flow control capabilities are achieved using several control lines and internal timers.

Program code and patches are downloaded and updated onto the microcontroller via a JTAG port or a microcontroller socket programmer.

4. Antenna:

A low cost, high gain, omni-directional SMA antenna was obtained commercially for use in the RF range of 902 - 928 MHz within the ISM band.

5. Buffer/Line Drivers

Three buffer/line-driving devices from Texas Instruments were used specifically to prevent the microprocessor from sinking or sourcing high currents and from being exposed to ESD. Two SN74ALVCH244PWR 8-bit buffers provide this protection for the general I/O, and one SN75LV4737ADBR RS232 buffer provides this for the RS232 connection. The buffer/line-driver for the RS-232 interface also allows for operation at multiple voltage levels.

6. Power supply:

The power supply consists of power sources in the form of batteries or generic DC adapters and a voltage regulator to limit the voltage to 3.3 V for all components while allowing a broad range of input voltages up to 20 V. The Linear Technology LT1962EMS8-3.3 is a low drop out voltage regulator used to perform this task. Dropout voltage is the input-to-output differential voltage at which the circuit stops regulating against decreases in supply voltage. This point occurs when input voltage approaches the output voltage. Therefore a very low dropout voltage continues operation when the output reaches the input voltage.

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Technical Design – Software

The Texas Instruments MSP430F413 microcontroller runs the software needed to establish communication between the user and the remote unit. The software consists of one main loop to handle receiving from the remote unit and an interrupt handler to process transmit requests from the user.

Figure 3 – Software Flow Diagram All functions are explained in detail below:

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Main Loop

1. Initialize: The “initialize” function prepares the microcontroller and transceiver for operation. For

the microcontroller it configures the clock, initializes ports, defines the unit identification, calculates the desired user settings from the configuration pins, and enables interrupts. For the transceiver it programs all necessary configuration data.

2. Idle: If the user does not have the module configured to accept received transmissions, the

“idle” function will simply execute null instructions until an interrupt occurs. 3. Receive RF:

If the user has chosen to accept received transmissions, this function will continuously monitor the received data from the transceiver. When it determines that valid data is arriving, it will read it in using a fixed baud rate. The baud rate will be controlled by using the watchdog timer to wait for an exact time interval between samples. After the data has been read in, the destination ID tag for the data will be checked against the local unit ID. If they match, then the data was meant for this unit and it will accept the data. The exception to this is when the module is in FM mode. In this mode, the data will not be analyzed digitally in any manner, but will be simply passed to the user across the analog output.

4. Verify Checksum: If the user has chosen to verify received data, then this function will compute the checksum value of the data and compare it to the received checksum. If the values match, the data was received successfully and it will accept the data. If the values do not match it will reject the data and return to the “receive RF” function to wait for data.

5. Acknowledge:

After “verify checksum” has validated the received data the acknowledge function transmits a data packet to the remote unit to inform it that the data was successfully received.

6. Transmit to User:

This function outputs the data to the user over the chosen interface using the I/O ports.

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Send Interrupt Handler

1. Read User Data: This function reads the user data from the selected interface. It is triggered by an

interrupt, which is caused when the user transmits data to the device. 2. Get Checksum: If the checksum is needed for remote verification, this function calculates the checksum

from the data input by the user. 3. Transmit RF: This function transfers data at a fixed baud rate to the transceiver. As with the “receive

RF” function, the watchdog timer is used to wait an exact time between bit transmissions. Again, the exception is if the user has selected FM mode, where the data will be transmitted without any digital modification or interpretation.

4. Wait for Acknowledge: The “wait for acknowledge” function waits until the remote unit transmits a reception

acknowledge. If this is not received after a certain amount of time then “transmit RF” will be called to retransmit the data. If the data is not acknowledged after a certain number of tries the attempt is abandoned.

Testing Description Testing was conducted on various levels to insure correct operation and efficient completion. The testing levels are described below.

1. Testing began on the component level, checking each component in the system. 2. Integration tests were performed once all components are functional.

3. Revision A was fabricated, populated, and tested for operation.

At this point, time was not left to finish tests. The current status, as shown in the following test sheets, is that the power supply is functional and the microcontroller is programmable and mostly functional. The following steps need to be taken in the future

1. Test all current functions, RS232 communication, RF transceiver programming, and RF transmission/reception.

2. Add and test additional code to support all desired functions, including configuration via

onboard switches, transmit only, receive only, OOK interface, and analog transmission 3. Finally, potential users will have a chance to evaluate the design.

The forms that will be used in conducting these tests are shown in the following sections.

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1. Component Level Tests Test Acceptance Criteria Results&Comments Conducted

By Date / Time

1.1 Power Regulator

Regulates to 3 V and provides ample supply current for operation

Pass D.F.

1.2. Passive Components

All passive components meet design specifications

Pass D.F.

1.3 Buffers

Buffers regulate to the specified amperage

Pass D.F.

1.4 Antenna

Antenna transmits required signal

TBD

1.5 Microcontroller

Microcontroller meets input/output specifications

Pass D.F. T.P.

1.6 Microcontroller Code

Microcontroller programmed and responsive

Pass D.F. T.P.

1.7 Transceiver

Transceiver can receive and transmit a signal

TBD

Figure 4 - Component Level Test Form 2. Integration Tests Test Acceptance Criteria Results & Comments Conducted

By Date / Time

2.1 Power Integration

Power is supplied to all components

Pass D.F.

2.2 Microcontroller Integration

Microcontroller is capable of operational modes

TBD

Figure 5 - Integration Test Form

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3. Functionality Tests Test Acceptance Criteria Results & Comments Conducted

By Date / Time

3.1 Analog Functionality

Analog information is sent and received without signal loss

TBD

3.2 Digital Functionality

Digital information is sent and received without signal loss

TBD

Figure 6 - Functionality Test Form 4. Reliability Tests Test Acceptance Criteria Results & Comments Conducted

By Date / Time

4.1 Maximum Data Throughput

Determine maximum reliable data-throughput

TBD

4.2 Signal Transmission Range

Determine signal range for indoor/outdoor activity

TBD

Figure 7 - Reliability Test Form 5. User Tests Test Acceptance Criteria Results & Comments Conducted

By Date / Time

5.1 Signal Connection

User understands input connection details

TBD

5.2 Setup Basics

User understands the basics of each operation and setup

TBD

5.3 Operation Modes

User understands and can switch to different modes

TBD

5.4 User Transmission

User sends and received data

TBD

Figure 8 - User Test Form

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Risks and Risk Management In any endeavor there exist obstructions to success, some visible from the start and some not. Below is a list of problems seen by the team from the outset as risks to project completion.

1. Team member loss: Talent and knowledge are evenly distributed within the group, so a loss of any member will not tremendously affect productivity. However, this will reduce the number of hours planned for product completion. Fortunately, this did not occur.

2. Part availability:

Availability of chosen parts can greatly affect project progress. Problems occurred in manufactures not delivering on promised samples, or giving misleading information about the simplicity of ordering that part.

3. Design problem: Technical problems with implementing the functions could arise. In this instance,

additional help will be sought and alternative solutions created. A small design problem surfaced in the export of the PCB design, causing all ground connections to be open. This was corrected by adding small ground wires.

3. Unknown actual cost:

The actual cost of a unit is extremely volatile. Component prices are subject to change based on amount ordered. Currently, the unit price is being greatly reduced through obtaining part samples, acquiring PCB sponsorship, and assembling the boards internally. Good project management was needed to successfully reduce the cost.

Recommendation for Continued Work Due to setbacks including over a month wait for PCB layout software, it is recommended that the project be extended to another team. The goals for the next team are as follows:

1. Continue testing of prototype currently being developed. 2. Modify hardware and software to incorporate necessary changes

3. Fabricate revision B if testing deems necessary

4. Design and build a metal casing to accomplish the following:

• Protect components from RF induced saturation. • Provide fixed connector attachments to prevent wire flex. • Provide access to LED feedback • Provide device with professional finished appearance.

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5. Draft user documentation to aid users in the following:

• Implementation of device into system • Alleviating improper operation of device • Choosing appropriate power sources • Configuring device to application’s requirements • Demo at least one digital and one analog application

Financial Budget The financial budget shown below compares the revised estimated costs to the original estimated costs. The table shows that the total estimated cost more than doubled. This was due to several factors. First, it became clear that the team would be unable to acquire many component samples. Second, PCB fabrication was much more expensive than originally planned. Finally, the team originally overlooked the cost of shipping. The majority of components were ordered online from companies not in the vicinity of Iowa State University. Thus, all orders had to be mailed to the team. The actual cost of the project was very near that originally estimated although the money spent was not allocated where originally planned. The acquisition of a sponsorship for PCB fabrication was a huge relief. With fabrication taken care of, components were left as the major financial sink. The complex components were readily available as samples at no cost to the team. Ironically, the simple passive components ended up taking the largest cut of the budget. Table 1 – Original vs. Revised Estimated Cost

Original Revised Actual Estimated Cost Estimated Cost Cost

Project Poster $55.00 $43.00 43.00Components $60.00 $273.00 300.00PCB Fabrication $200.00 $350.00 0.00Mechanical / Packaging $20.00 $20.00 0.00Shipping $0.00 $30.00 0.00Batteries $10.00 $10.00 10.00Miscellaneous Printing $10.00 $10.00 17.00Total Cost $355.00 $736.00 370.00

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Personnel Effort Budget The personnel effort budget shows the division of labor by both project area and person-hours. These figures are estimates and reflect the total project time required for each item including meetings, individual work, and group work. The original and revised estimated personnel effort budgets are shown separately due to their complexity. Table 2 – Original Estimated Project Time in Hours Task Name: Dan Fox: Tony Poon: Daniel Dobson: John Kenkel: Usman Tariq: Total:Product Definition 20 20 16 20 18 94Research 8 8 7 10 8 41Pre-Design 11 12 11 14 12 60Design 8 8 9 13 14 52Software Design 5 5 3 3 3 19Procure Parts 2 4 2 2 2 12

Functional Prototyping 37 38 32 36 30 143Revision A 27 28 25 26 25 131Revision B 10 11 8 10 7 46Documentation 8 9 8 8 8 41Final Verification 14 15 12 14 15 70Class Deliverables 14 14 22 14 12 76 Total Per Person: 164 172 155 170 154 815 Team Total: 815

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In the Revised Budget functional prototyping has been removed from the project schedule and that time has been allotted to revision A and software coding. This change was made because it was realized that hand creating a prototype was not feasible. The following table shows these changes. Table 3 – Revised Estimated Project Time in Hours Task Name: Dan Fox: Tony Poon: Daniel Dobson: John Kenkel: Usman Tariq: Total:Product Definition 20 20 16 20 18 94Research 8 8 7 10 8 41Pre-Design 11 12 11 14 12 60Design 8 8 9 13 14 52Software Design 5 5 3 3 3 19Procure Parts 2 4 2 2 2 12Revision A 44 46 52 58 51 221Software Coding 20 20 5 4 4 53Revision B 10 11 8 10 7 46Documentation 8 9 8 8 8 41Final Verification 14 15 12 14 15 70Class Deliverables 14 14 22 14 12 76 Total Per Person: 164 172 155 170 154 815 Team Total: 815 In the final budget note that revision B and final verification has been removed due to time constraints. The time taken from these areas were routed to software design and revision A. This change was made after several setbacks encountered in getting revision A fabricated and populated. Table 4 – Actual Project Time in Hours Task Name: Dan Fox: Tony Poon: Daniel Dobson: John Kenkel: Usman Tariq: Total:Product Definition 20 20 16 20 18 94Research 8 8 7 10 8 41Pre-Design 11 12 11 14 12 60Design 25 8 9 13 14 52Software Design 20 30 3 3 3 27Procure Parts 25 4 8 10 2 34Revision A 121 38 52 58 18 267Software Coding 10 28 5 4 4 73Documentation 10 8 16 18 10 62Class Deliverables 20 25 28 20 12 105 Total Per Person: 270 172 190 190 100 922 Team Total: 922

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Project Schedule The project schedule indicates the separate areas of work and their required time. Each area of work is broken into its specific components to more clearly show the work being completed. Although the original schedule was well created, the actual time to complete the items varied slightly. Also, new information prompted several major changes to the second semester portion of the schedule. Because of major changes involving the removal of prototyping and revision B, the original, revised and final schedules are shown separately for comparison.

Figure 9 – Original Schedule

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The “Competitive Analysis” took slightly longer than expected, but was compensated for by increased work in the “Function and Application Analysis” phase. This resulted in the “Project Defined” milestone slipping by only two days. It was also realized that both “Implementation Block Diagrams” and “Component Selection” could be done in parallel. The “Schematics” phase was moved from “Hardware Design” to “Revision A” to reflect the actual work schedule. Because components had not been finalized, the “Procure Parts” phase was moved to be after the “Project Design Completed” milestone. Realizing that hand-creating a functional prototype was not feasible, the first major schedule change was done to remove the “Functional Prototyping” phase and move up the “Revision A” phase. With this arrangement, it made sense to do the “Software Coding” in parallel with the hardware, so it was moved. This gave extra time for testing, and expanded the “Verification Testing and Debug” phase, as well as the “Detailed Verification and Validation” phase. These changes are all reflected in the revised schedule.

Figure 10 – Revised Schedule

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Shortly before the end of the first semester the team began ordering parts. It was quickly realized that this would be a continuous effort throughout the second semester as evidenced by the final schedule. In fact, part samples have been sought throughout the “Revision A” phase. This phase took much longer than expected due to several setbacks, the largest being the difficulty in acquiring a licensing key to use a layout and routing tool on campus. These problems expanded “Revision A” well over its allotted time frame. To alleviate the time frame constraint, the “Revision B” phase was eliminated. Also, as testing got under way late the testing of revision A was forced to be the final verification. This is accounted for on the final schedule as the elimination of “Final Verification”. To ensure that as much time is spent on getting the core features operating, the “additional functionality” phase under “software” is now pushed beyond product completion.

Figure 11 – Actual Schedule

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Evaluation of Project Success Each of the milestones is evaluated as follows:

1. Project definition: This milestone was fully met. By the end of first semester, the team compiled a list of functions and applications the link should incorporate. This was done by investigating past senior design projects and pinpointing areas where a wireless RF link would have improved the project. Commercially available products were then analyzed based on this list including products from RF Digital, RF Micro Devices, Chipcon, and Lynx. Each product was near $200 for a transmitter and receiver pair and lacked the flexibility required.

2. Project design:

This milestone was fully met. The project design includes complete software and hardware block diagrams, schematics, and board layout files. The parts build of materials details the manufacturer part number, the board layout denotation, and component size. All this information can be found in the appendices of this document.

3. Working prototype:

This milestone is partially met. The required components for an initial working prototype of a transmitter and receiver have all been acquired through samples or purchase orders. Ten four-layer boards have been fabricated through a $350 sponsorship through PCB Express. Jason Boyd in the ECPE department is currently populating the boards with all components. There are over 100 different components required on the printed circuit board and most are surface mount devices. A small problem with missing ground connections had to be corrected with the addition of ground wires. The next step is to finish the software for the microcontroller and conduct component, software, and integrations tests.

3. Product completed:

This milestone is partially met. While an operational transceiver is not finished, all supporting documentation to this point is complete.

Commercialization Because the goal of this product is to be used by other students and faculty in senior design and research products, there is little potential for commercialization of this end product. However, other future design projects using the transceiver link hold the possibility for commercialization. If the transceiver link were commercialized as is, an appropriate price would be $300 for a pair.

1. Cost: The cost to manufacture small quantities, ranging in the dozens of transceivers, would be $100 per transceiver. This could be decreased if less expensive, substitute surface mount components are found, however the cost for populating the boards would still need to be included.

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2. Street Selling Price: Current street selling prices for commercial products are in the order of $200 for a less flexible transmitter and receiver, so $300 for a pair is appropriate.

3. Potential Market:

The potential for market is very little as a standalone unit; however there is potential for a market when used within other senior design projects.

Recommendation for Future Work It is recommended that a second senior design team continue this project. Because very little testing has been conducted on the transceiver, this would be their main priority. Other tasks would include reducing the cost per transceiver by finding alternate components with similar specifications such as finding a different transceiver crystal, developing the code to accommodate all planned functions including analog transmission, redoing the PCB design to accommodate the less-expensive components and to fix the floating ground-layer issue, deciding how to shield the transceiver components for the antenna radiation, and developing add-on modules to be used for various applications such as a walky-talky. Finally, the senior design group will test the final product under different environments and compile a set of criteria for each application. A few examples of this list would be to determine the distance range for a given antenna under various noise levels, the criteria under which analog transmission is better, and the power consumption with each operating mode. Also, the team should prepare a demo of at least one digital and one analog application. Lessons Learned This project has been a learning experience throughout the entire year. Problems and successes in both technical and non-technical areas are listed below.

1. What went well: The documentation for the transceiver chip from TI was superb. This facilitated both the hardware and software designs. The documentation also listed possible manufacturers and a sample build of materials. Some companies, like Texas Instruments, were willing to give samples and delivered them overnight.

2. What did not go well:

Other companies were unwilling to give samples or were hard to contact. Sometimes much time was spent contacting and requesting samples that it would have been more efficient use of time to just buy them. Getting expertise on RF design was difficult. The people with knowledge in this area did not have time for regular meetings and had little time to meet. Therefore, the lack of understanding on how to approach the technical design set the team back. Since there was limited knowledge in the group and no practical experience of layout and routing, this required extra time to layout and fabricate the PCBs. The team was set back a month and a half waiting to get the layout software because sufficient facilities were not available as previously promised.

25

3. Technical knowledge gained: The team gained knowledge in wireless frequencies used and transmission schemes. In order to build the transceiver, learning the terminology for parts, connectors, designs, and assembly was necessary. Each team member had a different specialty that they readily shared with other team members. The overall technical lesson learned was that a full PCB design cycle is complicated and requires much expertise.

4. Non-technical knowledge gained: The main non-technical knowledge gained was that realistic cost analysis is needed in the beginning. A team should not rely on someone else’s estimate cost analysis; team members should be thorough and get actual costs for parts and manufacturing themselves. Splitting up tasks among group members facilitated the work load, and acquiring samples and corporate sponsorship is helpful to reduce overall cost. Teamwork and efficient management is extremely important to be on schedule, but problems arise that are inevitable and delay the project. Also, five minutes of an experts time and advice is worth hours of the team’s time. An expert may point out flaws in a design and suggest alternatives, saving the team valuable time and resources.

Project Team Information Team Members Dan Fox, CprE Daniel Dobson, EE John Kenkel, EE 1122 Hawthorn Ct. 919 6th St. # 21 5322 Hawthorn Ct Ames, IA 50010 Nevada, IA 50201 Ames, IA 50010 (515) 572-7808 (515) 382-5385 (515) 572_8040 foxy@iastate.edu dadobson@iastate.edu jkenkel@iastate.edu Tony Poon, CprE Usman Tariq, EE 4709 Steinbeck St. #14 4317 Lincoln Swing # 21 Ames, IA 50014 Ames, IA 50014 (515) 268-5015 (515) 292-1694 poony@iastate.edu utariq@iastate.edu Faculty Advisors John Lamont Ralph Patterson III 2215 Coover 2215 Coover Ames, IA 50011-3060 Ames, IA 50011-3060 Phone: (515) 294-3600 Phone: (515) 294-2428 Fax: (515) 294-6760 Fax: (515) 294-6760 jwlamont@iastate.edu repiii@iastate.edu

26

Summary The inspiration for this project stems from past senior design teams being unable to acquire a suitable wireless communication system due either to lack of finances to buy a commercial unit or lack of time to design one. The solution proposed in this document solves both problems; bypassing both cost and time. The project is to design and fabricate a well-documented, easily integrated, application agile RF solution from commercially available components. Implementing this proposal will ensure future design teams will not be set back by incorporating wireless technology.

27

References

1. “TRF6900A, Single-Chip RF Transceiver Datasheet.” Texas Instruments Mix Signal Processing Group. May. 2001. Texas Instruments Incorporated. <http://www-s.ti.com/sc/psheets/slas213g/slas213g.pdf>

2. “TRF6900/MSP430 EVK Application Report.” Texas Instruments Wireless

Communication Business Unit. May. 2001. Texas Instruments Incorporated. < http://www-s.ti.com/sc/psheets/swra032/swra032.pdf>

3. “MSP430x11x Mixed Signal Microcontrollers Datasheet.” Texas Instruments Mix Processing Signal Group. April 2000. Texas Instruments Incorporated. < http://www-s.ti.com/sc/psheets/slas196b/slas196b.pdf>

4. “Implementing a Bi-directional, Half-Duplex FSX RF Link.” Texas Instruments Mix

Processing Signal Group. March 2001. Texas Instruments Incorporated. < http://www-s.ti.com/sc/psheets/slaa121/slaa121.pdf>

5. “MSP430x1xx Family User’s Guide” Texas Instruments Mix Processing Signal Group.

Aug 2000. Texas Instruments Incorporated <http://www-s.ti.com/sc/psheets/slau056a/slau056a.pdf>

6. “TRF6900 Evaluation Board User’s Guide” Texas Instruments Mix Processing Signal

Group. May 2001. Texas Instruments Incorporated <http://www-s.ti.com/sc/psheets/swru001c/swru001c.pdf>

7. “MSP430 Family Serial Programming Adapter Manual” Texas Instruments Mix

Processing Signal Group. July 2001. Texas Instruments Incorporated <http://www-s.ti.com/sc/psheets/slau048b/slau048b.pdf>

8. “SN74lV244A Octal Buffers/Drivers with 3-State Output Data Sheet ” Texas Instruments

Mix Processing Signal Group. Jan 2001. Texas Instruments Incorporated <http://www-s.ti.com/sc/psheets/scls383d/scls383d.pdf>

9. “300mA, Low Noise, Micropower LDO Regulators Data Sheet ” Linear Technology

LDO Group. Jan 1999. Linear Technology Corporation <http://www.linear-tech.com/pdf/1962fa.pdf>

10. “Low Voltage Power Supply Circuits Application Notes ” Advance Micro Devices EPD

Group. Aug1995. Advance Micro Devices Corporation <http://www.amd.com/epd/processors/6.32bitproc/x19197/19197.pdf>

11. “Energizer e2 No. X92 Engineering Data” Energizer Alkaline Group – AAA Division.

Aug1998. Energizer Battery Company Incorporated <http://data.energizer.com/datasheets/frames.htm>

I

Appendix A – Hardware Schematics

II

Appendix B – PCB Layout Masks

Silkscreen_Top.grb (Board layer 1) Scale=3.00 Fri Mar 01 14:36:48 2002

Soldermask_Top.grb (Board layer 2) Scale=3.00 Fri Mar 01 14:37:01 2002

III

Layer_1.grb (Board layer 3) Scale=3.00 Fri Mar 01 14:37:17 2002

Layer_2.grb (Board layer 4) Scale=3.00 Fri Mar 01 14:37:32 2002

IV

Layer_3.grb (Board layer 5) Scale=3.00 Mon Mar 25 16:13:57 2002 – With GND fixed

Layer_4.grb (Board layer 6) Scale=3.00 Fri Mar 01 14:37:52 2002

V

Soldermask_Bottom.grb (Board layer 7) Scale=3.00 Fri Mar 01 14:38:08 2002

VI

Appendix C – Software Code for Microcontroller ;**************************************************************************************************************; ; MSP430F1121 Program for the MSP-EVKTRF6900 Revision B1 ; ; This code supports the transmission and reception of 32 data bytes ; and 2 checksum bytes. ; It supports an acknowledge. ; The data transmission rate is 38.4 kbit/s on the RF side ; The data transmission rate at the RS232 port is 19.2 kbit/s ; ; Written by: Peter Spevak ; Texas Instruments Deutschland GmbH ; June 2000 ; Last change: 19.6.2000 ;************************************************************************************************************** #include "TRF6900_413.H" ; include the special settings for MSP-EVKTRF6900 RAM_orig EQU 00200h ; RAM start 256 Bytes FLASH_orig EQU 0E000h ; F413 FLASH start 8kB NAME TRF6900_Demo ;********************************************** Main ********************************************************* ; last change: April 12th 2000 Last print: November 19th 1999 ; ; calls all the subroutines ; is the frame for the whole program ; ; ;************************************************************************************************************** RSEG CODE ; beginning of the code START main MOV #0300h,SP ; initialize system stack pointer DINT ; general Interrupt disable MOV #WDTPW+WDTHOLD,&WDTCTL ; write with password 5A00h, WDT off CALL #initialization ; initialization of the TRF6900 and MSP430 settings loop_main CALL #receive_RF ; receive 10x8bits BIC #TAIE,&TACTL ; disable Timer_A interrupt BIC #CCIE,&CCTL1 ; disable CCR1 interrupt CALL #check_checksum_r ; check the checksum on the receiver side CALL #check_checksum_s ; check the received checksum from receiver MOV #099Ch,wait_r ; init. wait_r for 250µs, to delay the acknowledge, ; run in time of the sender from receive to send mode CALL #wait_x_cycles ; wait 250µs CLR counter ; set counter value to 0 CALL #send_RF ; send acknowledge CALL #rs232_send ; transmits the received data via RS232 Port ;CALL #IIC_initialize_LCD ; initialize the LCD ;CALL #IIC_LCD_display ; IIC-routine for LCD display BIC #CCIFG,&CCTL1 ; reset interrupt flag BIC #TAIFG,&TACTL ; reset interrupt flag BIS #TAIE,&TACTL ; enable interrupt BIS #CCIE,&CCTL1 ; enable interrupt JMP loop_main ; end of the main routine end_main ;**************************************** Initialization ******************************************************* ; last change: June 19th 2000 Last print: November 19th 1999 ; ; affects: clock settings ; initializes the hardware ; clearing oscillator fault flag !!! necessary for MSP430F430 ;**************************************************************************************************************

VII

initialization ;*********************************** Clock Settings ********************************************************* ; 1. LFXT1CLK-signal is driven by the external 2.4576Mhz crystal ; 2. ACLK is 1/8*LFXT1CLK ; 3. MCLK directly coupled to LFXT1CLK (used only for the CPU) ; 4. SMCLK directly coupled to LFXT1CLK (used for Timer_A during code reception) ;************************************************************************************************************** MOV.B #clock_new_1,&FLL_CTL1 ; set the divider for ACLK to 8 high frequency ; Oscillator selected oscillator on BIS #0x0040,SR ; set FLL to off MOV #0FFFh,wait_r ; for programming purpose MSP430P112 and oscillator start up CALL #wait_x_cycles ; wait routine, waits 3+x*13 cycles initialize_port1 MOV.B #rts+txd+0x0010+0x0040,&P1OUT ; set TXD_MSP(P1.3), TXD_MSP by default high ; reset CTS(P1.0), RXD(P1.1), RTS(P1.2) MOV.B #rts+txd+0x0010+0x0040+0x0020,&P1DIR ; switch RTS(P1.2), TXD(P1.3), P(1.4), P(1.5) and (P1.6) to output dir. MOV.B #0x0020,&P1SEL ; select the module function for ACLK P1.5 (TA1) initialize_port2 MOV.B #0x0004+0x0010+0x00+greenLED+yellowLED,&P2OUT ; set P2.2, P2.4, greenLed, and yellowLed MOV.B #0x0004+0x0010+0x00+greenLED+yellowLED,&P2DIR ; switch P2.2, P2.4, greenLed, and yellowLed to output initialize_port3 MOV.B 0x0000, &P3OUT ; reset mode(0..4) and channel(0..2) on Port3 (all input) MOV.B 0x0000, &P3DIR ; switch all pins on Port3 to input initialize_port4 MOV.B 0x0000, &P4OUT ; reset channel(3..4) and UID(0..5) on Port4 (all input) MOV.B 0x0000, &P5DIR ; switch all pins on Port4 to input initialize_port5 MOV.B #0x00FF, &P5OUT ; set stdb_rs232(P5.0), stdbGB(P5.1), data(P5.2), clk(P5.3), strobe(P5.4), ; mode(P5.5), stdb_trf6900(P5.6), and tx(P5.7) MOV.B #0x00FF, &P5DIR ; switch stdb_rs232(P5.0), stdbGB(P5.1), data(P5.2), clk(P5.3), strobe(P5.4), ; mode(P5.5), stdb_trf6900(P5.6), and tx(P5.7) to output initialize_port6 MOV.B #0x0002+0x0008+0x0020+0x0080, &P6OUT ; set (P6.1), (P6.3), (P6.5), and (P6.7) MOV.B #0x0002+0x0008+0x0020+0x0080, &P6DIR ; switch (P6.1), (P6.3), (P6.5), and (P6.7) to output initialize_receive_status CLR &data_rx_state ; reset receive status initialize_Clock MOV.B #clock_new_2,&FLL_CTL0 ; DCO+ = 1 LFXT1CLK source for SMCLK ; LFXT1CLK source for MCLK oscillator_flag BIC.B #02h,&IFG1 ; reset the oscillator fault flag MOV #0Fh,wait_r ; wait 3 + Fx13 cycles CALL #wait_x_cycles ; call the wait routine BIT.B #02h,&IFG1 ; test the oscillator fault flag JNZ oscillator_flag BIC.B #02h,&IFG1 ; clear oscillator fault flag ;------------------------------------------------------------------------------------------------------------------------------- ; programming the 4 words to TRF6900 CALL #program_DDS0_receive_learn CALL #program_DDS1_send

VIII

CALL #program_send_FSK CALL #program_receive_FSK_learn initialize_CCR1_interrupt MOV #CCIE+CAP+CMNEG,&CCTL1 ; interrupt enable, capture mode, neg. edge ; for RS232 reception end_intialization RET ;********************************* Programming the TRF6900 ******************************************** ;******************************* program_DDS0_receive_learn ******************************************* ; last change: September 20th 1999 ; ; purpose: programs the DDS_0 for FSK Reception in learn mode (see further settings below) ; (Mode 0, A-word) ; ;************************************************************************************************************** program_DDS0_receive_learn MOV #023h,word_h MOV #0BE00h,word_l ; frequency for Mode 0, receive FSK in learn ; mode, DDS_0 settings for 915.00MHz, ; 25.6 MHz system crystal, 10.7MHz IF CALL #program_TRF6900 end_program_DDS0_receive_learn RET ;******************************* program_DDS1_send ***************************************************** ; last change: September 20th 1999 ; ; purpose: programs the DDS_1 for Transmission (see further settings below) ; (Mode 1, B-word) ; ;************************************************************************************************************** program_DDS1_send MOV #023h,word_h MOV #0BE99h,word_l ; frequency for Mode 1, send DDS_1 settings for 915.06 MHz, ; 25.6 MHz system crystal, 10.7MHz IF CALL #program_TRF6900 end_program_DDS1_send RET ;******************************* program_send_FSK ****************************************************** ; last change: September 20th 1999 ; ; purpose: programs the module Mode 1 for FSK transmission (see further settings below) ; (Enable register for PLL, Data Slicer and Mode 1 settings, C-word) ; ;************************************************************************************************************** program_send_FSK MOV #0BCh,word_h MOV #09E00h,word_l ; Module Mode 1, send ; 1_LNAM [bit 0..1] 00b disabled Low noise amplifier operation mode ; 1_MIX [bit 2] 0b disabled Enable Mixer ; 1_IF [bit 3] 0b disabled Enable 1st IF Amplifier ; 1_DEM [bit 4] 0b disabled Enable Limiter/Demodulator ; 1_RSSI [bit 5] 0b disabled Enable Limiter/RSSI

IX

; 1_DSW [bit 6] 0b conn. to Demod. Data Switch (Demodulator or RSSI) ; 1_LPF [bit 7] 0b disabled Enable LPF Amplifier ; 1_SLC [bit 8] 0b disabled Enable Data Slicer ; 1_PA [bit 9..10] 11b 0dB att. Power Amplifier gain value in TX mode (see also MS bit) ; 1_VCO [bit 11] 1b enabled Enable VCO ; 1_PLL [bit 12] 1b enabled Enable PLL (DDS System, RF divider, Phase Comparator and Chargepump) ; [bit 13..14] 00b not used ; SLCTL [bit 15] 1b learn mode Slicer mode select bit ; MS [bit 16] 0b FSK modulation mode select ; NPLL [bit 17] 0b 256 RF divider ratio for PLL ; APLL [bit 18..20] 111b 140 acceleration factor for the charge pump CALL #program_TRF6900 end_program_send_FSK RET ;******************************* program_receive_FSK_learn ********************************************* ; last change: September 20th 1999 ; ; purpose: programs the module Mode 0 for FSK reception in learn mode (see further settings ; below) ; (modulation and mode 0 settings, D-word) ; ;************************************************************************************************************** program_receive_FSK_learn MOV #0C7h,word_h MOV #0199Fh,word_l ; Modulation, Module Mode 0, receive ; 0_LNAM [bit 0..1] 11b normal Low noise amplifier operation mode ; operation ; 0_MIX [bit 2] 1b enabled Enable Mixer ; 0_IF [bit 3] 1b enabled Enable 1st IF Amplifier ; 0_DEM [bit 4] 1b enabled Enable Limiter/Demodulator ; 0_RSSI [bit 5] 0b disabled Enable Limiter/RSSI ; 0_DSW [bit 6] 0b con. to Dem. LPF Amplifier input routed to Demodulator ; (FSK) or to RSSI (OOK) ; 0_LPF [bit 7] 1b enabled Enable LPF Amplifier ; 0_SLC [bit 8] 1b enabled Enable Data Slicer ; 0_PA [bit 9..10] 00b disabled Power Amplifier gain value in TX mode (see also MS bit) ; 0_VCO [bit 11] 1b enabled Enable VCO ; 0_PLL [bit 12] 1b enabled Enable PLL (DDS System, RF divider, Phase comparator and Chargepump) ; MR [bit 13..20] 0011 1000b FSK frequency deviation register (corresponds with 60kHz modulation) CALL #program_TRF6900 end_program_receive_FSK_learn RET ;****************************** program_receive_FSK_hold ********************************************** ; last change: October 7th 1999 ; ; purpose: programs the module Mode 1 for FSK reception in hold mode (see further settings ; below) ; (enable register for PLL, Data Slicer and Mode 1 settings, C-word) ; ;************************************************************************************************************** program_receive_FSK_hold MOV #0BCh,word_h MOV #01E00h,word_l ; Modulation, Module Mode 1, receive

X

; 1_LNAM [bit 0..1] 00b disabled Low noise amplifier operation mode ; 1_MIX [bit 2] 0b disabled Enable Mixer ; 1_IF [bit 3] 0b disabled Enable 1st IF Amplifier ; 1_DEM [bit 4] 0b disabled Enable Limiter/Demodulator ; 1_RSSI [bit 5] 0b disabled Enable Limiter/RSSI ; 1_DSW [bit 6] 0b conn. to Demod. Data Switch (Demodulator or RSSI) ; 1_LPF [bit 7] 0b disabled Enable LPF Amplifier ; 1_SLC [bit 8] 0b disabled Enable Data Slicer ; 1_PA [bit 9..10] 11b 0dB att. Power Amplifier gain value in TX mode (see also MS bit) ; 1_VCO [bit 11] 1b enabled Enable VCO ; 1_PLL [bit 12] 1b enabled Enable PLL ( DDS System, RF divider, Phase Comparator and Chargepump) ; [bit 13..14] 00b not used ; SLCTL [bit 15] 0b hold mode Slicer mode select bit ; MS [bit 16] 0b FSK modulation mode select ; NPLL [bit 17] 0b 256 RF divider ratio for PLL ; APLL [bit 18..20] 111b 140 acceleration factor for the charge pump CALL #program_TRF6900 end_program_receive_FSK_hold RET ;****************************** program_TRF6900 ********************************************************* ; last change: January 26th 2000 ; ; purpose: programs a word to A, B, C or D word register of the TRF6900 ; gets the settings from the calling routine in R6 and R7 ; suppresses the strobe pulse in receive_RF routine, to support shorter training ; sequence ; ;************************************************************************************************************** program_TRF6900 init_high_byte DINT BIC.B #strobe,&P5OUT ; reset Strobe port BIS.B #strobe,&P5DIR ; switch Strobe to output direction MOV #02h,counter ; initialize the counter for high and low byte MOV #08h,bits_r ; initialize bitcounter MOV word_h,word_trf ; push the high byte to the programming buffer SWPB word_trf ; push the low byte to the high byte, only the ; data in the low byte is relevant JMP program_word init_low_byte MOV #010h,bits_r ; initialize bitcounter MOV word_l,word_trf ; push the low byte to the programming buffer program_word RLC word_trf ; push the msb of the programming buffer to carry JNC program_low program_high BIS.B #data,&P5OUT ; set data(P5.2) program_clock BIS.B #clk,&P5OUT ; generate a pulse on the clock line (P5.3) BIC.B #clk,&P5OUT program_next_bit DEC bits_r ; decrement bit counter JNZ program_word ; have already all bits been sent? DEC counter ; decrement counter for low byte recognition JNZ init_low_byte ; low byte is to be programmed generate_strobe

XI

BIC.B #data,&P5OUT ; reset data (P5.2) BIT #08h,&data_rx_state ; shall the strobe pulse be suppressed? JNZ end_program_TRF6900 ; yes suppress it BIS.B #strobe,&P5OUT ; set strobe(P5.4) BIC.B #strobe,&P5OUT ; clear strobe(P5.4) BIC.B #strobe,&P5DIR ; set strobe(P5.4) to input direction end_program_TRF6900 EINT RET ; back to calling routine program_low BIC.B #data,&P5OUT ; clear data(P5.2) JMP program_clock ;*************************************** send_RF *********************************************************** ; last change: April 3rd 2000 ; purpose: sends the received 32 bytes package from RS232 + 2 bytes checksumvia RF as ; NRZ code, features a shorter training sequence ; counter value comes from the calling routine ; ;************************************************************************************************************** send_RF send_RF_acknowledge? BIT #020h,&data_rx_state ; has an acknowledge to be send? JNZ send_RF_init data_to_transmit? BIT #04h,&data_rx_state ; is there any data to send via TRF6900? JZ end_send_RF ; no nothing to send send_RF_init DINT ; CALL #program_DDS1_send ; program the DDS_1 register for sending ; CALL #program_send_FSK ; program the mode 1 register for FSK sending ; obsolete, only necessary if routine used as stand alone BIS.B #stdb_rs232,&P5OUT ; RS232 driver in standby mode (P5.0) BIC.B #rxd,&P1IE ; disable P1.2 Interrupt BIS.B #stdb_trf6900,&P5OUT ; TRF6900 active, STANDBY(P5.6) is high BIS.B #mode,&P5OUT ; Mode 1 is set -> Send mode (P5.5) BIC.B #tx,&P5OUT ; TXDATA(P5.7) is reset CALL #wait_lockdet ; wait for the lockdetect signal MOV #WDTPW+WDTHOLD,&WDTCTL ; Password, Watchdog Timer hold MOV 0200h(counter),data_r ; push data to the send register MOV #WDTPW+WDTTMSEL+WDTCNTCL+03h,&WDTCTL ; Reset, Timer Mode, Password, every 26,04µsec BIS.B #01h,&IE1 ; enable Watchdog Timer interrupt EINT send_RF_training_sequence ; the entire length ca. 1ms, 38 pulses MOV #026h,tr_counter ; 1ms, 38 pulses send_RF_toggle BIS #CPUOFF+GIE,SR ; CPU off ;---------------------------------- Start of the trainings sequence ---------------------------------------------------- XOR.B #tx,&P5OUT ; toggle TXDATA(P5.7) DEC tr_counter ; decrement counter for the training sequence JNZ send_RF_toggle ; length of the loop exactly 26,04µsec send_RF_long_bit BIS #CPUOFF+GIE,SR ; CPU off

XII

;---------------------------------------- Start of the start bit ------------------------------------------------------------- BIS.B #tx,&P5OUT ; start of the long start-bit 78,12µsec (end by the transmission of the 1st data bit) BIS #CPUOFF+GIE,SR ; CPU off BIC #04h,&data_rx_state ; the RS232 buffer is ready for reception BIS #CPUOFF+GIE,SR ; CPU off BIS #CPUOFF+GIE,SR ; CPU off ;-------------------------------------- End of the start bit ---------------------------------------------------------------- BIC.B #tx,&P5OUT ; reset TXDATA(P5.7) BIS #CPUOFF+GIE,SR ; CPU off send_RF_data MOV #010h,bits_r ; init bitcounter, transmit first 16 bits send_RF_bit_test RLC data_r ; push the next data bit to carry JC send_RF_high send_RF_low BIS #CPUOFF+GIE,SR ; CPU off ;---------------------------------------- Start of the Databit -------------------------------------------------------------- BIC.B #tx,&P5OUT ; reset TXDATA(P5.7) send_RF_next_word? DEC bits_r ; decrement bit counter JNZ send_RF_bit_test DECD counter ; decrement word counter JZ send_RF_LED3_on ; all data has been transmitted JN send_RF_reset_ackn ; acknowledge has been transmitted MOV 0200h(counter),data_r ; get the next data word JMP send_RF_data ; send next word send_RF_high BIS #CPUOFF+GIE,SR ; CPU off ;---------------------------------------- Start of the Data Bit ------------------------------------------------------------- BIS.B #tx,&P5OUT ; set TXDATA(P5.7) JMP send_RF_next_word? send_RF_reset_ackn BIC #020h,&data_rx_state ; reset acknowledge state send_RF_LED3_on BIS #CPUOFF+GIE,SR ; CPU off BIS.B #greenLED,&P2OUT ; greenLED on (RF LED) end_send_RF MOV #WDTPW+WDTHOLD,&WDTCTL ; stop Watchdog Timer BIC.B #stdb_rs232,&P5OUT ; RS232 driver go active BIC.B #tx,&P5OUT BIC.B #stdb_trf6900,&P5OUT ; clear STDBY(P5.6), TRF6900 standby mode RET ;************************************** receive_RF ********************************************************* ; last change: April 3rd 2000 ; ; main routine for code reception via RF ; ; purpose: receives the 32 bytes data package + 2 bytes checksum and saves it to memory ; the reception is also supported by several interrupt routines

XIII

; checksum checking implemented (for Flash reprogramming) ; ;************************************************************************************************************** receive_RF BIT #02h,&data_rx_state ; is the reception buffer full? JNZ end_receive_RF ; yes the data has to be send to desktop first CALL #program_send_FSK ; program the C-word for reception in learn mode MOV #CCIE+CAP+CMNEG,&CCTL1 ; interrupt enable, capture mode, neg. edge CLR data_r ; reset data_r CLR wake_up_counter ; reset wake_up_counter CLR RSTAT ; reset receive status register, RSTAT = 0, ; detecting the Trainingssequence BIC.B #mode,&P5OUT ; receive FSK in learn mode BIS.B #01h,&IE1 ; enable Watchdog Timer interrupt BIS.B #stdb_trf6900,&P5OUT ; TRF6900 active, STANDBY(P5.6) is high CALL #wait_lockdet MOV #TAIE+CLEAR+CONTUP+MCLK,&TACTL ; interrupt enable, clear Timer_A, ; continuous up mode, MCLK as clock source MOV #CCIE+CAP+CMANY,&CCTL2 ; interrupt enable, capture mode, both edges BIS #08h,&data_rx_state ; for suppressing strobe pulse at the end ; of the programming routine BIS.B #greenLED,&P2OUT ; switch on the system mode greenLED CALL #program_receive_FSK_hold ; goto hold mode BIC #08h,&data_rx_state ; reset the the "suppressing mode" BIC.B #data,&P5OUT ; reset data (5.2) ;------------------------ scanning the received signal for the training sequence ------------------------------- loop_receive_training_seq CMP #08h,wake_up_counter ; 8 equal pulses in succession JL loop_receive_training_seq ; no the result is less than 8 equal pulses in a row BIC #022h,&TACTL ; stop Timer_A and disable interrupt BIC #CCIE,&CCTL2 ; disable interrupt INCD RSTAT ; RSTAT = 4 start_bit_reception ; waiting for the start_bit BIS.B #strobe,&P5OUT ; set strobe(P5.4) BIC.B #strobe,&P5OUT ; clear strobe(P5.4) MOV #TAIE+CLEAR+CONTUP+MCLK,&TACTL ; interrupt enable, clear Timer_A, continuous ; up mode, MCLK as clock source MOV #CCIE+CAP+CMANY,&CCTL2 ; interrupt enable, capture mode, both edges loop_start_bit CMP #04h,RSTAT ; has the start bit been detected? JEQ loop_start_bit ; wait for the start bit JN receive_RF ; the received sequence is invalid BIC.B #rxd,&P1IE ; disable P1.2 interrupt ;---------------------------------------------- start bit detected ----------------------------------------------------------- init_data_reception ; RSTAT = 6, Start Bit detected, Data Reception NOP ; insert for the right timing NOP MOV #WDTPW+WDTTMSEL+WDTCNTCL+03h,&WDTCTL ; Reset, Timer Mode, Password, every 26µs MOV #022h,counter ; Initialize counter init_rx_bit_counter

XIV

CLR bits_r ; Reset bitcounter word_reception_loop BIS #CPUOFF+GIE,SR ; go to sleep! BIT.B #02h,&P1IN ; is RXDATA high or low? read_data RLC data_r ; push carry into the data register INC bits_r CMP #010h,bits_r ; receive 16 bits in row JNE word_reception_loop ; haven't received 8bits yet store_data INV data_r ; the received data is inverted! MOV data_r,0222h(counter) ; store received data to RAM DECD counter ; next storage register JNZ init_rx_bit_counter ; receive the next word BIC.B #greenLED,&P2OUT ; system LED off for test purpose BIS #02h,&data_rx_state ; 2 stands for data received, has to be send to desktop via RS232 BIS #020h,&data_rx_state ; initialize the acknowledge state end_receive_RF BIC #CCIE,&CCTL2 ; disable CCR2 interrupt BIC #022h,&TACTL ; stop Timer_A and disable interrupt MOV #WDTPW+WDTHOLD,&WDTCTL ; stop Watchdog Timer CALL #checksum_r ; calculate checksum of received data BIC.B #stdb_trf6900,&P5OUT ; clear STDBY(P5.6), TRF6900 in standby mode RET ;**************************************** rs232_send ******************************************************* ; last change: April 12th 2000 ; ; purpose: the transmission of the received data from TRF6900 to the PC via RS232-Port ; ;************************************************************************************************************** rs232_send BIT #02h,&data_rx_state ; is there any data in the reception buffer, ; which hasn't been sent to the desktop? JZ end_rs232_send ; no the reception buffer is empty BIC.B #cts,&P1OUT ; reset CTS BIC.B #stdb_rs232,&P5OUT ; activate RS232 driver MOV #032Eh,wait_r ; initialize wait register for ca. 1ms waiting loop CALL #wait_x_cycles ; wait for RS232 driver ready to transmit MOV.B #DIVA_2,&FLL_CTL1 ; set the divider for ACLK to 2, high frequency oscillator MOV #020h,counter ; Initialize counter BIS.B #01h,&IE1 ; enable Watchdog Timer interrupt MOV #WDTPW+WDTTMSEL+WDTCNTCL+07h,&WDTCTL ; Reset, Timer Mode, Password, every 52.08µs EINT ; general Interrupt enable rs232_send_init MOV.B 0223h(counter),data_r ; move the first received word into the output buffer MOV #0Ah,bits_r ; send only 8bit in a row BIS #0100h,data_r ; prepare stop bit CLRC ; set carry, prepare start bit RLC data_r ; prepare the output buffer for data transmission rs232_send_loop RRC data_r ; push next bit to carry for transmission JNC rs232_send_low rs232_send_high

XV

BIS #CPUOFF+GIE,SR ; CPU off BIS.B #txd,&P1OUT ; set TXD DEC bits_r ; decrement bit counter JNZ rs232_send_loop rs232_send_next_byte DEC counter ; decrement byte counter JNZ rs232_send_init ; get the next byte for transmission BIC #02h,&data_rx_state ; the buffer is ready to receive from TRF6900 the next data JMP end_rs232_send_lp ; rs232_send_low BIS #CPUOFF+GIE,SR ; CPU off BIC.B #txd,&P1OUT ; reset TXD DEC bits_r ; decrement bit counter JNZ rs232_send_loop JMP rs232_send_next_byte end_rs232_send_lp ; generate the last change of the TXD BIS #CPUOFF+GIE,SR ; CPU off BIS.B #txd,&P1OUT ; TXD by default high, data toggles the TXD end_rs232_send DINT ; MOV #WDTPW+WDTHOLD,&WDTCTL ; stop Watchdog Timer BIS.B #greenLED,&P2OUT ; set System LED for test purpose RET ;*************************************** checksum_s ******************************************************* ; last change: April 11th 2000 ; ; purpose: calculate the checksum of the received data package from RS232, for secure data ; transmission ; (Flash reprogramming via RF) ; ;************************************************************************************************************** checksum_s MOV #020h,counter ; initialize counter CLR chcksum_s ; reset checksum checksum_s_loop ADD 0200h(counter),chcksum_s ; calculate checksum of the whole data package, that has to be send DECD counter JNZ checksum_s_loop MOV chcksum_s,&0222h ; save checksum end_checksum_s RET ;**************************************** checksum_r ******************************************************* ; last change: April 11th 2000 ; purpose: the checksum of the received data package from RF, for reliable data transmission ; (Flash reprogramming via RF) ;************************************************************************************************************** checksum_r BIT #040h,&data_rx_state ; expecting acknowledge? JNZ end_checksum_r ; no need to calculate the checksum MOV #020h,counter ; initialize counter

XVI

CLR chcksum_r ; reset checksum checksum_r_loop ADD 0222h(counter),chcksum_r ; calculate checksum of the entire data to send DECD counter JNZ checksum_r_loop MOV chcksum_r,&0200h ; save checksum end_checksum_r RET ;*********************************** check_checksum_s *************************************************** ; last change: February 29th 2000 ; ; purpose: compares the received checksum from the receiver, with the checksum of the ; received data ; from the PC via RS232 ; ;************************************************************************************************************** check_checksum_s ; BIT #040h,&data_rx_state ; check if waiting for an acknowledge JZ end_check_checksum_s ; CMP &0222h,&0244h ; compare the both checksums JNE end_check_checksum_s ; no the received data isn't valid check_checksum_s_ok ; MOV #06F6Bh,&0242h ; move "ok" to the first word MOV #06F6Bh,&0240h ; MOV #06F6Bh,&023Eh ; MOV #06F6Bh,&023Ch ; MOV #06F6Bh,&023Ah MOV #06F6Bh,&0238h MOV #06F6Bh,&0236h MOV #06F6Bh,&0234h MOV #06F6Bh,&0232h MOV #06F6Bh,&0230h MOV #06F6Bh,&022Eh MOV #06F6Bh,&022Ch MOV #06F6Bh,&022Ah MOV #06F6Bh,&0228h MOV #06F6Bh,&0226h MOV #06F6Bh,&0224h BIS #02h,&data_rx_state ; set the data package received state CALL #rs232_send ; send the "ok" to the PC BIC #040h,&data_rx_state ; reset the state "waiting for acknowledge" BIC #020h,&data_rx_state ; reset the state "acknowledge to send" BIC #02h,&data_rx_state ; reset the state "data_package_received" end_check_checksum_s ; RET ;********************************* check_checksum_r ***************************************************** ; last change: April 13th 2000 ; ; purpose: - Compares the received checksum, that has been calculated by the transmitter for ; the received data package via RS232, with the checksum calculated on the receiver ; ; side of the received data package via RF. ; - If the two checksums are equal, the received data package is send of via RS232, ; and the checksum is send as an acknowledge back to the sender. ; - IF the checksums aren't equal the package is not send via RS232 to the PC, and ; no acknowledge will be send to the sender. ;************************************************************************************************************** check_checksum_r BIT #040h,&data_rx_state ; check if waiting for an acknowledge

XVII

JNZ end_check_checksum_r BIT #02h,&data_rx_state ; is there any data in the reception buffer, ; which hasn't been sent to the desktop? JZ end_check_checksum_r ; no, no new data package CMP &0200h,&0244h ; are the checksums equal? JEQ end_check_checksum_r ; yes the data is valid check_checksum_r_inv BIC #02h,&data_rx_state ; reset the data package received state BIC #020h,&data_rx_state ; reset the acknowledge to send state end_check_checksum_r RET ;****************************************** wait loops ******************************************************* ; last change: August 11th 1999 ; ; purpose: used for various timings, e.g. NRZ reception and transmission ; ;************************************************************************************************************** wait_x_cycles ; waits 13 + x times 3 cycles DEC wait_r JNZ wait_x_cycles end_wait_x_cycles RET ;**************************************** wait for lockdetect ************************************************ ; last change: September 6th 1999 ; ; wait routine for the Lockdetect signal ; ;************************************************************************************************************** wait_lockdet BIT.B #lockdet,&P2IN ; is the LOCKDET(P2.1) set? ;****************************************************************** ; debug just to make LED flash ;****************************************************************** BIC.B #greenLED,&P2OUT ;green LED off MOV.B #greenLED,&P2OUT ;green LED on JZ wait_lockdet ; not yet end_wait_lockdet RET ;************************************** Timer_A Interrupt routine ****************************************** ; last change: July 27th 1999 ; ; purpose: handle the Timer_A interrupts, and decide which dedicated routine should be ; addressed. (CC1_INT / RS232 reception, CC2_INT / RF reception) ;************************************************************************************************************** TA_INT ADD &TAIV,PC RETI JMP CC1_INT ; RS232 reception -> falling edge of the start bit JMP CC2_INT ; RF reception -> every edge of the rx-signal RETI RETI RETI

XVIII

;******************************* Capture Compare 1 Register ********************************************* ; last change: April 11th 2000 ; ; purpose: RS232-Reception ; ;************************************************************************************************************** CC1_INT BIC #CCIE,&CCTL1 ; disable CCR1 interrupt BIT #04h,&data_rx_state ; is the RS232 buffer full? JNZ end_CC1_INT ; yes, do not receive further data MOV #08h,bits_r ; init bit counter MOV #020h,counter ; init byte counter BIC #022h,&TACTL ; stop Timer_A and disable interrupt BIC #CCIE,&CCTL2 ; disable interrupt EINT rs232_init_WDT MOV.B #DIVA_2,&FLL_CTL1 ; set the divider for ACLK to 2, high frequency oscillator MOV #WDTPW+WDTTMSEL+WDTCNTCL+07h,&WDTCTL ; Reset, Timer Mode, Password, every 52.08µs rs232_rec_data BIS #CPUOFF+GIE,SR ; CPU off BIC.B #greenLED,&P2OUT ; greenLED off BIT.B #rxd,&P1IN ; is the rx line high, or low? rs232_push_buffer RRC data_r ; push carry to reception buffer DEC bits_r ; decrement bit counter JNZ rs232_rec_data ; read the next bit rs232_stop_bit BIS #CPUOFF+GIE,SR ; CPU off BIS #04h,&data_rx_state ; set the data reception state to received! MOV #WDTPW+WDTHOLD,&WDTCTL ; stop watchdog timer rs232_start_bit ; waits for the next start bit BIT.B #rxd,&P1IN ; wait for the falling edge of the start bit for synchronization JNZ rs232_start_bit MOV #WDTPW+WDTTMSEL+WDTCNTCL+07h,&WDTCTL ; Reset, Timer Mode, Password, every 52.08µs MOV #08h,wait_r ; init wait parameter CALL #wait_x_cycles MOV #08h,bits_r ; init bit counter SWPB data_r ; swap high and low byte of the receive buffer MOV.B data_r,0201h(counter) ; store the received data to RAM for RF-Transmission DEC counter ; decrement the byte counter JNZ rs232_rec_data ; get the next byte end_CC1_INT MOV #WDTPW+WDTHOLD,&WDTCTL ; stop watchdog timer BIS #040h,&data_rx_state ; set the status on waiting for acknowledge CALL #checksum_s ; built checksum over received data MOV #022h,counter ; init counter CALL #send_RF ; send the received data out BIC #CPUOFF+GIE,0(SP) ; wake up from sleep mode MOV #receive_RF,2(SP) ; do not return to the original address ; before the interrupt request, but start

XIX

; at the beginning of the receive_RF subroutine RETI ;******************************* Capture Compare 2 Register ********************************************* ; last change: October 19th 1999 ; ; purpose: RF-Reception ; ;************************************************************************************************************** CC2_INT ; supports receive_RF MOV #WDTPW+WDT26MS+WDTCNTCL+WDTTMSEL,&WDTCTL ; ACLK, ca.106ms, Timer Mode, Reset MOV RRFTAB(RSTAT),PC ; conditional jump depends on RSTAT ; RSTAT = 0, detecting the Trainingsequence ; RSTAT = 1, Trainingsquence detected, waiting for the Start Bit ; RSTAT = 2, Start Bit detected, Data Reception RRFTAB DW RSTAT00 DW RSTAT01 DW RSTAT10 RSTAT00 MOV &CCR2,res_new_r ; save Reference Capture value MOV res_new_r,res_r ; copy Timer_A value SUB res_old_r,res_r ; subtract the current Timer_A value from the ; old one -> Bitwidth in cycles in res_r MOV res_new_r,res_old_r ; current value now -> old value later test_res_r00 SUB #038h,res_r ; subtract the average value from the measured value CMP #010h,res_r ; is the detected signal 51-63 cycles long? JHS no_valid_pulse INCD RSTAT ; first valid pulse detected INC wake_up_counter ; count this valid pulse RETI no_valid_pulse CLR RSTAT ; no the signal doesn't fit the wakeup sequence CLR wake_up_counter ; reset the wake_up_counter, received an invalid pulse RETI RSTAT01 MOV &CCR2,res_new_r ; save Reference Capture value MOV res_new_r,res_r ; copy Timer_A value SUB res_old_r,res_r ; subtract the current Timer_A value from the ; old one -> Bitwidth in cycles in res_r MOV res_new_r,res_old_r ; current value now -> old value later test_res_r01 SUB #038h,res_r ; subtract the average value from the measured value CMP #010h,res_r ; is the detected signal 51-63 cycles long? JHS no_valid_pulse INC wake_up_counter ; next valid pulse RETI RSTAT10 MOV &CCR2,res_new_r ; save Reference Capture value MOV res_new_r,res_r ; copy Timer_A value SUB res_old_r,res_r ; subtract the current Timer_A value from ; the old one -> Bitwidth in cycles in res_r MOV res_new_r,res_old_r ; current value now -> old value later

XX

test_res_r10 SUB #0ACh,res_r ; subtract the average value from the measured value CMP #028h,res_r ; is the detected signal x cycles long? JGE invalid_bit ; restart detection, this is not a valid sequence JHS no_start_bit INCD RSTAT ; go to RSTATE 2, Data Reception, Start Bit detected BIC #CCIE,&CCTL2 ; disable CCR2 interrupt BIC #022h,&TACTL ; stop Timer_A and disable interrupt no_start_bit INC wake_up_counter ; count the pulses of the trainings sequence, ; to terninate at least after 8ms CMP #02Fh,wake_up_counter ; compare the value of the counter with the ; maximum value of the pulses of the trainings sequence JGE invalid_bit ; RETI invalid_bit CMP #08h,wake_up_counter ; to avoid errors during the first run JEQ invalid_bit_end ; skip clearing RSTAT CLR RSTAT ; restart the detection, this is not a valid sequence CLR wake_up_counter ; initialize the wake_up_counter invalid_bit_end RETI ;******************************* WDT Interrupt Routine **************************************************** ; last change: August 19th 1999 ; purpose: generate periodical wakeup for communication routines (timing generation) ; ;************************************************************************************************************** WDT_INT BIC #CPUOFF,0(SP) ; reactivate CPU RETI ;***************************************** Interrupt vector table ******?************************************** ; last change: 04/11/02 ; ;************************************************************************************************************** reset RSEG INTVEC ; DW START ; Basic Timer DW START ; 0FFE2h I/O Port P2 DW START ; 0FFE4h not used DW START ; 0FFE6h not used DW START ; 0FFE8h I/O Port P1 DW TA_INT ; 0FFEAh Timer_A3 CC1, CC2, TA DW START ; 0FFECh Timer_A3 CC0 DW START ; 0FFEEh not used DW START ; 0FFF0h not used DW START ; 0FFF2h CC0_INT DW WDT_INT ; 0FFF4h Watchdog Timer in timer mode DW START ; 0FFF6h Comparator_A DW START ; 0FFF8h not used DW START ; 0FFFAh not used DW START ; 0FFFCh NMI, Oscillator fault, ACCV DW START ; 0FFFEh Power On Reset, WDTIFG END main

XXI

/************************************************************************************************************** * Special and standard definitions for the MSP-EVKTRF6900 (ISU Senior Design), * used Device: MSP430F413 * * last change: 4/10/2002 * * Texas Instruments - Iowa State University * **************************************************************************************************************/ /************************************************************************************************************** * STATUS REGISTER BITS **************************************************************************************************************/ #define C 0x0001 #define Z 0x0002 #define N 0x0004 #define V 0x0100 #define GIE 0x0008 #define CPUOFF 0x0010 #define OSCOFF 0x0020 #define SCG0 0x0040 #define SCG1 0x0080 /* Low Power Modes coded with Bits 4-7 in SR */ #ifndef __IAR_SYSTEMS_ICC /* Begin #defines for assembler */ #define LPM0 CPUOFF #define LPM1 SCG0+CPUOFF #define LPM2 SCG1+CPUOFF #define LPM3 SCG1+SCG0+CPUOFF #define LPM4 SCG1+SCG0+OSCOFF+CPUOFF /* End #defines for assembler */ #else /* Begin #defines for C */ #define LPM0_bits CPUOFF #define LPM1_bits SCG0+CPUOFF #define LPM2_bits SCG1+CPUOFF #define LPM3_bits SCG1+SCG0+CPUOFF #define LPM4_bits SCG1+SCG0+OSCOFF+CPUOFF #include "In430.h" #define LPM0 BIS_SR(LPM0_bits) /* Enter Low Power Mode 0 */ #define LPM0_EXIT _BIC_SR(LPM0_bits) /* Exit Low Power Mode 0 */ #define LPM1 _BIS_SR(LPM1_bits) /* Enter Low Power Mode 1 */ #define LPM1_EXIT _BIC_SR(LPM1_bits) /* Exit Low Power Mode 1 */ #define LPM2 _BIS_SR(LPM2_bits) /* Enter Low Power Mode 2 */ #define LPM2_EXIT _BIC_SR(LPM2_bits) /* Exit Low Power Mode 2 */ #define LPM3 _BIS_SR(LPM3_bits) /* Enter Low Power Mode 3 */ #define LPM3_EXIT _BIC_SR(LPM3_bits) /* Exit Low Power Mode 3 */ #define LPM4 _BIS_SR(LPM4_bits) /* Enter Low Power Mode 4 */ #define LPM4_EXIT _BIC_SR(LPM4_bits) /* Exit Low Power Mode 4 */ #endif /* End #defines for C */ /************************************************************************************************************** * PERIPHERAL FILE MAP **************************************************************************************************************/ /************************************************************************************************************** * SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS **************************************************************************************************************/ #define IE1_ 0x0000 /* Interrupt Enable 1 */ sfrb IE1 = IE1_; #define WDTIE 0x01 #define OFIE 0x02 #define NMIIE 0x10 #define ACCVIE 0x20 /********************************************************************************************** * added code for basic timer

XXII

**********************************************************************************************/ #define IE2_ 0x0001 /* Interrupt Enable 2 */ sfrb IE2 = IE2_ #define BTIE 0x40 #define IFG1_ 0x0002 /* Interrupt Flag 1 */ sfrb IFG1 = IFG1_ #define WDTIFG 0x01 #define OFIFG 0x02 #define NMIIFG 0x10 /********************************************************************************************** * added code for basic timer **********************************************************************************************/ #define IFG2_ 0x0003 /* Interrupt Flag 2 */ sfrb IFG2 = IFG2_ #define BTIFG 0x40 #define ME1_ 0x0004 /* Module Enable 1 */ sfrb ME1 = ME1_ ;#define IE2_ 0x0001 /* Interrupt Enable 2 */ ;sfrb IE2 = IE2_ ;#define IFG2_ 0x0003 /* Interrupt Flag 2 */ ;sfrb IFG2 = IFG2_ #define ME2_ 0x0005 /* Module Enable 2 */ sfrb ME2 = ME2_ /************************************************************************************************************** * WATCHDOG TIMER **************************************************************************************************************/ #define WDTCTL_ 0x0120 /* Watchdog Timer Control */ sfrw WDTCTL = WDTCTL_ /* The bit names have been prefixed with "WDT" */ #define WDTIS0 0x0001 #define WDTIS1 0x0002 #define WDTSSEL 0x0004 #define WDTCNTCL 0x0008 #define WDTTMSEL 0x0010 #define WDTNMI 0x0020 #define WDTNMIES 0x0040 #define WDTHOLD 0x0080 #define WDTPW 0x5A00 /* WDT-interval times [1ms] coded with Bits 0-2 */ /* WDT is clocked by fMCLK (assumed 1MHz) */ #define WDT_MDLY_32 WDTPW+WDTTMSEL+WDTCNTCL /* 32ms interval (default) */ #define WDT_MDLY_8 WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0 /* 8ms " */ #define WDT_MDLY_0_5 WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1 /* 0.5ms " */ #define WDT_MDLY_0_064 WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0 /* 0.064ms " */ /* WDT is clocked by fACLK (assumed 32KHz) */ #define WDT_ADLY_1000 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL /* 1000ms " */ #define WDT_ADLY_250 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0 /* 250ms " */ #define WDT_ADLY_16 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1 /* 16ms " */ #define WDT_ADLY_1_9 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0 /* 1.9ms " */ /* Watchdog mode -> reset after expired time */ /* WDT is clocked by fMCLK (assumed 1MHz) */ #define WDT_MRST_32 WDTPW+WDTCNTCL /* 32ms interval (default) */ #define WDT_MRST_8 WDTPW+WDTCNTCL+WDTIS0 /* 8ms " */ #define WDT_MRST_0_5 WDTPW+WDTCNTCL+WDTIS1 /* 0.5ms " */ #define WDT_MRST_0_064 WDTPW+WDTCNTCL+WDTIS1+WDTIS0 /* 0.064ms " */ /* WDT is clocked by fACLK (assumed 32KHz) */ #define WDT_ARST_1000 WDTPW+WDTCNTCL+WDTSSEL /* 1000ms " */

XXIII

#define WDT_ARST_250 WDTPW+WDTCNTCL+WDTSSEL+WDTIS0 /* 250ms " */ #define WDT_ARST_16 WDTPW+WDTCNTCL+WDTSSEL+WDTIS1 /* 16ms " */ #define WDT_ARST_1_9 WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0 /* 1.9ms " */ /* INTERRUPT CONTROL */ /* These two bits are defined in the Special Function Registers */ /* #define WDTIE 0x01 */ /* #define WDTIFG 0x01 */ /************************************************************************************************************** * DIGITAL I/O Port1/2 **************************************************************************************************************/ #define P1IN_ 0x0020 /* Port 1 Input */ const sfrb P1IN = P1IN_ #define P1OUT_ 0x0021 /* Port 1 Output */ sfrb P1OUT = P1OUT_ #define P1DIR_ 0x0022 /* Port 1 Direction */ sfrb P1DIR = P1DIR_ #define P1IFG_ 0x0023 /* Port 1 Interrupt Flag */ sfrb P1IFG = P1IFG_ #define P1IES_ 0x0024 /* Port 1 Interrupt Edge Select */ sfrb P1IES = P1IES_ #define P1IE_ 0x0025 /* Port 1 Interrupt Enable */ sfrb P1IE = P1IE_ #define P1SEL_ 0x0026 /* Port 1 Selection */ sfrb P1SEL = P1SEL_ #define P2IN_ 0x0028 /* Port 2 Input */ const sfrb P2IN = P2IN_ #define P2OUT_ 0x0029 /* Port 2 Output */ sfrb P2OUT = P2OUT_ #define P2DIR_ 0x002A /* Port 2 Direction */ sfrb P2DIR = P2DIR_ #define P2IFG_ 0x002B /* Port 2 Interrupt Flag */ sfrb P2IFG = P2IFG_ #define P2IES_ 0x002C /* Port 2 Interrupt Edge Select */ sfrb P2IES = P2IES_ #define P2IE_ 0x002D /* Port 2 Interrupt Enable */ sfrb P2IE = P2IE_ #define P2SEL_ 0x002E /* Port 2 Selection */ sfrb P2SEL = P2SEL_ /************************************************************************************************************** * DIGITAL I/O Port 3/4/5/6 **************************************************************************************************************/ #define P3IN_ 0x0018 /* Port 3 Input */ const sfrb P3IN = P3IN_ #define P3OUT_ 0x0019 /* Port 3 Output */ sfrb P3OUT = P3OUT_ #define P3DIR_ 0x001A /* Port 3 Direction */ sfrb P3DIR = P3DIR_ #define P3SEL_ 0x001B /* Port 3 Selection */

XXIV

sfrb P3SEL = P3SEL_ #define P4IN_ 0x001C /* Port 4 Input */ const sfrb P4IN = P4IN_ #define P4OUT_ 0x001D /* Port 4 Output */ sfrb P4OUT = P4OUT_ #define P4DIR_ 0x001E /* Port 4 Direction */ sfrb P4DIR = P4DIR_ #define P4SEL_ 0x001F /* Port 4 Selection */ sfrb P4SEL = P4SEL_ #define P5IN_ 0x0030 /* Port 5 Input */ const sfrb P5IN = P5IN_ #define P5OUT_ 0x0031 /* Port 5 Output */ sfrb P5OUT = P5OUT_ #define P5DIR_ 0x0032 /* Port 5 Direction */ sfrb P5DIR = P5DIR_ #define P5SEL_ 0x0033 /* Port 5 Selection */ sfrb P5SEL = P5SEL_ #define P6IN_ 0x0034 /* Port 6 Input */ const sfrb P6IN = P6IN_ #define P6OUT_ 0x0035 /* Port 6 Output */ sfrb P6OUT = P6OUT_ #define P6DIR_ 0x0036 /* Port 6 Direction */ sfrb P6DIR = P6DIR_ #define P6SEL_ 0x0037 /* Port 6 Selection */ sfrb P6SEL = P6SEL_ /************************************************************************************************************** * Timer_A **************************************************************************************************************/ #define TAIV_ 0x012E /* Timer A Interrupt Vector Word */ sfrw TAIV = TAIV_ #define TACTL_ 0x0160 /* Timer A Control */ sfrw TACTL = TACTL_ #define CCTL0_ 0x0162 /* Timer A Capture/Compare Control 0 */ sfrw CCTL0 = CCTL0_ #define CCTL1_ 0x0164 /* Timer A Capture/Compare Control 1 */ sfrw CCTL1 = CCTL1_ #define CCTL2_ 0x0166 /* Timer A Capture/Compare Control 2 */ sfrw CCTL2 = CCTL2_ #define CCTL3_ 0x0168 /* Timer A Capture/Compare Control 3 */ sfrw CCTL3 = CCTL3_ #define CCTL4_ 0x016A /* Timer A Capture/Compare Control 4 */ sfrw CCTL4 = CCTL4_ #define TAR_ 0x0170 /* Timer A */ sfrw TAR = TAR_ #define CCR0_ 0x0172 /* Timer A Capture/Compare 0 */ sfrw CCR0 = CCR0_ #define CCR1_ 0x0174 /* Timer A Capture/Compare 1 */

XXV

sfrw CCR1 = CCR1_ #define CCR2_ 0x0176 /* Timer A Capture/Compare 2 */ sfrw CCR2 = CCR2_ #define CCR3_ 0x0178 /* Timer A Capture/Compare 3 */ sfrw CCR3 = CCR3_ #define CCR4_ 0x017A /* Timer A Capture/Compare 4 */ sfrw CCR4 = CCR4_ #define TASSEL2 0x0400 /* to distinguish from UART SSELx */ #define TASSEL1 0x0200 #define TASSEL0 0x0100 #define ID1 0x0080 #define ID0 0x0040 #define MC1 0x0020 #define MC0 0x0010 #define TACLR 0x0004 #define TAIE 0x0002 #define TAIFG 0x0001 #define MC_0 00*10h #define MC_1 01*10h #define MC_2 02*10h #define MC_3 03*10h #define ID_0 00*40h #define ID_1 01*40h #define ID_2 02*40h #define ID_3 03*40h #define TASSEL_0 00*100h #define TASSEL_1 01*100h #define TASSEL_2 02*100h #define TASSEL_3 03*100h #define CM1 0x8000 #define CM0 0x4000 #define CCIS1 0x2000 #define CCIS0 0x1000 #define SCS 0x0800 #define SCCI 0x0400 #define CAP 0x0100 #define OUTMOD2 0x0080 #define OUTMOD1 0x0040 #define OUTMOD0 0x0020 #define CCIE 0x0010 #define CCI 0x0008 #define OUT 0x0004 #define COV 0x0002 #define CCIFG 0x0001 #define OUTMOD_0 00*20h #define OUTMOD_1 01*20h #define OUTMOD_2 02*20h #define OUTMOD_3 03*20h #define OUTMOD_4 04*20h #define OUTMOD_5 05*20h #define OUTMOD_6 06*20h #define OUTMOD_7 07*20h #define CCIS_0 00*1000h #define CCIS_1 01*1000h #define CCIS_2 02*1000h #define CCIS_3 03*1000h #define CM_0 00*4000h #define CM_1 01*4000h #define CM_2 02*4000h #define CM_3 03*4000h

XXVI

#define CLEAR 0x0004 /* clear the Timer_A */ #define CMPOS 0X4000 /* select rising edge */ #define CMNEG 0x8000 /* select falling edge */ #define CMANY 0xC000 /* select every edge */ #define CONTUP 0x0020 /* continuous up mode */ #define MCLK 0x0200 /* select MCLK as clokc source */ /************************************************************************************************************** * Basic Clock Module **************************************************************************************************************/ #define FLL_CTL1_ 0x0054 /* FLL + Control 1 */ sfrb FLL_CTL1 = FLL_CTL1_ #define FLL_CTL0_ 0x0053 /* FLL + Control 0 */ sfrb FLL_CTL0 = FLL_CTL0_ #define SCFQCTL_ 0x0052 /* System clock frequency cotrol */ sfrb SCFQCTL = SCFQCTL_ #define SCFI1_ 0x0051 /* System clock frequency integrator */ sfrb SCFI1 = SCFI1_ #define SCFI2_ 0x0050 /* System clock frequency integrator */ sfrb SCFI2 = SCFI2_ #define BTCNT2_ 0x0047 /* BT counter2 */ sfrb BTCNT2 = BTCNT2_ #define BTCNT1_ 0x0046 /* BT counter1 */ sfrb BTCNT1 = BTCNT1_ #define BTCTL_ 0x0045 /* BT Control */ sfrb BTCTL = BTCTL_ #define MOD0 0x01 #define MOD1 0x02 #define MOD2 0x04 #define MOD3 0x08 #define MOD4 0x10 #define DCO0 0x20 #define DCO1 0x40 #define DCO2 0x80 #define RSEL0 0x01 #define RSEL1 0x02 #define RSEL2 0x04 #define XT5V 0x08 #define DIVA0 0x10 #define DIVA1 0x20 ;#define XTS 0x40 /* might not need for F413, compensated by using DIVA_2 */ #define XTOFF 0x80 #define DCOR 0x01 #define DIVS0 0x02 #define DIVS1 0x04 #define SELS 0x08 #define DIVM0 0x10 #define DIVM1 0x20 #define SELM0 0x40 #define SELM1 0x80 /************************************************************************************************************** * Flash Memory **************************************************************************************************************/ #define FCTL1_ 0x0128 /* FLASH Control 1 */ sfrw FCTL1 = FCTL1_ #define FCTL2_ 0x012A /* FLASH Control 2 */

XXVII

sfrw FCTL2 = FCTL2_ #define FCTL3_ 0x012C /* FLASH Control 3 */ sfrw FCTL3 = FCTL3_ #define FRKEY 0x9600 #define FWKEY 0xA500 #define FXKEY 0x3300 /* for use with XOR instruction */ #define ERASE 0x0002 #define MERAS 0x0004 #define WRT 0x0040 #define SEGWRT 0x0080 #define FN0 0x0001 #define FN1 0x0002 #define FN2 0x0004 #define FN3 0x0008 #define FN4 0x0010 #define FN5 0x0020 #define FSSEL0 0x0040 /* to distinguish from UART SSELx */ #define FSSEL1 0x0080 #define BUSY 0x0001 #define KEYV 0x0002 #define ACCVIFG 0x0004 #define WAIT 0x0008 #define LOCK 0x0010 #define EMEX 0x0020 /************************************************************************************************************** * Comparator A **************************************************************************************************************/ #define CACTL1_ 0x0059 /* Comparator A Control 1 */ sfrb CACTL1 = CACTL1_ #define CACTL2_ 0x005A /* Comparator A Control 2 */ sfrb CACTL2 = CACTL2_ #define CAPD_ 0x005B /* Comparator A Port Disable */ sfrb CAPD = CAPD_ #define CAIFG 0x01 #define CAIE 0x02 #define CAIES 0x04 #define CAON 0x08 #define CAREF0 0x10 #define CAREF1 0x20 #define CARSEL 0x40 #define CAEX 0x80 #define CAOUT 0x01 #define CAF 0x02 #define P2CA0 0x04 #define P2CA1 0x08 #define CACTL24 0x10 #define CACTL25 0x20 #define CACTL26 0x40 #define CACTL27 0x80 #define CAPD0 0x01 #define CAPD1 0x02 #define CAPD2 0x04 #define CAPD3 0x08 #define CAPD4 0x10 #define CAPD5 0x20 #define CAPD6 0x40 #define CAPD7 0x80 /**************************************************************************************************************

XXVIII

* Interrupt Vectors (offset from 0xFFE0) **************************************************************************************************************/ ;#define WDT_VECTOR 10 * 2 /* 0xFFF4 Watchdog Timer */ ;#define NMI_VECTOR 14 * 2 /* 0xFFFC Non-maskable */ ;#define RESET_VECTOR 15 * 2 /* 0xFFFE Reset [Highest Priority] */ ;#define PORT1_VECTOR 2 * 2 /* 0xFFE4 Port 1 */ ;#define PORT2_VECTOR 3 * 2 /* 0xFFE6 Port 2 */ ;#define TIMERA1_VECTOR 8 * 2 /* 0xFFF0 Timer A CC1-2, TA */ ;#define TIMERA0_VECTOR 9 * 2 /* 0xFFF2 Timer A CC0 */ ;#define COMPARATORA_VECTOR 11 * 2 /* 0xFFF6 Comparator A */ /*** * new set of interrupts ****/ #define BT_VECTOR 0 * 2 /* 0xFFE0 Basic Timer1 [Lowest Priority] */ #define PORT2_VECTOR 1 * 2 /* 0xFFE2 Port 2 */ #define PORT1_VECTOR 4 * 2 /* 0xFFE8 Port 1 */ #define TIMERA1_VECTOR 5 * 2 /* 0xFFEA Timer A3 CC1-2, TA */ #define TIMERA0_VECTOR 6 * 2 /* 0xFFEC Timer A3 CC0 */ #define WDT_VECTOR 10 * 2 /* 0xFFF4 Watchdog Timer */ #define COMPARATORA_VECTOR 11 * 2 /* 0xFFF6 Comparator A */ #define NMI_VECTOR 14 * 2 /* 0xFFFC NMI, OF, ACCV, NonMaskable */ #define RESET_VECTOR 15 * 2 /* 0xFFFE Reset [Highest Priority] */ /************************************************************************************************************** * Port 1 definition for the MSP-EVKTRF6900 **************************************************************************************************************/ #define cts 0x0001 /* P1.0 clear to send (RS232) */ #define rxd 0x0002 /* P1.1 RXD_MSP, receive data from RS232 */ #define rts 0x0004 /* P1.2 request to send (RS232) */ #define txd 0x0008 /* P1.3 TXD_MSP, sent data to the PC via RS232 */ /************************************************************************************************************** * Port 2 definition for the MSP-EVKTRF6900 **************************************************************************************************************/ #define rx 0x0001 /* P2.0 RXDATA, receive data from TRF6900 */ #define lockdet 0x0002 /* P2.1 Lock Detect, the PLL has locked at the selected frequency */ #define greenLED 0x0040 /* P2.6 General purpose on-board led (green) */ #define yellowLED 0x0080 /* P2.7 General purpose on-boardl led (yellow) */ /************************************************************************************************************** * Port 3 definition for the MSP-EVKTRF6900 **************************************************************************************************************/ #define mode0 0x0001 /* P3.0 Mode 0 */ #define mode1 0x0002 /* P3.1 Mode 1 */ #define mode2 0x0004 /* P3.2 Mode 2 */ #define mode3 0x0008 /* P3.3 Mode 3 */ #define mode4 0x0010 /* P3.4 Mode 4 */ #define channel0 0x0020 /* P3.5 Channel 0 */ #define channel1 0x0040 /* P3.6 Channel 1 */ #define channel2 0x0080 /* P3.7 Channel 2 */ /************************************************************************************************************** * Port 4 definition for the MSP-EVKTRF6900 **************************************************************************************************************/ #define channel3 0x0001 /* P4.0 Channel 3 */ #define channel4 0x0002 /* P4.1 Channel 4 */ #define UID0 0x0004 /* P4.2 Unit ID bit 0 */ #define UID1 0x0008 /* P4.3 Unit ID bit 1 */ #define UID2 0x0010 /* P4.4 Unit ID bit 2 */ #define UID3 0x0020 /* P4.5 Unit ID bit 3 */

XXIX

#define UID4 0x0040 /* P4.6 Unit ID bit 4 */ #define UID5 0x0080 /* P4.7 Unit ID bit 5 */ /************************************************************************************************************** * Port 5 definition for the MSP-EVKTRF6900 **************************************************************************************************************/ #define stdb_rs232 0x0001 /* P5.0 Standby Mode for RS232(Standby Hi) */ #define stdbGP 0x0002 /* P5.1 General Buffer Standby (Standby Hi) */ #define data 0x0004 /* P5.2 DATA, programming data into the TRF6900 */ #define clk 0x0008 /* P5.3 CLK, programming clock of the TRF6900 */ #define strobe 0x0010 /* P5.4 STROBE, STROBE line to the TRF6900 */ #define mode 0x0020 /* P5.5 Mode 1 or Mode 0 for TRF6900 */ #define stdb_trf6900 0x0040 /* P5.6 Standby_N for the TRF6900 */ #define tx 0x0080 /* P5.7 TXDATA, transmit data to the TRF6900 */ /************************************************************************************************************** * SYSTEM DEFINITIONS **************************************************************************************************************/ #define MSTOP 0x0080 /* Stop Mode */ #define MCONT 0x0020 /* Continuous Mode */ /************************************************************************************************************** * Basic Clock Module **************************************************************************************************************/ #define DIVA_2 0x0001 /* divide ACLK by 2 of F413 */ /************************************************************************************************************** * Register Definitions **************************************************************************************************************/ #define data_r R4 /* current transmitted or received byte */ #define word_trf R4 /* programming buffer for the TRF6900 registers */ #define bits_r R5 /* bit counter, counts the bits of the current byte */ #define address_r R6 /* pointer to RAM address of the current received or transmitted byte */ #define word_h R6 /* the high byte of the TRF6900 programming word */ #define word_l R7 /* the low byte of the TRF6900 programming word */ #define address_start R7 /* start addres for transmission */ #define RSTAT R8 /* state of the reception */ #define chcksum_r R8 /* checksum of the received data */ #define chcksum_s R9 /* checksum of the transmitted data */ #define wait_r R9 /* counter register for all waiting loops (no collusion with res_new_r possible) */ #define wake_up_counter R10 /* counter for valid pulses during training phase */ #define counter R10 /* universal counter */ #define current R11 /* buffer for the current result of Timer_A */ #define previous R12 /* buffer for the previous result of Timer_A */ #define res_old_r R13 /* old value of the CCR2 */ #define res_new_r R14 /* new value of the CCR2 difference gives pulse width -> res_r (both only during the RF reception) */ #define res_r R15 /* width of the recently received puls, only during RF reception */ #define tr_counter R15 /* counter for the training sequence */ #define rs232_counter R15 /* used for the detection of the high and low byte during the rs232 reception */ /************************************************************************************************************** * Clock

XXX

**************************************************************************************************************/ #define clock_new_1 0x0003 /* ACLK 1/8 from external crystal */ #define clock_new_2 0xC0 /* MCLK directly from LFXTCL SMCLK directly from MCLK */ /* OSCCap both set to one for now, XTS_FLL = 1 for ext high frequency xtal, dco+ =1 for direct FM clk */ /************************************************************************************************************** * Watchdog Timer **************************************************************************************************************/ #define WDT26MS 0x0005 /* set the timing to 26 microseconds */ /************************************************************************************************************** * Other Registers for RF transmission **************************************************************************************************************/ sfrw data_rx_state = 0x0248 /* stores the state of the RF and RS232 */ /* reception */

XXXI

Appendix D – Build of Materials

Stock: Qty: Value: Device: Package: Distributer: Part Number: Parts:

10 1 LT1962 LT1962 8-MSOP Linear Technology LT1962EMS8-3.3 U5

10 2 SN74ALVCH244 SN74ALVCH244 20-TSS Texas Instruments SN74ALVCH244PWR U4, U6

6 1 SN75LV4737 SN75LV4737 28-SOP Texas Instruments SN75LV4737ADBR U3

6 1 TRF6900A TRF6900A 48-LQFP Texas Instruments TRF6900APT U1

8 1 MSP430F413 MSP430F413 64-LQFP Texas Instruments MSP430F413IPM U2

1 CS4-22YB CS4-22YB Gullwing BC Components CS4-22YB S6

1 CHS-02B1 DIPSWITCH2SMALL Gullwing BC Components CHS-02B1 S5

2 CHS-08B1 DIPSWITCH8SMALL Gullwing BC Components CHS-08B1 S2, S3

2 1 25.6MHz HC45/U HC45/U ICM 865842 CQ1

1 2.4576MHz HC45/U HC45/U Digikey X069-ND CQ2

10 2 10.7MHz MURATAFILTER SMD Chip Murata SFECV10M7JA00-R0 BPF1, BPF2

1 DFCB2915MLDJAA DFCB2915MLDJAA DFCB Murata DFCB2915MLDJAA BPF3

1 SMB Jack BU-SMB-V SMB Digikey A4041-ND X1

2 SMV1247-079 SMV1247-079 SC-79 Alpha SMV1247-079 VD1, VD2

1 SMV1251-079 SMV1251-079 SC-79 Alpha SMV1251-079 VD3

2 100k 2QSP16-8 16-QSOP Vishay VSSR1603104J RP1, RP2

3 68 2QSP16-8 16-QSOP Vishay VSSR1603680J RP3, RP4, RP5

2 1k 2QSP16-8 16-QSOP Vishay VSSR1603102J RP6, RP7

1 Gre LED LED0603 1206 D1

1 Yel LED LED0603 1206 D2

1 Red LED LED0603 1206 D3

10 2 10nH L0603 0603 Murata LQW18AN10NG00D L1, L6

10 1 4.7nH L0603 0603 Murata LQW18AN4N7D00D L2

10 1 8.2uH L0603 0603 Murata LQW18AN8N2D00D L3

10 1 18nF L0603 0603 Murata LQW18AN18NG00D L4

10 1 2.2uH L1214 1214 Murata LQH3ERN2R2G01L L5

20 0.1uF C-EUC0805 0805 Digikey PCC1828CT-ND

C1, C6, C10, C11, C13, C14, C15, C16, C21, C25, C26, C29, C33, C34, C35, C36, C37, C38, C39, C101

1 4.7pF C-EUC0805 1206 Digikey PCC4R7CCT-ND C2

3 100pF C-EUC0805 0805 Digikey PCC101CGCT-ND C3, C9, C20

3 1nF C-EUC0805 0805 Digikey PCC102BNCT-ND C4, C5, C32

2 3.3pF C-EUC0805 1206 Digikey PCC3R3CCT-ND C7, C28

1 680pF C-EUC0805 0805 Digikey PCC681BNCT-ND C8

1 1pF C-EUC0805 0805 Digikey PCC010CNCT-ND C12

1 100pF-1% C-EUC0805 0805 C17

1 330pF C-EUC0805 0805 Digikey PCC331CGCT-ND C19

3 27pF C-EUC0805 0805 Digikey PCC270CGCT-ND C22, C23, C44

1 2.7pF C-EUC0805 1206 Digikey PCC2R7CCT-ND C27

2 10pF C-EUC0805 0805 Digikey PCC100CNCT-ND C30, C31

1 1uF C-EUC0805 0805 Digikey PCC1807CT-ND C40

XXXII

1 10uF Polarized Cap Chip A Digikey PCS1106CT-ND C43

1 0.01uF C-EUC0805 0805 Digikey PCC103BNCT-ND C42

1 56pF C-EUC0805 0805 Digikey PCC560CGCT-ND C45

1 68pF C-EUC0805 0805 Digikey PCC680CGCT-ND C100

4 100k R-US_R0805 0805 Digikey 311-1003CCT-ND R1, R8, R11, R12

1 300k R-US_R0805 0805 Digikey 311-3003CCT-ND R2

2 39k R-US_R0805 0805 Digikey 311-3902CCT-ND R3, R5

3 10k R-US_R0805 0805 Digikey 311-1002CCT-ND R4, R9, R10

1 100 R-US_R0805 0805 Digikey 311-1000CCT-ND R6

1 1M R-US_R0805 0805 Digikey 311-1004CCT-ND R7

4 68 R-US_R0805 0805 Digikey 311-0680CCT-ND R21, R22, R23, R24

2 2.32k R-US_R0805 0805 Digikey 311-2321CCT-ND R41, R42

2 1k R-US_R0805 0805 Digikey 311-1001CCT-ND R43, R100

XXXIII

Appendix E – MCU I/0 Configuration

MCU 48 I/O pins: 4 pins: RS232 Interface 5 pins: Mode DIP Switches 5 pins: Channel DIP Switches 6 pins: Unit ID DIP Switches 2 pins: TRF6900 RxD and LockDet 6 pins: TRF6900 Mode, Standby, RxD, CLK, Data, Strobe 8 pins: General Output/Debug 8 pins: General Input/Control 1 pin: RS232 Transceiver Standby 1 pin: General Buffer Standby 2 pins: LED Control This requires: 1 - RS232 3V Transceiver (SN75LV4737A) 2 - 8-bit Buffers (SN74ALVCH244) 16 - DIP Switches (CHS-08B1) 1 - 21 pin (at least) off-board connector The breakdown for the MCU ports is as follows: Port: MCU p#: Cn1 p#: OBC p#: Dir: Use: ------- ------- ------- ------- ------- ------------------------------------ 1 0 U3.7 J4.21 Input RS232 - CTS 1 U3.9 J4.20 Input RS232 - RxD 2 U3.12 J4.19 Output RS232 - RTS 3 U3.14 J4.18 Output RS232 - TxD 4 U5.2 J4.9 Output General 5 U5.3 J4.8 Input General 6 U5.4 J4.7 Output General 7 U5.5 J4.6 Input General 2 0 U1.28 NA Input TRF6900 Receive_Data 1 U1.11 NA Input TRF6900 Lock_Detect 2 U5.6 J4.5 Output General 3 U5.7 J4.4 Input General 4 U5.8 J4.3 Output General 5 U5.9 J4.2 Input General 6 NA NA Output Green LED - Active Hi 7 NA NA Output Yellow LED - Active Hi 3 0 S3.1 NA Input Mode 0 1 S3.2 NA Input Mode 1 2 S3.3 NA Input Mode 2 3 S3.4 NA Input Mode 3 4 S3.5 NA Input Mode 4 5 S3.6 NA Input Channel 0 6 S2.1 NA Input Channel 1 7 S2.2 NA Input Channel 2 4 0 S2.3 NA Input Channel 3 1 S2.4 NA Input Channel 4 2 S2.5 NA Input Unit ID 0 3 S2.6 NA Input Unit ID 1 4 S2.7 NA Input Unit ID 2 5 S2.8 NA Input Unit ID 3 6 S2.9 NA Input Unit ID 4 7 S2.10 NA Input Unit ID 5

XXXIV

5 0 U3.23 NA Output RS232 Transceiver Standby (Standby Hi) 1 U4.1 NA Output General Buffer Standby (Standby Hi) 2 U1.27 NA Output TRF6900 Program_Data 3 U1.26 NA Output TRF6900 Program_Clock 4 U1.25 NA Output TRF6900 Program_Strobe 5 U1.17 NA Output TRF6900 Mode 6 U1.16 NA Output TRF6900 Standby_N 7 U1.19 NA Output TRF6900 Transmit_Data 6 0 U4.9 J4.10 Input General 1 U4.8 J4.11 Output General 2 U4.7 J4.12 Input General 3 U4.2 J4.17 Output General 4 U4.3 J4.16 Input General 5 U4.4 J4.15 Output General 6 U4.5 J4.14 Input General 7 U4.6 J4.13 Output General