university of michigan electrical engineering and computer science 1 polymorphic pipeline array: a...

University of MichiganElectrical Engineering and Computer Science1

Polymorphic Pipeline Array: A Flexible Multicore Accelerator with Virtualized Execution

for Mobile Multimedia Applications

Hyunchul Park1, Yongjun Park2, Scott Mahlke2

December 12, 2009

Texas Instruments Inc.1

University of Michigan, Ann Arbor 2

University of MichiganElectrical Engineering and Computer Science

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• Multimedia applications have high performance, cost, energy demands– High-quality video– Flash animation

• Clear need for application and domain-specific hardware

Introduction

24 fps min.

Fram

es/s

ecMPEG-4 Decoder

Cell-phone battery life(hours)

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energyperformance


Convergence of Functionalities

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Anatomy of iPhone

HD TV decoder

Video Recording

Video Editing

3D Rendering

4G Wireless

Advanced Image

Processing

Convergence of functionalities demands a flexible solutionApplications have different characteristics


ASIC Alternatives

General PurposeProcessors

DSPs

Efficiency, Performance

Fle

xibi

lity

ASICs

Domain specificEfficiency

Somewhat programmable

What’s the right way to support multimedia applications ?

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Coarse-Grained Reconfigurable Architecture (CGRA)

• Array of PEs connected in a mesh-like interconnect• High throughput, low cost/power with distributed hardware• High flexibility with dynamic reconfiguration• Morphosys, SiliconHive, ADRES


Execution Model of CGRAs

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for ( …… ) {

}

time

Host

CGRA

• Modulo scheduling exploits loop level parallelism


Large Scale CGRA

• Need for higher performance– Higher resolution/more detail video– Multiple concurrent applications support

• Increasing technology allows more resources available

Loop 0 Loop 0 Loop 0Loop 0

Loop 1

Loop 2

Loop 3

Task 0 Task 1 Task 2 Task 3 Task 4Loop 0


Streaming Execution Model• Streaming property

– Packet of data goes through independent tasks

• Partition tasks into stages– Map each stage onto different

hardware• Pipeline parallelism

– Pipeline the outermost loop

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Insights

• Multimedia applications rich both in ILP/pipeline parallelism– Not mutually exclusive, cooperatively enhance performance

• Resource requirement varies– Statically / dynamically

• Need a flexible execution model– Exploiting both types of parallelism– Resource allocation based on computation requirement– Dynamically adapt to computation variance

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Polymorphic Pipeline Array

• Multi-core accelerator : each 2x2 array becomes a processor• Cores can be combined to form a larger logical core• Exploit both coarse-grain and fine-grain pipeline parallelism• No dynamic routing logic: all communications statically generated

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Core Core Core Core

Core Core Core Core

Logical Core

Logical Core

Logical Core


Execution Model

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• Pipeline outermost loop

ST 0 ST 1 ST 2 ST 3

ST 0

ST 1

ST 2

ST 3


Execution Model

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• Pipeline outermost loop• Compute intensive stage

– Assign more resources– Modulo scheduling

ST 0

ST 1

ST 2

ST 3

ST 0 ST 1 ST 2 ST 3


Execution Model

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ST 0

ST 1

ST 2

ST 3

ST 0 ST 1 ST 2

ST 3

• Pipeline outermost loop• Compute intensive stage

– Assign more resources– Modulo scheduling


Partitioning of PPA

• Static partitioning– Schedules can be optimized– Computation variance leads to low utilization

• Dynamic partitioning– Adjust core assignment at run-time– Adapt to computation variance, but some overhead

• How to support dynamic partitioning– Multiple schedules: code bloat– Unified schedule targeting multiple sub-arrays (virtualization)

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Virtualized Modulo Scheduling

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• One binary that can run in multiple targets– Part of code migrate to

neighboring core– No rescheduling

• Challenges– Avoid resource conflict – Enforce multiple modulo

constraints– Inter-core communication

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A B0 1

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Multi-level Modulo Constraints

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time F0 F1 F2 F3

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II = 4

II =

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II =

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= 2


Inter-core Communication

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Direct RF connection


VMS Summary

• Edge-centric Modulo Scheduling [PACT’08] with virtualization support

• Generate a unified schedule– Schedule for the smallest array, then expanded

• Multi-level modulo constraints enforced– Avoid resource conflict when expanded– Apply to computation/routing/registers

• Register transfer operations for inter-core communications– Enabled only when expanded

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Evaluation of PPA

• Exploiting both types of parallelism in AAC• Dynamic partitioning overhead

– 13% overhead for single-core schedule, runtime overhead

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CGRA static dyn static dyn static dyn static dyn static dyn4 cores 4 cores 5 cores 6 cores 7 cores 8 cores

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Where PPA stands

24 fps min.

Fram

es/s

ec

MPEG-4 Decoder

Cell-phone battery life(hours)

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energyperformance


Questions?

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