Upgrading the STAR TPC FEE(R & D Phase)

Fred Bieser

R&D Program Goals

Develop solid technical approach for upgrading TPC (and FTPC) readout speed and data quality

Basis for eventual upgrade implementation (in tandem with DAQ) to support >1kHz rate of event presentation to level 3

History

• EOS @ Bevatron (1990)– 15K channels; 100/sec SCA + ext. ADCs

• NA49 @ CERN SPS (1995)– 186K channels; 16/sec SCA/ADC

• STAR @ RHIC (1998)– 137K channels; 100/sec SCA/ADC + Gigabit links

The Future

• ALICE @ LHC (2007)– 570K channels, 200 central events/sec

• STAR (after upgrade)– 137K channels, 1000 central events/sec

Bottlenecks, shortcomings

• Analog store + digitization (SCA/ADC)

• Discontinuous sampling

• Off-chamber zero suppression

• Spatial ‘noise’

analog sampledigitize

sub. pedestalsuppress 0s

serializesend to DAQ

preampshaper

Desired Improvements

• Higher Event Rate to Level 3 (>1KHz)

• Continuous Waveform Sampling

• Digital filtering (better shaping)

• Zero suppression before Xmission to DAQ

digitizeadj. baseline

serializesend to DAQ

suppress 0spreampshaper

ALTRO Features

• 20MHz/10bit ADC per channel (4mW)

• 2 stages of adaptive baseline restoration

• Tunable pulse shaping (tail corrections)

• Continuous Pipelined Digital Processing/Formatting

• Output = 4x faster & 4x wider than inputs

R & D Plan

Year 1:

• Develop science-driven requirements

• Evaluate technical approaches

(e.g. ALTRO chip developed for ALICE TPC)

• Learn about care and feeding of ALTRO chip

• Define topology of FEE on a STAR TPC Sector

• Define interface to DAQ (both physical and philosophical)

R & D Plan

Year 2:• Design FEE card and Readout Controller

• Develop STAR-specific algorithms and parameters used within the ALTRO chip

• Construct several prototype FEE cards and interface to DAQ

• Perform detailed testing/evaluation of prototypes using spare TPC sector

Costs

• Major effort = contributed time (free) (myself + jay + other RNC members)

• 50% of one post-doc

• Part of a junior engineer in second year

• Travel (BNL,CERN)

• prototype PCBs

• Costs: year 1 $80K

year 2 $167K

Summary

• The goal of this R&D proposal is to prepare for upgrading the performance of the TPC electronics.

• We are doing preliminary work now and are ready to rapidly move ahead once we are approved.