Annual Review – Poster Session March 24, 2004 1

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US CMS HCAL Front End Electronics

US CMS HCAL Front End US CMS HCAL Front End ElectronicsElectronics

US CMSFront End Electronics

Theresa Shaw, Scott Holm, Sergey Los, Claudio Rivetta, Anatoly Ronzhin, Julie Whitmore

(FNAL)

Annual Review – Poster Session March 24, 2004 2

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LCMS Hadron CalorimeterCMS CMS HadronHadron CalorimeterCalorimeter

HCAL: Barrel, Endcap, Outer,and Forward Calorimeters

Annual Review – Poster Session March 24, 2004 3

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HCAL: The two HBs have been Completed

HCAL: The two HCAL: The two HBsHBs have have been Completedbeen Completed

Ready for installation of readout boxes and burn in 2004. Insertion in vacuum tank: Jan 2005.

Annual Review – Poster Session March 24, 2004 4

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HCAL: The two HEs have been Completed

HCAL: The two HCAL: The two HEsHEs have have been Completedbeen Completed

HE+1 HE-1

Annual Review – Poster Session March 24, 2004 5

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LHCAL :HF Fibre InsertionHCAL :HF HCAL :HF FibreFibre InsertionInsertion

All 36 wedges complete by 15 Nov 2003 (instead of Apr 2004 target).

Cylindrical support structure + table manufactured in Iran and on schedule.

Mount HF wedges on final support structure in 2004.

2 wedges tested in beam (summer 2003).

Annual Review – Poster Session March 24, 2004 6

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HCAL FE/DAQ Electronics

HCAL FE/DAQ HCAL FE/DAQ ElectronicsElectronics

QIE

QIE

QIE

QIE

QIE

QIE

CC

AC

CA

CC

A

TXTX

Shield Wall

CPU

DCC

HTR

HTR

HTR

HTR

HTR

HTR

LEVEL 1TRIGGER

TTC

DDU/FED

HPD

CONTROL MODULE

FE READOUTMODULE

VR

1600 Mbit/s

L1 Accept

1 Gbit/s 16 1600Mbit/s fiber perHTR

18 HTRs per HCALReadout Crate

Annual Review – Poster Session March 24, 2004 7

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L6 Channel FE Board6 Channel FE Board6 Channel FE Board

Custom ASICsQIE (6 / board)FNAL ASIC

CCA (3 / board)FNAL ASIC

Low Voltage Regulator(2 / board) CERN

Developed in rad hard process

Gigabit OpticalLink [GOL]

(2 / board) CERNDeveloped in

rad hard process

Annual Review – Poster Session March 24, 2004 8

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LQIE DescriptionQIE DescriptionQIE Description

QIE – FNAL developed ASICCharge Integrator Encoder4 stage pipelined device (25ns per stage)

charge collectionsettlingreadoutreset

Inverting (HPDs) and Non-inverting (PMTs) InputsInternal non-linear Flash ADCOutputs

5 bit mantissa2 bit range exponent2 bit Cap ID

Annual Review – Poster Session March 24, 2004 9

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LQIE SpecificationQIE SpecificationQIE Specification

QIE Design Specifications• Clock > 40 MHz• Must accept both polarities of charge• Charge sensitivity of lowest range –

1fC/LSB(inverting-input)• In Calibration Mode 1/3 fC/LSB

• Maximum Charge – 9670 fC/25ns(inverting-input)

• 4500 electrons rms noise• FADC Differential Non-Linearity < .05 LSBs

Annual Review – Poster Session March 24, 2004 10

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Channel Control ASIC FNAL ASIC

Channel Control ASIC Channel Control ASIC FNAL ASICFNAL ASIC

The CCA provides the following functions:• The processing and synchronization of data from two QIEs, • The provision of phase-adjusted QIE clocking signals to run

the QIE charge integrator and Flash ADC,• Checking of the accuracy of the Capacitor IDs, the Cap IDs

from different QIEs should be in synchronization,• The ability to force the QIE to use a given range,• The ability to set Pedestal DAC values, • The ability to issue a test pulse trigger,• The provision of event synchronization checks – a crossing

counter will be implemented and checked for accuracy with every beam turn marker,

• The ability to send a known pattern to the serial optic link, • The ability to “reset” the QIE at a known and determined time, • And, the ability to send and report on any detected errors at a

known and determined time.

Annual Review – Poster Session March 24, 2004 11

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LCivil Engineering and MagnetCivil Engineering and MagnetCivil Engineering and Magnet

Annual Review – Poster Session March 24, 2004 12

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Outstanding Surface Works: SX5, SDX5 and SCX5

Outstanding Surface Works: Outstanding Surface Works: SX5, SDX5 and SCX5SX5, SDX5 and SCX5

Annual Review – Poster Session March 24, 2004 13

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Construction of 2nd Phase SX5 has Started

Construction of 2nd Construction of 2nd Phase SX5 has StartedPhase SX5 has Started

Extension of SX slab has started

Crown of shaft is being removed

Annual Review – Poster Session March 24, 2004 14

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UXC5 Steel Reinforcement of Floor

UXC5 Steel UXC5 Steel Reinforcement of FloorReinforcement of Floor

Annual Review – Poster Session March 24, 2004 15

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LGOL – CERN ASICGOL GOL –– CERN ASICCERN ASIC

Gigabit Optical Link (GOL) Configuration• 32 bit mode; 1.6 Gb/s; Gigabit Ethernet Protocol• FNAL produced the GOL ASIC tester

Annual Review – Poster Session March 24, 2004 16

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Clock, Control and Monitor Module

Clock, Control and Clock, Control and Monitor ModuleMonitor Module

Annual Review – Poster Session March 24, 2004 17

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CMS HCAL TIMING & CONTROL MODULE(CCM)

CMS HCAL TIMING & CONTROL CMS HCAL TIMING & CONTROL MODULE(CCM)MODULE(CCM)

CCM “CLOCK – CONTROL – MONITOR”CCM - FOUR Board Module that resides in

the CMS HCAL Readout Box(RBX)Interface between Front End Boards

and Main Control SystemMAIN CONTROL

SYSTEM

Custom SERIAL 1:18 HUB

CommercialSERIAL 1:32 HUB

CCM Front End BoardFront End BoardFront End Board

Front End BoardFront End BoardFront End Board

QIE CCA GOLQIE CCA GOLQIE CCA GOL

QIE CCA GOLQIE CCA GOLQIE CCA GOL

CMS HCAL Readout Box(RBX)

Control Board

Monitor Board

Clock Board

Clock Board

Annual Review – Poster Session March 24, 2004 18

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LRBX Readout ModuleRBX Readout ModuleRBX Readout Module

• The readout module (RM) integrates the HPD, front end electronics, and digital optical drivers.

Electronics cards

HPD MountHV

Interface Card

ODU

Annual Review – Poster Session March 24, 2004 19

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LHCAL HE RBX with 4 RMsHCAL HE RBX with 4 HCAL HE RBX with 4 RMsRMs

Annual Review – Poster Session March 24, 2004 20

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LHCAL Channel CountHCAL Channel CountHCAL Channel Count

624485761728HB/HE overlap

352819226430729072Tot

67248485761728HF

87636727682160HO

69672485761728HE (pure)

66036485761728HB(pure)

TotalFibers

CalibFiber

TTCrxFibers

DataFibers

ChannelCount

Annual Review – Poster Session March 24, 2004 21

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LOptical Data/ControlOptical Data/ControlOptical Data/Control

1.6 Gbps Digital Readout~3500 Data + TTC/Calibration Links

Annual Review – Poster Session March 24, 2004 22

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LOptical ConnectorsOptical ConnectorsOptical Connectors

•MTP /MPO •Multi-fiber•RMs/HTRs/Patch panels•Shutters –Laser safety

• LC / ST•Single-fiber•CCM/CalibPatch panels•Shutters (LC) Laser safety

Annual Review – Poster Session March 24, 2004 23

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L1.6 Gbps Optical Link1.6 1.6 GbpsGbps Optical LinkOptical Link

Annual Review – Poster Session March 24, 2004 24

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HE, HB RBXs at CERN Testbeam 03

HE, HB HE, HB RBXsRBXs at CERN at CERN TestbeamTestbeam 0303

Annual Review – Poster Session March 24, 2004 25

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LHB Wire Source CalibrationHB Wire Source Calibration

There is no big difference in the gains over 3 months running

Annual Review – Poster Session March 24, 2004 26

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Pedestals - HB 144 channels

Pedestals Pedestals -- HB 144 HB 144 channelschannels

average

dispersionped(i) -ave

rms

Annual Review – Poster Session March 24, 2004 27

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Dynamic Range and Pulse Shape

Dynamic Range and Pulse Dynamic Range and Pulse ShapeShape

Signal fraction in 1 timeslice0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8

Sig

nal

fra

ctio

n in

2 t

imes

lices

0.74

0.76

0.78

0.8

0.82

0.84

0.86

0.88

0.9

Signal fraction

13

19

1 25

e 30 GeV

1 2 3 4 5

6 7 8 9 10

11 12 13 14 15

16 17 18 19 20

2522 23 2421

30 GeV Electrons

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Annual Review – Poster Session March 24, 2004 28

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LUS CMS SummaryUS CMS SummaryUS CMS Summary

CMS HCAL FE Electronics has entered the production stage.

Testbeam Run scheduled this summer at CERN using production Hardware.