user’s guide „logic - analyze“ for pc logic analyzer · 2020. 8. 29. · position the...

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User’s Guide

„Logic - Analyze“

for

PC Logic Analyzer

Copyright © QUANCOM Informationssysteme GmbH

All specification in this manual was arranged after careful check, and it is not considered as any war-ranty of product properties. QUANCOM shall not be responsible for any errors or omissions containedin this user’s manual, and reserves the right to make changes without notice. Passing on and duplica-tion of this manual and the utilisation of its contents as well as the software belonging to the productare permitted only with written permission by QUANCOM.

Wesseling, August 2004 – Version 2.11

Overview

PC-Logic Analyser

Table of contents

1 Overview ..................................................................................................... 6

1.1 Introduction .......................................................................................................................... 6

1.2 Our experience is your profit.............................................................................................. 6

1.3 Customer Communication.................................................................................................. 6

1.4 Changes in this manual and software updates ................................................................ 7

1.5 Extend of delivery ................................................................................................................ 7

2 Installation procedures.............................................................................. 8

2.1 System requirements .......................................................................................................... 8

2.2 Safety precautions............................................................................................................... 8

2.3 Installing the board.............................................................................................................. 9

2.4 PCI Interface board for the logic Analyser ...................................................................... 10

2.5 Jumper settings ................................................................................................................. 10

2.5.1 Memory or I/O-port transfer selection............................................................................................... 10

2.5.2 Selection 5V / 3,3V Motherboard...................................................................................................... 11

2.6 Connecting the Logic Analyser to the PC interface....................................................... 11

3 Technical Hardware Description............................................................. 12

3.1 General................................................................................................................................ 12

3.2 Theory of operation ........................................................................................................... 15

3.3 Technical Data.................................................................................................................... 16

3.3.1 Hardware ........................................................................................................................................... 16

3.3.2 Software............................................................................................................................................. 17

3.4 External clock..................................................................................................................... 19

3.5 Trigger-logic ....................................................................................................................... 20

3.6 Signals at the input-sockets ............................................................................................. 21

4 The software Logic Analyze.................................................................... 22

4.1 Installing the Logic Analyse Software............................................................................. 22

4.2 Introducing the software................................................................................................... 27

4.2.1 Software-overview............................................................................................................................. 27

Overview

Description

4.2.2 Using the Software ............................................................................................................................ 29

4.3 Menus of the software.......................................................................................................30

4.3.1 The File-menu.................................................................................................................................... 30

4.3.2 The Edit-menu ................................................................................................................................... 32

4.3.3 The Set-up menu................................................................................................................................ 34

4.3.4 The Run-Menu................................................................................................................................... 39

4.3.5 The Cursor/Marker-menu .................................................................................................................. 40

4.3.6 The Window-menu ............................................................................................................................ 41

4.3.7 The Help-Menu.................................................................................................................................. 42

4.3.8 Quick-start ......................................................................................................................................... 43

4.4 Keyboard-shortcuts........................................................................................................... 44

5 Measurement examples........................................................................... 46

5.1.1 Checking connections ........................................................................................................................ 47

5.1.2 Defining trigger-conditions................................................................................................................ 48

5.1.3 Defining State-channels..................................................................................................................... 49

5.1.4 Using the zoom.................................................................................................................................. 52

5.1.5 Hiding unused channels ..................................................................................................................... 53

5.2 Measurement example: synchronous counter ............................................................... 54

5.2.1 Measuring time .................................................................................................................................. 55

5.3 Measurement example: Handshake parallel printer-port .............................................. 57

5.3.1 Printer-communications..................................................................................................................... 58

5.3.2 Comparing printer-speed using copy or print Command................................................................... 59

5.3.3 Comparing printer-speed with fast and slow CPU............................................................................. 61

5.4 Measurement example: IBM-PC bus................................................................................ 62

6 Annex ........................................................................................................ 64

6.1 Customer Communication and Help................................................................................ 64

6.2 Technical support form..................................................................................................... 67

6.3 Hardware and Software configuration form.................................................................... 68

6.4 Documentation Comment Form ....................................................................................... 69

Overview

PC-Logic Analyser

Overview

Description

1 Overview

1.1 IntroductionWe congratulate you on buying the QUANCOM high quality measurement and ana-lysing system. You have chosen a product which attributes and functions show thelatest updates of technology.The following special attributes are included:

• Easy to use with PC- Windows Program

• Fast acquisition rate of up to 400MS/s

• 64 kBit internal buffer for each channel

• Short cabling through external acquisition module

• Lots of variations for trigger-events

• Software support for Windows XP / 2000 / NT and ME / 98 with Logic Analyse

1.2 Our experience is your profitQUANCOM is specialised in development of hard- and software. QUANCOM hasbecome one of the leading suppliers of measuring and automation technology in-dustry. At its design centres QUANCOM has developed an impressive range ofproducts.

1.3 Customer CommunicationQUANCOM wants to receive your comments on our products and manuals. Weare interested in the applications you develop with our products, and we want to helpyou if you have got any problems with them. For easy contacting, this manual con-tains comment and configuration forms for you to complete, which are in chapter 6.1“Customer Communication and Help” at the end of this manual.

Overview

PC-Logic Analyser

1.4 Changes in this manual and software updatesQUANCOM - products are marked out by their constant further development. Youcan watch all the actual information of changes in the README-file on the installationdisk or CD. You can always get more information and free software updates on ourinternet website.

(WWW.QUANCOM.DE)

1.5 Extend of delivery

• External Logic Analyser with integrated measurement amplifier

• PCI interface for the Logic Analyser

• Two 17 pin measurement cable (16 pin data and one for GND)

• 1.5 metres Connection cable to connect the Logic Analyser with the interface

• User‘s manual

• Measurement software Logic Analyse on CD

If a component is missing please contact your dealer. QUANCOM reserves the rightto change the extent of delivery without a preliminary announcement.

Installation procedures

Description

2 Installation procedures

2.1 System requirements• Personal computer: The QUANCOM boards are as-

signed to operate in IBM-AT compatible computers with80X86 or compatible. (i.e. 80386 / 80486 / Pentium )

• Your computer must have a PCI bus.

You can find more information in chapter 3, “Technical Hardware Description”.

2.2 Safety precautionsFor the sake of your security and a safe function of your new QUANCOM boardplease take notice of the following advices:

• Please unplug the computer before opening it.

• Computer motherboards and components contain very delicate integrated circuit(IC) chips. You have to obey some precautions whenever you work on your com-puter to protect them against damage from static electricity. Use a grounded wriststrap before handling computer components. If you don’t have one, touch both ofyour hands to a safely-grounded object or to a metal object, for example thepower supply case.

• Take components by the edges and try not to touch the integrated circuit chips,leads or circuitry.

• Place components on a grounded anti-static pad or on the bag that was sent withthe component whenever the components are separated from the system.

! Attention ! Modifications, made at the device without expressing permission ofQUANCOM, lead to the loss of warranty!


PC-Logic Analyser

2.3 Installing the board

CAUTION: Always turn the system power off and remove the power cord fromthe wall before installing or removing any device. Always observestatic electricity precautions. See Safety precautions“ in chapter 2.2for further information

1. Switch off the computer and the connected devices and unplug them.

Warning: Static electricity can destroy your computer and the board!

Discharge yourself as described in chapter 2.2 Safety precautions

2. To open your PC you have to unscrew thescrews on the back of the case with a screwdriver. Then you can pull the cover forwards. Ifnecessary you must remove impeding cables.

3. The slots are positioned at the rear side ofyour computer. The positions of unused slots arecovered by a small metal plate. Search for a freeslot, detach its holding screw and remove thesmall metal plate belonging to it.

4. Position the extension card into a free slot. Pay attention that the card is set firmlyinto the slot.

5. Fasten the board with the screw as shown in the picture above.

6. Close the cover of your computer. Cables, that you detached during the installa-tion, should now be reconnected.

7. Connect the cable of the board into the slot belonging to it.


Description

2.4 PCI Interface board for the logic Analyser

LatticeiM4A3-256/

128JP2JP1

SN

74LS

245N

SN

74LS

245N

SN

74LS

245N

SN

74LS

245N

JP3

Con

n1

2.5 Jumper settings

2.5.1 Memory or I/O-port transfer selectionWith JP3 you may choose the way how data to and from the board will be transfered.You may choose between memory-mode or I/O-port transfers. The factory setting istransfer in memory-mode as this is the fastest way to transfer data.

Mode JP3

I/O transfer

Memory Modetransfer(Default)


PC-Logic Analyser

2.5.2 Selection 5V / 3,3V Motherboard

from+3,3V

PCI-Bus

JP2Selection +3,3V supply

JP1Selection +5V supply

fromVCC

PCI-Bus

from+5V

PCI-Bus

frominternal+3,3V

generation

Configuration for +5V supply with 5V-PCI-Bus (default)

JP1 JP2

Configuration for 3.3V supply with 3.3V-PCI-Bus

JP1 JP2

2.6 Connecting the Logic Analyser to the PC interface

PC

LA interface-board

37pin DSUBcable

LogicAnalyser

LED

Technical Hardware Description

Description

3 Technical Hardware Description

3.1 GeneralThe QUANCOM® logic analysers are external devices and work perfectly with theWindows-software, which completes a professional logic analyser system. Short sig-nal paths are possible through the external acquisition module, which samples andstores the acquired data as long as the PC fetches them or the buffer is full. The ex-ternal module is connected through an round cable with the interface card which re-ceives the finished data.

Logic Analyse is able to display the sampled data as State- or Timing-channels.You may print, load or save your sampled data and send the data to other develop-ers via e-mail. Only the software Logic Analyse is needed. The Software itself isable to run without any logic analyser hardware and is freely available as a full-version from our website.

Do you need 200MSamples/s or 400MSamples/s?The supplied signals are sampled with 200 or 400 millions of samples per second.That means that each 5ns (2.5ns with 400MSamples) data is acquired. For mostmeasurements you do not need these high sample rates for it is more important toinspect address-/data-busses and control-signals of microprocessors. The main rea-son for LA’s is to acquire and analyse the dependencies of the address-/data-bussesand control-signals. With these logic analysers you may analyse signals with a reso-lution of 5ns or 2.5ns which is even enough for analysing PC-busses.

Logic analysing in commonDid you ever try to debug digital boards with an oscilloscope? If it is so, you knowhow difficult this job can be, even with a 4 channel scope.You have to use a scope with 2 channels or more to debug with a scope, otherwiseyou will not see multiple channels or time-depending signals. But even when you areusing a 4 channel scope debugging a 8-bit data-bus it is a difficult task.Logic analysers or short LA’s were developed to solve this problem. This LA’ s can’tmeasure analogue signals, but they provide multiple channel digital inputs at thesame time.2 characteristics are important for every LA: the number of channels and the maxi-mum sample rate.


PC-Logic Analyser

Number of channelsWhich number of channels you need to solve your problem depends to the problemitself:You need at least 8 channels for the data-bus and at least another 8 channels for theaddress-bus to develop microprocessor- or microcontroller-boards. Furthermore youneed several channels for the control-signals of the processor. A LA with 32 channelsis far enough for the development of a board for an 8-Bit processor. But if you want todevelop a board for a 32-Bit processor, you have to use at least 80 channels be-cause of the 32 data- and address-bits and several control signals.The question of the number of channels you need may not be easily answered with-out thinking about future developments too.For common TTL-layouts or 8-Bit microprocessor developments a 32 channel LA isfar enough.

Sample RateAnother main aspect is the maximum sample rate of the LA. The sample rate de-scribes how many samples of all channels are sampled per second. With samplerates of 200 MSamples/s or 400 MSamples/s 200 million or 400 million samples persecond are done. This factor also defines the maximum resolution of the signal. With400 MSamples/s the signal may change up to every 2.5ns without loosing a singlestate of the signal. The resolution of a LA with 200 MSamples/s is 5ns (1/f=T,f=200MHz => T=1/200MHz=20*10-9 s = 5ns). That means that every 2.5ns or 5ns asample of each channel is taken and stored in an ultra fast RAM.To analyse PC-slot cards you need at least a sample rate of 33MS/s (PCI-Bus has33 MHz). For a chip-select inside a PC is even longer than 1 cycle, you are able todo multiple samples for each chip-select which is even enough for debugging PC-cards.


Description

Logic analysers from QUANCOMYou may choose out of the following logic analysers we have developed:PCLOG200/32, PCLOG400/64 and PCLOG400/96.The following table shows the characteristics of them:

Model Channels at200 MSamples/S

Channels at400 MSamples/S

PCLOG200/32 32 -PCLOG400/64 64 32PCLOG400/96 96 48

Each model is designed to generate trigger-events out of all 32/64/96 channels. Eachchannel is buffered with 64 kBit ultra fast RAM. All logic analysing systems consistsin an external module in combination with a PCI-interface card for the PC and thesoftware Logic Analyse (for Windows XP/2k/NT and Windows ME/98). Input andoutput (keyboard, display, printer and so on) is done from the PC. Because of this di-vision of tasks the logic analyser itself only costs a part of what others cost whichcombine every task in one module.Another main reason for this task division is that the PC with the software has muchmore usability to offer than just an external module. You gain all advantages of thecommon used Microsoft Windows GUI, including controlling the LA with mouse,loading and saving data, printing timing diagrams, using clipboard, zooming in andout and defining trigger-events. With loading and saving of the sampled data youmay send your data to other developers via network, email or simple floppy disks.The only needed thing for the other developers is the software Logic Analyse whichmay be downloaded from our website as demo. This feature allows team-working-logic-analysing from all over the world.


PC-Logic Analyser

3.2 Theory of operationHow the hardware worksThe external measurement module samples every data into the internal memory.This buffer is large enough to sample even complete routines of a microprocessor.But to solve problems you need to see what happened before and after the error oc-curs. For that the user can define from what time on the logic analyser begins withthe sampling of data. For each channel you can set either “1” (high), “0” (low) or “X”(don’t care) as trigger condition. To trigger on even more complicated situations youmay set the minimum or maximum time the signal is at that level or trigger to a de-fined slope of that signal. You also can define if this trigger-event is raised with it’sfirst occurrence or after the up to 255th occurrence.

Example: You connect an 8-Bit counter to the LA and set the connected channels totrigger with 0 and the unused channels to X (don’t care). The sampling will then bestarted with counter-state 0.

The point of time where sampling of data is started (where all data signals havestates as defined with the trigger-settings) is called trigger-event.But now we only see what happens after the error might occur, but we need to seewhat happens before this error. We implemented the pretrigger method to sample thedata before the error starts. You can define how much of the sampling-buffer will beused to store data before the measurement is triggered with this function. Values of0/8, 1/8, 2/8...7/8 are possible and divide the data-buffer of 65535 bits into data-before trigger and data-after trigger parts. If you set pre-trigger to 1/8 the buffer is di-vided into 8192 bits before trigger and 57344 bits after the trigger-event. An error canbe analysed very comfortable with this division.

Example:A device under test produces an error at a known condition. You set-up the trigger-event to this condition and set the pre- trigger to 1/8. After sampling you will see theerror at the trigger-point and the data before as conditions which might lead to the er-ror. The data after trigger-event is surely show too.


Description

3.3 Technical Data

3.3.1 Hardware• External Measurement module• 32 Bit PCI-interface card

Sample rates Sample rates of 400MHz*, 200MHz, 100MHz, 50MHz, 25 MHz, 10MHz, 5 MHz, 2.5 MHz, 1 MHz, 500 kHz, 250 kHz, 100 kHz, 50 kHz,25 kHz, 10 kHz, 5 kHz, 2.5 kHz, 1 kHz, 500 Hz, 250Hz

Channel + Buffer 32/64*/96* TTL-Inputs (65536 Bit/Channel)( * depending to the model )

Trigger (all channel) Trigger with 0 (low), 1 (high), X (don’t care)

Pre-trigger 0/8, 1/8, 2/8, 3/8, 4/8, 5/8, 6/8, 7/8 before trigger eventAt 200 MHz 0/8, 2/8, 4/8, 6/8At 400 MHz 0/8, 4/8

External Clock Sampling with positive and/or negative slope:Clockstate0 = K0Clockstate1 = K0 * K1Clockstate2 = K0 * K3Clockstate3 = K0 * K1 * K2Clockstate4 = K0 * K1 * K3Clockstate5 = K0 * K1 * K2 * K3Clockstate6 = K0 + K1Clockstate7 = K0 + K1 + K2Clockstate8 = K2 * ( K0 + K1 )Clockstate9 = K2 * K3 * ( K0 + K1 )Clockstate10 = K3 * ( K0 + K1 )Clockstate11 = K3 * ( K0 + K1 + K2 )

DimensionsLogic Analyser 230 mm * 208 mm / (23" * 20,8").PC Interface 124 mm * 85 mm / (12,4“ * 8,5“)


PC-Logic Analyser

3.3.2 Software

Software Logic Analyse Software for Windows XP / 2000 / NT and Windows ME / 98with State/Timing view, zoom and markers for measurement.

Configuration of hardware One software-version for all Logic Analysers.

Type Version of Logic-Analyser.PCLOG200/32, PCLOG400/64, PCLOG400/96

Hardware 32-Bit PCI input / output Interface to PC.

3.3.2.1 File-UtilitiesSave Saving of channel names, trigger-conditions, measurement

data, and other actual settings.

Load Loading of all saved information.

Print Print to installed printers (hardcopy of screen). Multi-page-printout is possible.

Clipboard Copy actual screen-data to clipboard for further usage in otherprograms. (i.e. EXCEL, Word)

Channel-assignment Free assignment of timing-channels, assignment of Bits tostate-channels. Display state-channels in hexadecimal, deci-mal, binary, octal.

3.3.2.2 Screen-view

Zoom Adjustable Zoom with1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2, 1x, 2x, 4x, 8x, 16x, 32x,64x, 128x.

Markers Measure times with reference-line and marker-line.

View Slope Adjustable slope display.

Hold View The actual position is kept while a new sampling is done .


Description

Trigger Assign timing-channels with low, high or don't care.Trigger with state-channels with values in bin, hex, dec.

Sampling Adjustable sample-rateSample-rates of 400MHz / 200MHz to 250Hz(steps see Hardware, Sample-rates).

Snapshot (without Trigger) Begin sampling on key press.

Pre-trigger Adjustable Pre-trigger(steps see Hardware, Pre-trigger).

Signal Beep when sampling is finished.


PC-Logic Analyser

3.4 External clockThrough the generation of an external clock out of the data-signals, the logic analyseris able to sample with your applications clock and save internal memory.External clock can be generated out of the channels 0 to 3 and the trigger-conditionin a way the following table shows:

Clock-state Clock-sourceSTATE-CLOCK 0 K0STATE-CLOCK 1 K0 * K1STATE-CLOCK 2 K0 * K1 * K2STATE-CLOCK 3 K0 * K1 * K3STATE-CLOCK 4 K0 * K1 * K2 * K3STATE-CLOCK 5 K0 + K1STATE-CLOCK 6 K2 * ( K0 + K1)STATE-CLOCK 7 K3 * ( K0 + K1)STATE-CLOCK 8 K2 * K3 * ( K0 + K1)STATE-CLOCK 9 K0 + K1 + K2STATE-CLOCK 10 K3 * (K0 + K1 + K2)STATE-CLOCK 11 K0 * K3

Each of the four channels of the clock-state may be inverted separately. The gener-ated STATE-CLOCK may be combined with the trigger-condition in the followingcombinations:

Clock Description

STATE_CLOCK Clock from state-clockTrigger- condition Clock from triggerSTATE_CLOCK * trigger- condition Clock from state-clock and triggerSTATE_CLOCK + trigger-condition Clock from state-clock or trigger


Description

3.5 Trigger-logicWith the help of the built-in trigger-logic a measurement is started at predefined sig-nal conditions.

Trigger-logic

externalClock-source

Trigger-generation

Chanel0 0/1/X

Trigger OKCounter1...255

Channel31 0/1/X

t<Value

t>Value

.

.

.

.

.

.

.

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.

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.

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t

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PC-Logic Analyser

3.6 Signals at the input-sockets

1

202

19G

ND

76543210

GN

D15141312111098

1

202

19G

ND

2322212019181716

GN

D3130292827262524

The software Logic Analyze

Description

4 The software Logic Analyze

4.1 Installing the Logic Analyse Software

Attention! Please obey that you’ll need administrator-rights in order to let the in-stallation-program install and register all needed components of thelogic-analyser software.

You install the software Logic Analyze performing the following steps:

1. Start Microsoft Windows.2. Insert the supplied Logic-Analyser-CD into your CD-ROM-drive.3. Select Start -> run... from the taskbar.4. Now click on Browse...5. Now choose the file QUANCOM.EXE located in the root folder of the Logic-

Analyser installation-CD and click on open

The setup-program is now started and will show you a setup-window.


PC-Logic Analyser

1. Click on the „Next“ Button to get to next step of the installation.

2. Please read the license agreement and click on „I accept the license agreement“and then on „Next“ to proceed.


Description

3. In this window you should enter your name and your companies name. After thatyou may select if only the current user or anyone who uses this PC should beable to start the software. Commit your selection with „Next“.

4. Now you may enter the path where the software should be installed.


PC-Logic Analyser

5. Now my have to choose the kind of installation. You should choose „Complete“ toinstall the software completely. The installation will be proceeded if you click on„Next“.

6. The installation program now has collected all needed information and will copythe files after you click on “Next”.


Description

7. After all files were copied, the installation program will close. Click on “Finish” toclose the program.

After this installation process you will find a new entry in your Start-Menu called“Logic-Analyze”. To start the software simply click on “Logic-Analyze” inside thismenu entry.

QUANCOM wishes happy sampling and debugging


PC-Logic Analyser

4.2 Introducing the software

This logic analyser software is as simple as using Windows software. The user isable to do measurements with state or timing channels and define to define trigger-conditions. One of the basic-functions is saving and loading the measured data. Youare able to send your measured data to other developers via file-transfer or email orarchive your processes to backup-media with this functions.The needed software Logic-Analyze is freely available from our website as a full-version.

4.2.1 Software-overview4.2.1.1 The Menus

File Edit Setup Run Cursor/View Window Help

FileoperationsHardwaresetupPrintExit

CopyClipboard

Setupfor Trigger,Clock etc.

Setup ofView, Cursor-

movement

Windowmanagement

OverviewKeyboard

RegisterAbout

Logic-Analyze


Description

4.2.1.2 Toolbar

open file

stopsampling

start samplingw/o trigger

zoomin/out

copy title

print

help for...

new file

save file

start samplingwith trigger cut title

paste title

info

move cursor/marker

select area

findvalue

togglefullscreen

Remark: The functions for the title are only available in mode „configure fields“.

4.2.1.3 The Status-bar

Samplefrequency

Pre-Trigger

Overallsample buffer

ZoomStatus-bar withmeasurement data


PC-Logic Analyser

4.2.2 Using the Software4.2.2.1 Timing and Listing-viewSampled data may be viewed into different kind of views: Timing and Listing-view.The Timing-view allows you to analyse the time dependencies of all channels likeviewing with an oscilloscope. With this view you gain a quick overview of your meas-ured data.Within the listing-view all sampled data are displayed as table. Here you can analyseyour data clockstep-by-clockstep, which is needed if you want to see what is hap-pening during every clockstep.You can quickly change from one view to another with the window-menu.

4.2.2.2 Moving Cursor and MarkerWith the Cursor and the Marker you are able to measure the time between two posi-tions or just tag one position inside your data. To enable or move the Cursor / Markerclick on the button “move Cursor/Marker” from the toolbar. You can move the Cursorif you left-click and hold on the red-line and move the mouse to the desired position.In listing-view simply left-click on the number of clock-step you want the cursor posi-tioned at. The Marker is moved in the same manner, just the right button of themouse is used while clicking.The time or frequency between two points, position Cursor and Marker to the desiredposition and read the time or frequency between these points from the measurement-line just above the diagram to measure.

4.2.2.3 Using context-menusYou can change the name and trigger-settings of each channel using the context-menu within timing-view. Just left-click on a name of a channel and a windows pops-up within you can change the settings for this channel.

4.2.2.4 Formatting the listing-viewJust click and hold between two columns and move the width to the desired positionto change the width of a column inside the Listing-view.


Description

4.3 Menus of the software

4.3.1 The File-menuSave or print your sampled data you use the file-menu to load. The sampled data canbe saved as file to send them to other developers or to backup the data. Other de-velopers can load the saved data into a demo-version of this software to analyse thedata and helps you to solve your problems. A kind of team-development may be es-tablished for efficient and rapid development with this feature. This software does notdepend on any logic-analyser hardware and runs on every PC which meets theminimum requirements.

4.3.1.1 New fileThis function creates a new empty file. You can choose between Timing-view or inListing-view if you want to.

4.3.1.2 Open fileWith the Open-File function you can open saved data from a recent sampling.

4.3.1.3 Save fileThis function stores the sampled data, the actual settings for channel-names, trigger-conditions, sample-rates and so on in a file. If a filename is already given, the file isstored with this name, otherwise the software will prompt for a filename.


PC-Logic Analyser

4.3.1.4 Save file as...Like the function Save-file this function saves a file, but the file has to be named be-fore saving.

4.3.1.5 Printer setupWith this function you can set-up your printer

4.3.1.6 Recent filesThe last four files are shown as quick-links to open this files.

4.3.1.7 ExitThis function terminates the program.


Description

4.3.2 The Edit-menu4.3.2.1 CopyThe actual view will be copied into the clipboard and may be inserted into documentsof Microsoft Word, Excel and so on.

4.3.2.2 Edit symbolsWith the Edit-Symbols function youare able to label values of a chan-nel. This function is useful, if youwant to show the value of achannel with your desired values oryou want to see an offset to aspecial address. You may use thisfunction with all channels whichdisplay-variant is set to “bus”. If youwant to assign more than one aliasto a value you have to createanother symbol file in the Edit-Symbols dialog.

HowToDo:Press “F7” and create a file with clickingthe add-button to create symbols for achannel. After entering a name for thisnew file and selecting the type of symbolyou may click on “add” inside the symbol-frame.

You can enter an alias for your special val-ues with the dialog which is shown then.The values may be entered as ASCII(“.A”), hexadecimal (“.H”), decimal (“.D”),octal (“.O”) or binary (“.B”) values. If youenter a value-range from Value1 to Value2all values inside this range are printed as

“Alias+x”. Single signals may be shown with their alias too if you set their display-variant to “bus” and assign them a symbol-file.


PC-Logic Analyser

After defining the alias-values, you must as-sign tem to a channel.This channel my beeither a single channelor combined channels(State-channels). Sim-ply click on the name ofthe channel and selectthe new created Sym-bol-file. Symbols workbest when using themin combination with

State-channels show as bus. How to combine channels is written in chapter 4.3.3.4“Formatting fields”

4.3.2.3 Find valuesYou select Edit -> Find value or simply press “Shift + F3” to find a special value for a

channel or state-channel. You can selectthe channel to be searched, the searchmode, and the value which is searchedwith the window that is shown then. Youcan also define if the value of the channelhas to be at least, up to or exact thesearched value. A range of values maybe entered with the second value which issearched. Searching for values may bedone with hexadecimal, decimal, octal,binary or ASCII-values. After searchingforward or backward from the current po-sition is done, the Cursor or the Marker isplaced to the found-position.

4.3.2.4 Find next valueSelect Edit -> Find next or press “F3” to search another position inside your data.


Description

4.3.3 The Set-up menu4.3.3.1 Time-baseSelect Set-up -> Time-base to set-up your clock-source. At first select the source ofthe used clock, this can be internal or external from data.

You can select your fixed frequencyclock for data acquisition inside theframe for the internal timebase.Various settings are possible if youuse the external timebase. At firstselect the source of the externalclock, which may be combinations ofdifferent terms of channel 0 to chan-nel 3 and the trigger-condition. Theterm for the clock-source can be set-up with the button “set-up clock-source”. After chosing between in-ternal- or external clock-source youalso can define if the clock is usedwith rising or falling slope of the sig-nal. For external clock-sources theexpected frequency of the clock maybe entered in the field below the

slope-settings to let the software show you the correct time and frequencies. The fre-quency has to be entered as value in Hertz.

You can select differentcombinations of channel 0 tochannel 3 and invert each ofthe used channels with thewindow which is shown afterpressing this button. Themeaning of a plus-sign insidethis combinations is the logi-cal OR, while a multiply-signstands for the logical AND.


PC-Logic Analyser

4.3.3.2 Post-ProcessingThe Post-Processing menu allows you to control some activities after the sampling isdone. You can define where the Cursor / Marker is positioned and what the screenwill show.

You may choose between the following options:

� For Cursor:• Leave unchanged – Position of Cursor will not be changed.• Move to beginning – Position of Cursor will be set to the beginning of sample.• Move to end – Position of Cursor will be set to trigger-event.

� For Marker:• Leave unchanged – Position of Marker will not be changed.• Move to beginning – Position of Marker will be set to the beginning of sample.• Move to end – Position of Marker will be set to trigger-event.

� For View:• Leave unchanged – view will not be changed.• Move to beginning – view will show the beginning of sample.• Move to end – view will show the trigger-event.• Move to Cursor – view will be moved to Cursor.• Move to Marker – view will be moved to Marker.


Description

4.3.3.3 Trigger-settings

The right point of view isvery important to analyseproperly. You can definea trigger-condition out ofthe state of every chan-nel just beneath thechannel-names to set-upyour right view. You de-fine how often a rising orfalling slope of the trig-ger-condition has to oc-cur and also excludetrigger-conditions whose

duration’s are longer or shorter than a defined time with this set-up window.You can also define the pre-trigger in other words how much of the existing memorywill be used before and after the defined trigger-condition. The set-up of the pre-trigger is done in steps of 1/8. A pretrigger of 0/8 means no pretrigger memory at all.


PC-Logic Analyser

4.3.3.4 Formatting fieldsThis menu and its corresponding window can be accessed in several ways: at firstwith this menu. Another way is to left-click onto a channel-name.You can adjust the way the signal for a channel is shown with the window which willbe shown:

Signals are shown likean oscilloscope does it,just high and low lev-els.Bus-levels of the signalare shown as numbers(0/1 with single chan-nel, higher numberswith state-channels).You can assign sym-bols to the differentlevels in this view withvery preferable viewingstated address / data-

busses. Analogue – like the “Signal” setting this mode displays the levels of thechannel(s) like an oscilloscope. The main difference is that combined state-channelsare displayed with different levels of the draw line. This mode is very usable withstated signals from / to an A/D or D/A converter.For each selected viewing-mode the output format for numbers may be chosen:hexadecimal, decimal, octal, binary and ASCII are available. For stated signals withsign-digit as MSB the corresponding option may be selected to show the correct po-larity of the value. Furthermore each channel may be set-up for inverted logic, wherea logical 0 is displayed as high and the logical 1 is displayed as low. As described inchapter 4.3.2.2 “Edit symbols” you may assign different aliases for each signal.


Description

4.3.3.5 Configuring fieldsWith this window you may label each channel and “connect” your displayed channelwith its hardware input-channel. In this windows state-channels are also defined.Read the screenshot below.

Figure 1 Assignment of Channels with State-channel

The window in Figure 1 shows that each channel is “connected” to its hardware input,but it is also shown that channel 16 is a stated-channel: Signal KA0 to KA3 are com-bined to one channel.


PC-Logic Analyser

4.3.4 The Run-Menu4.3.4.1 StopThe actual measurement will be stopped if you press this button.

4.3.4.2 Run (don’t care)A new sampling will be started independently from the trigger-condition

4.3.4.3 RunA new sampling is done after the trigger-condition has become real.


Description

4.3.5 The Cursor/Marker-menu

4.3.5.1 ToolbarShows or hides the toolbar.

4.3.5.2 Status barShows or hides the status bar

4.3.5.3 View MeasurementEnables or disables the display for Cursor / Marker differences, frequencies, clock-ticks and so on.

4.3.5.4 Go toMoves view either to trigger-position, Cursor or Marker position.

4.3.5.5 Move Cursor / MarkerMoves cursor or marker either to trigger-position or marker / cursor-position.

4.3.5.6 Display POD-NamesDisplays or hides labels for physical input-names of signals.

4.3.5.7 Extend low-levelsWhen enabled, the low level is extended with a stronger line (only in Timing-view).


PC-Logic Analyser

4.3.6 The Window-menu4.3.6.1 CascadeAll opened windows are cascaded, quick switching between these windows is possi-ble for every window that is partial visible.

4.3.6.2 TileAll opened windows are tiled over the space of the main window. If many windowsare opened Windows might become unusable because of their seize. Close notneeded windows and repeat the function.

4.3.6.3 Arrange symbolsMinimised windows are shown as symbols. They are arranged when this function isexecuted.

4.3.6.4 New Timing-viewOpen a new timing view of the sampled data.

4.3.6.5 New Listing-viewOpen a new listing-view of the sampled data.

4.3.6.6 Choose windowAll opened windows are quick accessible with this function. First nine windows areaccessible with numbers from 1 to 9.


Description

4.3.7 The Help-Menu4.3.7.1 HelpClick help to open the online help to gain help.

4.3.7.2 IndexQuick access to the help-content with the index.

4.3.7.3 RegisterWe implemented a form in which you can do this task to enter your registration-data.This form can be printed, faxed or emailed to us. After we received your data, you willreceive a register-key which will unlock your software.

4.3.7.4 Enter Register codeYou can enter the key here after receiving the register-key.

4.3.7.5 About...This function shows copyright information and the software revision number whichmight be useful if you want to check an update of the software. The revision numberis also important for support questions.


PC-Logic Analyser

4.3.8 Quick-start

Set-up and startAs first steps you have to set-up and start your software as described in chapter 4.1“Installing the Logic Analyse Software”

1. Set-upSelect your version of present hardware with menu “File -> Hardware set-up”

2. New fileCreate a new file with “File -> New file” to gain access to channel assignment.

3. Channel assignmentAssign the used channels to their correspondent input-channel (Set-up -> Configurefields or F8). You may name the channels as they are connected to your hardwareunder test (may also be done later). You would also like to define the trigger-condition (clicking on the “X” after the channel name).

4. SamplingSimply click onto the “single foot”-button located at the toolbar to start sampling.Sampling is done after the trigger-condition has become real. If no data is sampled,because the trigger-condition does not become real, click onto the “double-foot” atthe toolbar and the sampling will be started independently from the trigger-condition.

5. EditingYou can edit and analyse the sampled data after sampling is done. You may exportyour screens to Word, Excel or other programs. Save your data and you do not evenneed to put the hardware under test to do further analysing (depending to the com-pleteness of tests).


Description

4.4 Keyboard-shortcuts

Key FunctionF1 HelpF2 Show State-window

Shift + F3 Find a valueF3 Find next valueF4 Scroll view to trigger-positionF5 Scroll view to CursorF6 Scroll view to MarkerF7 Show Edit-symbols-windowF8 Show Configurations-windowF9 Go to next bookmark

Shift + F9 Go to previous bookmark

Cursor left/right Scroll view up/down or left/right.Cursor up/down Scroll view 1 rows up/down

Ctrl-N Show new windowCtrl-H Hold view

Shift++/Shift+- Adjust Pre-TriggerStrg++/ Strg+- Adjust Sample-rate

Return Start sampling

Ctrl-O Open fileCtrl-S Save fileCtrl-P PrintCtrl-C Copy screen to clipboardCtrl-T Set-up trigger-conditionCtrl-Z Exit

Measurement examples

PC-Logic Analyser


Description

5 Measurement examples

On the following pages there are some sample-measurements and show somescreenshots described.Measurement example: asynchronous counterThe first example demonstrates an asynchronous counter made of an oscillator with4 MHz and a 74LS393 as clock-divider.You have to connect the output of a flip-flop with the clock-input of another flop-flopto rebuild this counter. The value of the counter is increased by one with every clock-cycle. The output-value is time-shifted between one flip-flop to the next because thiscounting and clocking is done from one flip-flop to the next. We use the logic ana-lyser to analyse this time-shift.First connect the first channel to the 4 MHz clock, the second input to the output ofthe first flip-flop, the third input to the output of the second flip-flop and so on.


PC-Logic Analyser

5.1.1 Checking connectionsWe do one sampling without waiting for a trigger-condition to check the connections(as we did not define one yet). Press the button with two feet and the sampling isstarted. The sampled data is amplified, buffered and displayed at screen. You shouldsee a picture like shown below, if one of the signals is missing check the connectionto the counter. You will detect faulty connections with either only high or only low-level at this channel.

Figure 2 untriggered measurement at asynchronous counter

As shown in figure 2 the displayed counter-position is undefined. If you want to ex-amine special counter-states without searching, you will have to define a trigger-condition with which the logic analyser will begin sampling.


Description

5.1.2 Defining trigger-conditionsYou are able to define trigger-conditions to let the sampling start with the softwareLogic-Analyse 3.0. That means that data at the input-channel is only stored after aspecial combination of signal-states occur. This occurrence is called “Trace-Point“. Indifference to an oscilloscope the logic-analyser does not only store the data after thisTrace-Point, it stores a definable amount of data into memory before the Trace-Pointis reached. This function is called “Pre-trigger”. The amount of memory, which isneeded for data before the Trace-Point is adjustable in steps of 1/8. Settings from 0/8(no pre-trigger), 1/8, 2/8,...7/8 are possible. The pre-trigger function is needed, if youwant to analyse which signal-states raises the error (you have to trigger with the er-ror-condition of course).Click on the X right beneath the channel-name to define the trigger-condition of thistrace-point. The X (level doesn’t care) changes to 0 (level must be low) and after an-other click it changes to 1 (level must be high). The combination of all channels de-fines the trigger-word.

You have to set each trigger-level to 0 to trigger with the start of the counter. Channel0 was connected to the 4 MHz clock and the further 8 channels were connected tothe outputs of the flip-flops. Each start of sampling with respect to the trigger-condition will show the same picture. You also have one fixed-point inside your sam-pled data to which you can switch. You might need to examine every of the 64 kBit ofmemory which was filled during sampling without this fixed-point.In accordance to the settings told above, you also may trigger with all channels set to1 which will show the restart of counting just before the trace-point. Otherwise the re-start will be shown directly after the trace-point.


PC-Logic Analyser

5.1.3 Defining State-channelsYou probably want to know what number does the counter count, because the it“counts” clock-events. But it is quite difficult to translate between the channel-display(each channel shows high or low-state) and a numerical value. We implemented thestate-display for channels to make things easier for you. You can define from whichchannels a value is calculated and in which numerical-system this value is displayedwith this display-type. Possible numerical-systems are hexadecimal, decimal, octal,binary and ASCII. These state-channels are preferred with the analysis of data-, ad-dress- or other combined busses.Enter menu “configure-fields” or press “F8” to define a state-channel. The followingwindows will be shown:

Figure 3 defining state-channels

As you can see in figure 3, each logical channel is connected to its hardware input.Each but display position 8, which is defined as state-channel (CH0 to CH7 are con-nected). You can set a proper label for this channel and you can do this with the defi-nition of your first state-channel; click on “OK”.Click on the name of your state-channel inside the timing-view to change the numeri-cal-system which is used for displaying values.

It is not only the type of display that is different to normal channels. The way you en-ter the trigger-condition is different, too:Click on the X beneath your state-channel and a window will be opened:


Description

Figure 4 Trigger-settings for a State-channel

As Figure 4 shows that you can define numerical trigger-conditions for your state-channels. You are free to choose between hexadecimal, decimal, octal, binary andASCI trigger-conditions. The corresponding channel-settings for the included chan-nels will be updated after closing the window.


PC-Logic Analyser

Starting the sampling:Click on the single-feed button to start a new sampling with trigger- and state-channelsettings. Now, the logic analyser waits for the trigger-condition to becomereal and after that, your sampled data will be shown like the following figure shows.As described before, the logic analyser will show you the data before the trace-pointbecause of pre-triggering.

Figure 5 triggered measurement with state-channel

In figure 5 you will see channel 0 with a clock of 4 MHz (source-clock), channel 1only has 2 MHz, and every channel after them only shows the half clock of its previ-ous channel.You will also have noticed that the state channel does not show any values, but why?The reason is that the numbers does not match between one step to the next step.Only the bars as divider for two different states are shown. Zoom into the data andthe numbers will be shown.


Description

5.1.4 Using the zoomAs we could see in step before, the state-channel only shows bars, but no numbers.We only need to zoom into our measurement to solve this problem. You also have tozoom into measurements if you want to analyse timing-problems where the statesare correct, but a few ticks to late or to early.

Press the plus-key at the numeric-keypad to zoom into measured data. The magnifi-cation will be doubled with every key press up to 128-times. Just press the minus-keylocated at the numeric-keypad to zoom out and the magnification will be halved.While zooming the viewed screen is aligned to the right border of the view. Use thecursor-key to scroll left or right to recentre your screen.

Figure 6 visible state-values through zoom-in

As figure 6 shows you can see the values of your stated channel and how the coun-ter is counting back to zero, now. On the right you see how the counter steps from 1to 2 and produces a short zero phase. This is one of the main disadvantages ofasynchronous counters.


PC-Logic Analyser

5.1.5 Hiding unused channelsAs shown in the step before, there were unneeded channels which are responsiblefor making analyse more complicated. Enter the field-configuration (F8) and disablethe unneeded channels with unchecking the logical connections of the channel-names to their input-channel to disable these channels.

Figure 7 hiding unneeded channels

The window will be closed and the new configuration will be used for displaying themeasured data after clicking the OK-Button. Now it is obviously much easier to ana-lyse the important signals.

Figure 8 better overview with hidden channels


Description

5.2 Measurement example: synchronous counterThe next example will describe how a synchronous counter works. This counter alsoconsists a 4 MHz clock source (quartz oscillator) and a programmed GAL as counter.This time you will see that this counter changes all of its outputs at once.We will now analyse this counter if the counter works properly as described before.We will measure the time between clock ticks and output changes.At first connect the input-channels of the logic analyser to the outputs of the counter.Adjust the sample-rate to 50 MHz and the pre-trigger to 2/8.Connect each of the 8 Input-channels with the first 8 display-channels with the “con-figure-fields” window. Set the trigger-condition to trigger and the first 8 channels to 0in the timing-view. After sampling you will see a diagramm like the following:

Figure 9 Measurement at a synchronous counter

You see that the clock from one stage to another is divided by 2 at figure 9. Differentto the asynchronous counter you will see that there is no time between the change ofone output to the change of the next output. All channels are changed at the sametime. This is why this counter is called synchronous counter – every output ischanged with the same clock-tick of the input channel.


PC-Logic Analyser

5.2.1 Measuring timeIf you zoom into the diagram at the trace-point, you will see that there is really notime between switching the outputs. Only channel 0 (the clock-source) is time-shiftedto the other channels.

Figure 10 Synchronised zero-state of the counter

Measurement tools: Cursor and markerIf you want to measure the time-period of the input-clock (4 MHz) you may do this byusing cursor and marker.Both are located below the trace-point after sampling. Click either on the cursor- ormarker-line and drag the line while down-pressing the left-mouse-button to move oneof them. The other way to position the cursor- or marker-line is to press the leftmouse-button to set the cursor position and the right mouse-button for the markerposition.Now we set the marker‘s position to the left most raising slope of channel 0. The cur-sor is set to the second raising slope after the position of the marker. We measurethe doubled clock-cycle, because of the selected sample-rate (50 MHz) which isequal to a sampling-cycle of 20 ns. The sampling rate had to be chosen in accor-dance with the input-clock to measure 250 ns period-time.


Description

Figure 11 Measuring times with Cursor and Marker

The time-difference between the two measure-lines will be displayed in the state-line( below, on the right side). Additionally, the frequency f will be shown there. f=2 MHzwill be displayed. If you multiply this result with 2 you get the entry-frequency.


PC-Logic Analyser

5.3 Measurement example: Handshake parallel printer-portThe next example will examine the parallel printer-port of an IBM-PC. This interfaceconsists of 8 data lines and several handshake lines. All data will be transferred 8-bitparallel as the name may tell you. Some of the handshake-lines are only for signal-ling purposes i.e. PAPER-OUT, INIT, AUTO-FEET and so on. But some of the hand-shake lines are implemented in the transfer of data from and to the PC. Some ofthese handshake lines are: BUSY, STROBE, ACK.We now want to analyse how data-transfer from PC to printer is done and which sig-nal is flagged at which time of transfer. We have to build an adapter for the connec-tion of the logic analyser to do this measurement in combination with a printer. Thisadapter is made of a 25 pin D-Sub plug connected one-by-one with a 25 pin D-Subsocket. Between these two connectors we solder single-line-connectors to connectthe logic analyser inputs. The printer is now connected to the PC through our self-made connector. The following signals are connected to the logic analyser:

Pin at LPT-Port Hardware-channel at LAD0-D7 0-7Strobe 8Busy 9Acknowledge 10PE 11SLCT 12Auto Feed XT 13INIT 15

Table 5-1 Connection LPT-Logic Analyser

Channel 0 to channel 7 are combined as state-channel. The other connections arelabelled as shown in table 5-1.Choose a sample-rate of 1 MHz to gain a full resolution measurement without muchdata-waste. If you choose a higher sample-rate, the amount of data which is sampledwould be much greater and the result will become difficult to overview. If you select alower sample-rate, data loss might occur and short signals might be overseen by thelogic analyser.The pretrigger is set to 2/8 and the trigger-condition is set to trigger with a low stobe-signal.


Description

5.3.1 Printer-communicationsAfter the required settings are done, the logic analyser may begin with sampling.We send a ASCII-text file with “ABCDEFGH....” to the printer using the copy-command to see communications between the PC and the printer.

Beginning the sample and description of the measured data:The following diagram will be shown after you pressed the button “sample with trig-ger”.

Figure 12 Signals during data-transfer to printer

As it is shown in figure 12, the PC puts the data out to D0-D7, after the signal is sta-bled, the strobe-signal is raised (active-low). The printer then reads the data from D0-D7 into its input-buffer latch. At the same time a busy-signal is raised from the printerto signal the PC that no further data shall be send. After the printer has processedthe received data, he raises the acknowledge-signal to show that the data has beenreceived. With the rise of the acknowledge-signal the busy-signal is lowered and thenext byte can be send. It has to be noticed that the PC does not have to use the ac-knowledge-signal as handshake.


PC-Logic Analyser

5.3.2 Comparing printer-speed using copy or print CommandWe want to analyse the different printing-time using either the copy- or the print-command with this example. For that we print the same text twice in the sameprinter. At first we print the text using the print-command which is printing in thebackground using DOS Interrupt routines. The second printout will be done using thecopy command.

While the print-command uses DOS interrupt routines and is executed in the back-ground of the PC is slower in printing. The signal drivers are not read directly by theprinter, because the printer raised them while the PC is doing other things like waitingfor input of the user. So the PC cannot recognise a lowered busy-signal because thisis done with a function which is executed in background and has to wait a while.

It will wait for the signals to come to the right state and then do the next step becausethe copy-command is the only executed command. This theory will be proven withthe next measurements which will show the timing diagram using the print-commandand using the copy-command.

Sample-rate is set to 100 kHz and trigger-condition is the char “A” (dec. 64).


Description

Figure 13 timing diagram using the print-command

As it is shown in this diagram the cursor and the marker are placed just to the pointwhere next data is sent. The time between these to time-lines is the time when thePC/printer needs to send one char. The time measured here is 1,59 ms.

Figure 14 Timing diagram using the copy-command

This diagram shows the transfer using the copy-command. You see that the hand-shake-signals are much shorter when the PC “waits for them”. This results in a timeof 0.64 ms per char transferred.


PC-Logic Analyser

5.3.3 Comparing printer-speed with fast and slow CPUThe next example will answer if the speed of the PC can change the printing speed.You will need a PC with selectable CPU-speed (former TURBO-Key) to do this. Thecomparison is printing the same text twice with the copy command, just changing theCPU-speed.

Settings for sample-rate: 100 kHz; Trigger-condition: “A” (dec. 65).The following diagrams should be displayed after sampling.

Figure 15 printer-speed with high CPU-speed

Figure 16 printer speed with low CPU-speed


Description

We will notice that the speed of the PC is independent to the speed the printer canreceive the data after we measured the time between one Strobe to the next Strobe.This measurement was done using a Intel 286 and a matrix printer !!

You may save your sampled data with the name of your printer and compare thisdata with a new printer you might buy. If you reduce the sample-rate you will loosedata, but you may be able to analyse the data until the print-buffer is full.

5.4 Measurement example: IBM-PC busThe following example will analyse the ISA-Bus of another PC.You need to write a program which will output the value 0x23, 0x24, 0x25 to 0x28 ataddress 0x0704 to follow further steps .

The logic analyser is connected to the ISA-Bus using an extender card which willsupply the needed plugs. The following signals are used.

Signal LA channel RemarkOSC 0AEN 1

RESET 2IORD 3IOWR 4

MEMRD 5MEMWR 6

CLK 7D0-D7 8-15 As STATE-channel (HEX)A0-A7 16-23 As STATE-channel (HEX)

A8-A15 24-31 As STATE-channel (HEX)Table 5-2 Connections PC – Logic Analyser

Connect your logic analyser to the signals shown in table 5-2 and set-up the followingtrigger-condition:A8-A15 = Hex 07 and IOWR = 0 (active low)

With this trigger-condition a sampling will be started, if the address is in range of0x0700 to 0x07FF and the access is type of writing to IO-Port.

Sampling will be started just after the trigger-condition after pressing the button“sample with trigger”.Now start the program noticed in the beginning and wait for the logic analyser be-come ready.


PC-Logic Analyser

The following diagram should be displayed after the sampling is done.

Figure 17 Data sampled during I/O access

The address lines were set to 0x0704 before the trace-point as you can see in figure17. The address of the access can be calculated by combining the upper (A8-A15)with the lower (A0-A7) address lines. The clock signal shows the 8 MHz of the ISA-Bus. You can see how the PC transfers the values to the given address and commitsthem using the IOWR-line. You can also calculate the maximum write-speed of theISA-interface as each transfer uses 8 clock-ticks; that results in a maximum band-width of 1 Mbytes per second. Each transfer has a duration of 1µs as the measure-ment between one IOWR and the next IOWR shows.

Annex

Description

6 Annex

6.1 Customer Communication and Help

Do you need help? If you don’t know how to go on during the in-stallation or operation of your QUANCOMboard please read this user’s guide first.

! Tip ! You can find an ASCII–Text–file“README.TXT”, which includes changesmade after printing this user’s manual on theQUANCOM installation CD.

! IMPORTANT ! If you have further questions please contactour support team and have the following in-formation handy:• Exact type of board• Operating system, hardware equipment

and Bus-System• Name and version of the program, where

the error is reported.• A detailed failure description. Please try to

reproduce the failure, describe it as exactas possible, and which steps led to thisfailure.

Annex

PC-Logic Analyser

Contact:The QUANCOM internet websiteWWW.QUANCOM.DE

Per Fax+49 22 36 / 89 92 - 49

Per e-mail:[email protected]

Address:QUANCOM INFORMATIONSSYSTEMEGmbHIn der Flecht 14D-50389 WesselingGermany

If you need urgent help call:

QUANCOM Hotline Germany+49 22 36 / 89 92 - 20

Monday-Thursdayfrom 9:00 to 18:00Fridayfrom 9:00 to 17:00

Actual driversYou can find the latest Version of QUANCOMsoftware on our internet websitehttp://www.quancom.de.You can also find a lot of information and„Frequently asked questions (FAQ’s)”there.Before you contact the QUANCOM support,please check if you are using the newestsoftware version of the QUANCOM software.

Annex

Description

RepairIf you are not sure whether your QUANCOMboard is defective please call the QUANCOMHotline:

Tel.: +49 22 36 / 89 92 – 20

Before sending the QUANCOM board to us,call:

Tel.: +49 22 36 / 89 92 – 20

If you sent your QUANCOM board to us,please use the original package or any othersuitable package to protect the contentsagainst transport damage. You also need tosend us a copy of the original bill and theRMA number.

You can shorten the repair time by sendingus an exact failure description, so that afaster failure search is possible. Send yourQUANCOM board directly to the service de-partment of QUANCOM Informations-systeme GmbH.

Annex

PC-Logic Analyser

6.2 Technical support formIf you have internet access please enter the following URL in your browser:http://www.quancom.de/quancom/qshop.nsf/techniksupport?OpenForm&eng. Else photo-copy this form and use the copy of this form as a reference for your current configu-ration. Complete this form before contacting QUANCOM Informationssysteme GmbHfor technical support and our applications engineers may answer your questionsmore efficiently. If you are using any other QUANCOM hardware or software prod-ucts please add them to this configuration form. Include additional pages if neces-sary.Name: _________________________________

_________________________________Company: _________________________________

_________________________________Address: _________________________________Phone: _________________________________Fax: _________________________________Computer brand / Processor: _________________________________Operating system: _________________________________Display adapter: _________________________________Mouse: _________________________________QUANCOM board _________________________________Other adapters installed: _________________________________Hard disk (capacity, free): _________________________________The problem is: _________________________________List any error messages: _________________________________

____________________________________________________________________________________________________________________________________

The following steps cause the problem to recur:_______________________________________________________________________________________________________________________________________________________________________________________________________________________________________

Annex

Description

6.3 Hardware and Software configuration formThis form helps you to list your hardware and software settings. Complete this formeach time you change your software or hardware configuration, and use this form asa reference for your current configuration. Complete this form accurately before con-tacting QUANCOM Informationssysteme GmbH for technical support, so that our ap-plication engineers can answer your questions more efficiently.

• QUANCOM Product:Name / Name of board __________________________Interrupt Level __________________________DMA Channel __________________________Base I/O Address __________________________Operating system __________________________• Other informationComputer brand and Model __________________________Processor __________________________Clock Frequency __________________________Type of Video Board Installed __________________________DOS Version __________________________Programming Language __________________________Programming Language Version __________________________• Other Boards in System __________________________Base I/O Address of other Boards __________________________DMA Channels of other Boards __________________________Interrupt Level of other Boards __________________________

Annex

PC-Logic Analyser

6.4 Documentation Comment FormQUANCOM Informationssysteme GmbH would like you to comment on the docu-mentation supplied with our products. This information helps us to provide you withquality products to meet your needs. Please include additional pages if necessary.

Title: PC-Logic Analyser

Edition Date: 03.07.03

Please comment on the completeness, clarity, and organisation of the manual. If youfind errors in the manual, please record the page numbers and describe the errors.Thank you for your help.

Name: ________________________________________________________________________________________________

Company: ________________________________________________________________________________________________

Address: ________________________________________________________________________________________________________________________________________________

Phone: ________________________________________________Fax: ________________________________________________Comment: ________________________________________________

________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________

Mail to: [email protected]

Fax to: +49 2236 89 92 49

Address: QUANCOM Informationssysteme GmbHIn der Flecht 14,50389 WesselingGermany

Annex

Description

trademarks:

Linux is registered trade-mark of Linus Torvalds.MS, MS-DOS, Microsoft, Visual Basic, Windows, Windows XP/2000/NT/ME/98/95 is

registered trade-mark of Microsoft Corporation.XT and PS/2 are trade-marks and IBM, OS/2 and AT are registered trade-mark of

International Business Machines Corporation.Intel, Pentium is registered trade-mark of Intel Corporation.

USB is registered trade-mark of USB Implementers Forum Inc.JAVA is registered trade-mark of Sun Microsystems.

DELPHI and Pascal are registered trade-mark of Borland Corporation.PCI is registered trademark of PCI Special Interest Group.

National Instruments, LABVIEW is registered trade-mark of National InstrumentsCorporation.

Agilent VEE is registered trade-mark of Agilent Technologies.

By other product- and company names, that are mentioned in this manual, it maydeal with trademarks of the respective owners.

user’s guide „logic - analyze“ for pc logic analyzer · 2020. 8. 29. · position the...

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