using distortion shaping technique to equalize adc thd performance between ates
TRANSCRIPT
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Using Distortion Shaping Technique to Equalize ADC THD Performance Between ATEs
IMSTW 16
Peter Sarson CMgr MCMI SMIEEEFull Service Foundry
4th July 2016
Prof Hauro Kobayashi Gunma University
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Introduction
• During development of any test program test engineers sometimes face the issue that the tester isn’t as good as the chip
• This causes issues when device specs need testing and the limit cannot be reached
• Kobayashi will show some mathematics: harmonic distortion contents can be shifted up close to Nyquist frequency.
• Peter will show how the harmonic performance of an ATE’s AWG can be improved using this approach
• Peter will show how this approach improved the result and reproducibility of a 12-bit ADC testing
• Peter will show how this approach improved the result of a 16-bit ADC testing that was limited by the tester performance
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Research Objective
Low distortion signal generation with AWG for low cost and high quality testing of ADC
Investigation of phase switching signal generation method with experiment at ATE environment
• No need for AWG nonlinearity identification• Only DSP program change
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ADC test signal Test result
ADC Testing with Sine Signal
Freq.
ADC HD3
Freq.
“No Go”
“Go”
Freq.
Reference level
Allowable
fundamental
Freq.
Test result
fundamental
AWG ADC
𝑍=𝑏1𝑌 +𝑏3𝑌 3
fin 3fin
fin 3fin
fin 3fin
fin
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ADC test signal Test result
Problem of Conventional Method
AWG HD3+ADC HD3.
Freq.
fundamental
Freq.
Test result
AWG ADC
𝑍=𝑏1𝑌 +𝑏3𝑌 3fundamental
fin 3fin
fin
Test signal generationY=a1Din + a3Din
3
3fin
AWG HD3
HD3
ADC HD3 cannot be measured accurately
Low quality test
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ADC test signal Test result
Research Goal
Only ADC HD3
Freq.
fundamental
Freq.
Test result
AWG ADC
𝑍=𝑏1𝑌 +𝑏3𝑌 3fundamental
fin 3fin
fin
Test signal generationY=a1Din + a3Din
3
3fin
AWG HD3 reduction
HD3
High quality testOnly program change
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Conventional Signal Generation with AWG
AWG
DACCLK
DSP
X XXX
Din
Din
AWG sampling frequency: fs(AWG) = 1/Ts
A
𝐗= Acos(2πf_in nT_s)
0 0.1 0.2 0.3 0.4 0.5-300
-200
-100
0
Pow
er [d
B]
Normalized frequency f/fs
𝐟 𝐢𝐧
𝐇𝐃𝟑
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Proposed Signal Generation with AWG
AWG
DACCLK
DSP
X0 X1X0X1
Din
Din
AWG sampling frequency: fs(AWG) = 1/Ts(AWG)
𝐗𝟎= 1.15Acos(2πf_in nT_s−π/6)𝐗𝟏=1.15Acos(2πfin nTs+ /6)𝜋0 0.1 0.2 0.3 0.4 0.5
-300
-200
-100
0𝐟 𝐢𝐧
𝐟 𝒔/2−𝟑𝐟 ¿
𝐟 𝒔/2−𝐟 ¿
Pow
er [d
B]
Normalized frequency f/fs
Θ = π/3𝐓𝐬 (𝐀𝐖𝐆)
X 0
𝐗𝟏
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Principle of 3rd Harmonics CancellationTwo waves with phase difference π are cancelled
Con
vent
iona
lPh
ase
Switc
hing
Θ = π/3 3Θ = π
3rd o
rder
non
-line
ar s
yste
mP
hase
rota
tion
by x
3
fundamental: fin 3rd harmonics: 3 fin
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X0=Asin(2πfint+π/4) X1=Asin(2πfint-π/4)
HD2 Cancellation2-way interleave cancels HD2
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X0=Asin(2πfint-π/4-π/6)X2=Asin(2πfint+π/4-π/6)
X1=Asin(2πfint-π/4+π/6)X3=Asin(2πfint+π/4+π/6)
HD2, HD3 Cancellation4-way interleave cancels HD2 & HD3
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Be Careful
If you use this technique without filtering the generated high-frequency spurious
Harmonic contents of the ADC under test will be under-estimated.
These spurious components need filtering outto get back normal sinewave without harmonics.
More detailed later.
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How to Do in Software2-signal interleaved
Element 1
Element 2
Element 3
Element 4
Element 5
Element 6
Element 7
Element 8
Array 1 1 2 3 4 5 6 7 8
Array 2 9 10 11 12 13 14 15 16
Supressed 1 10 3 12 5 14 7 16
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How to Do in Software4-signal interleaved
Element 1
Element 2
Element 3
Element 4
Element 5
Element 6
Element 7
Element 8
Array 1 1 2 3 4 5 6 7 8
Array 2 9 10 11 12 13 14 15 16
Array 3 17 18 19 20 21 22 23 24
Array 4 25 26 27 28 29 30 31 32
Supressed 1 10 19 28 5 14 23 32
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Test Setup for Measuring Tester Performance
AWGMEMORY
AWG FILTER50MHz
DIGITIZERFFTTester Result
Loopback
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Tester 1 3rd Harmonic ReductionMeasured spectrum level improvement of reference vs suppressed 3rd harmonic for AWG.
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Tester 1: 3rd and 5th Harmonic ReductionMeasured spectrum level improvement of reference vs suppressed 3rd & 5th harmonics for AWG.
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Harmonic ReductionMeasured Harmonic Performance Improvement for AWG Using the Proposed Method
Harmonic Improvement
2nd6 dB
3rd16 dB
4th18 dB
5th23 dB
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ADC Performance Test Setup
AWGMEMORY
AWG FILTER50MHz
DUT ADC
DIGITIZERFFTTester Result
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12-bit ADC Results Tester 1
signal Thd std units
ref 89,7 2,5 dB
2nd_red 89,8 2,1 dB
3rd_red 89,3 2 dB
4th_red 89,5 2,1 dB
5th_red 89,2 2,6 dB
2nd,4th_red 91 2,4 dB
3rd,5th_red 89,7 2,5 dB
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12-bit ADC Results Tester 1
signal Thd std units
ref 89,7 2,5 dB
2nd_red 89,8 2,1 dB
3rd_red 89,3 2 dB
4th_red 89,5 2,1 dB
5th_red 89,2 2,6 dB
2nd,4th_red 91 2,4 dB
3rd,5th_red 89,7 2,5 dB
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12-bit ADC Results Tester 1
signal Thd std units
ref 89,7 2,5 dB
2nd_red 89,8 2,1 dB
3rd_red 89,3 2 dB
4th_red 89,5 2,1 dB
5th_red 89,2 2,6 dB
2nd,4th_red 91 2,4 dB
3rd,5th_red 89,7 2,5 dB
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12-bit ADC Harmonic Suppressed Result2nd and 4th suppressed delta and overall THD Improvement
THd ref THd supp
Tester 2 88,7dB 91dB
Tester 1 89,6dB 91dB
Without suppression:• Different measured values of THD performance
With Suppression:• Exactly the same result between Testers 1 & 2
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Site to Site Comparison No difference between sites with the proposed method!
12-bit ADC testing case
Tester 1 Site 1 Site 2 delta
Red 91dB 91,1dB 0,1dBref 89,6dB 89,6dB 0dB
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3rd, 5th and 7th Suppressed
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How 8-signal interleaved looks like2^3 = 8
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3-Harmonics (3rd , 5th & 7th Harmonics) Suppression
Using 3-harmonics suppression algorithm, effect of the sidebands would be SB= fs/8 – 7*fin
Maximum sampling freq. (fs) of AWGHSB : 250MHz Signal freq. (fin): 1MHz
Filter with 24MHz cutoff is needed
Not available on AWGHSB
Need a load-board filter.
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OVERSAMPLE = 1FS: 259.2000 kHz
THD = -89.83dB
Another Example – Tester 1 (Conventional)Obelic 16-bit ADC – no suppression, direct conversion
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OVERSAMPLE = 1FS: 259.2000 kHz
THD = -89.83dB
Another Example – MX01 (Conventional)16-bit ADC – no suppression, direct conversion
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OVERSAMPLE = 600FS: 155.5200 MHz
THD = -115.09dB
MUCH BETTER
Obelic 16-bit ADC – 2nd Harmonic Suppressed (Proposed)Oversample 600 times – Tester 1
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OVERSAMPLE = 600FS: 155.5200 MHz
THD = -113.87dB
Same as Tester 1
16bit ADC – 2nd Harmonic Suppressed (Proposed)Oversample 600 times – Tester 2
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Performance summary
Using a 12-bit ADC, testing performance can be improved but you are limited to the noise performance of the ADC itself
• If spec limits are an issue, the technique can help squeeze out some margin
Using a 16-bit ADC, performance can be significantly improved (say, by 25 dB) as the noise floor is much lower due to the number of bits.
Effectiveness of the distortion-shaping technique was verified with ATE environment.
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Appendix
Proposed signal generation method• Distortion components close to signal band are reduced• Distortion components far from signal band may appear.
Similar to but different from noise-shaping
Distortion-shaping
Normalized frequency f/fs