using fpga to control a virtual sorting systemjlcurzel/projeto integrador...using fpga to control a...

Using FPGA to Control a Virtual Sorting System

Jeferson Luiz Curzel1, Ricardo Lüders2

1Federal Institute of Education, Science and Technology of Santa Catarina – IFSC. R. Pavão, 1337 – Joinville – SC – Brasil – 89220-618. ([email protected])

2Federal University of Technology-Paraná - UTFPR. Av. Sete de Setembro, 3165 - Curitiba - PR - Brasil - 80230-901. ([email protected])

Abstract—This paper describes the development of a controller for a virtual sorting system based on FSM (Finite State Machines) with implementation in FPGA (Field Programmable Gate Array). The paper highlights the interface between hardware and a virtual plant that simulates its real behavior. Moreover, the control solution is implemented in FPGA which allows real time operation. All steps of the developed project are presented including a proper problem description, developing tools and implementation. Moreover, simulations are performed to test the overall system functioning.. All hardware implementation is made in a Programmable Logic Device (PLD) like FPGA.

Index Terms—Virtual Sorting System, Finite State Machine, FPGA.

I. INTRODUCTION Sorting systems are able to identify different types of

objects and sort them according to their destination. These systems are usually associated with other processes in an industry, such as storage and distribution, assembly lines, inventory control, among others [1]. The system modeling is essential for a successful control action. The integration of inputs and outputs of the system components and how they interact each other are fundamental for the controller design. In this paper a sorting system is modeled by using FSM (Finite State Machine).

A FSM is a transition state machine that represents the logical behavior of the system components. Transitions from a (current) state to another occur when a particular event has occurred. There is a single current state among all possible states of the machine. A state stores information about the past, reflecting input changes from the initial state to the current one. A transition indicates a state change and is described by a necessary condition for the transition to occur. An action is an activity that must be performed at a given time. Finite state machines are used to model a large number of engineering applications, such as manufacturing process or communication protocols.

This paper is organized as follows. Section II presents the different components of the project. The state ma-chines designed and implemented for controlling the sys-tem are presented in Section III. In Section IV, tests and the control system tuning are presented with conclusions in Section V.

1 Disponível em: http://www.realgames.pt/index.php/en/downloads

II. PROJECT DEVELOPMENT

A. The Sorting System The sorting system analyzed in this work was

developed by Real Games as part of the Software ITS PLC1 (Interactive Training System). ITS PLC is a tool for teaching and development of programming control devices. This software offers study cases with increasing levels of difficulty which cause users to be involved in a natural way for their training. There are five virtual systems which are visual simulations of an industrial plant including sensors and actuators (virtual) whose status can be sensed by the control device. The goal is to control each virtual system in a similar way to a real plant. The sorting system is composed of one feeder belt, three conveyor tables, ten sensors, one turntable with rollers and two elevators distributed as shown in Fig 1. The mats and rotary table are set in motion by their respective actuators. Cases transported on pallets in the system can be small or big.

The data exchanged between the control device and the virtual system is performed through a board data acquisition (DAQ) with 16 input and 16 output isolated channels as well as a USB communication interface. The connection scheme of the virtual system is shown in Fig. 2.

B. DE2 Altera - Development and Teaching Board The development board DE2-35 [3] is equipped with

almost 35,000 logic elements of Altera Cyclone ® II 2C35. It has not only the advantages of DE2 board, such as storage, multimedia and network interfaces, but also has components of higher capacity memory. The board offers a rich set of features that make it suitable for using in a lab environment at universities or for technical courses in a variety of projects as well as for development of sophisticated digital systems. DE2 board is shown in Fig. 3.

Figure 1. Virtual Environment ITS PLC for the Sorting System

978-1-4799-2025-9/14/$31.00 ©2014 IEEE Polytechnic of Porto (ISEP) in Porto, Portugal from 26-28 February 20142014 11th International Conference on Remote Engineering and Virtual Instrumentation (REV)

67

Figure 2. Connection between ITS PLC, DAQ and DE2 boards

C. Signal conditioning for DE2 with DAQ board interface

Due to the difference of voltages between DAQ (connected to PC USB port) and DE2 boards, it was necessary to implement an interface of opto-couplers for electrical signals providing an electrical isolation between two systems. Thus, output signals of DAQ board are optoisolated from the input plate DE2. Likewise, output signals from the plate DE2 are optoisolated from the inputs of DAQ board. In Fig. 4 is shown an image of the interface board with opto-couplers. Thus, the signals from sensors in the virtual environment are recognized by pins of DE2 board configured as inputs. Similarly, output signals from pins of DE2 board are then recognized by actuators of the virtual environment.

III. THE FINITE STATE MACHINES Signals from sensors of the virtual system determine the

coordination of the sorting system, as well as the state of the sensors and buttons of the virtual operator panel is performed the activation and/or deactivation of actuators responsible for movements engines mats. In Fig. 5 is shown the sensors of position (0 to 10) and actuators of the system. The mapping between sensors and actuators of the virtual system with pins of slot JP1 in DE2 board is shown in Table I.

TABLE I. MAPPING SENSORS AND ACTUATORS TO PINS OF DE2 BOARD

Figure 3. Altera DE2 Board

Figure 4. Interface board with opto-couplers

A nomenclature for transitions and actions of the FSM are given by Table II. In the following the development of FPGA programming in Quartus II software is detailed [4]. An overview of the software is presented in Fig. 6. Next the state machines are described using the nomenclature of Table II.

A. Counter This state machine is a counter of boxes which utilizes

sensor S0 to increment is two-bit counter and sensor S3 to decrement it.

Figure 5. Position of Sensors and Actuators


Page 168

TABLE II. NOMENCLATURE FOR THE FINITE STATE MACHINES

Since the maximum allowed value is three, this two-bit

counter is sufficient. The state machine considers all possibilities from one to two boxes When a limit is reached, no new entries are allowed to the system.

B. Feeder Belt 0 In this state machine controls the operation of Belt 0

which is the system feeder. Thus, entries Start, Stop and Mode are used to enable or disable the belt operation. When receiving a signal from S0, the counter status is checked. When the limit of three boxes is reached, belt 0 stops working. It is only switched on when a box leaves the system, which us captured by sensor S3.

C. Conveyor 1 The corresponding state machine controls the operation

of Conveyor 1 which is feeder of the rotary table. Thus, a Start input is used to enable or disable this operation. When receiving a signal S3 (out of the belt), the status of sensor S4 (table position) and S6 (table discharged) is checked.

Figure 6. Project Overview in Quartus II Software

If the table is suitable to receive a box (S4) and it is empty (S6) then output A1 triggers the loading of this box into the roller table.

D. Turntable 4 This state machine controls the rotary table. When a

box is loaded into the turntable, sensor S6 indicates whether or not the box is positioned according and rotation is driven by A4. The rollers are then triggered by leaving of the box, which is detected by S7 or S8. In the negative transition of S7 or S8, the rotary table returns to its initial position.

E. Turntable Rollers 2 and 3 This state machine controls the operation of the roller

rotary table. Depending on the box type present on the turntable (small or big), the drive turn on rollers clockwise or anti-clockwise. The effect is that the box will be sent to conveyor 5 or 6, depending on its size. The operation of the rollers also depends of sensors in the conveyors 5 and 6 in this way, the entry of both tracks are without the presence of the box (S7 and S8) is allowed to drive the roller in either direction, by the outputs A2 and A3. The box size is measured by sensors S1 and S2 placed on the top of first conveyor.

F. Conveyor 5 In this state machine controls the operation of the

conveyor 5. If the type of box on the rotary table is small, then the drive roller is set clockwise and the box is sent to conveyor 5. The operation of conveyor 5 also depends on sensor S8 (to trigger) and S10 to turn off the conveyor 5 through output A5.

G. Conveyor 6 In this state machine controls the operation of the

conveyor 6. If the type of box on the rotary table is big, then is made of the drive rollers is set counterclockwise and the box is sent to conveyor 6. The operation of the conveyor 6 also depends on sensor S7 (to trigger) and S9 to turn off the conveyor 6 through output A6.

In Fig. 7 shows all state machines used in the controller design.

IV. TESTS AND TUNING After implementation of the interface between signals

coming from the virtual system (DAQ board) and FPGA (DE2 board), tests have been performed to verify if the initial signs were correctly configured. After this step were programmed state machines and other project components, such as the appointment pins I/O in the Quartus II environment.

Following FPGA programming, tests have been made and results verified. The main issue was noise generated by signals through the interface. It was solved by decreasing the system clock to approximately 12 Hz resulting in satisfactory outcome.


Page 169

Figure 7. State machines used in the controller design

Another possibility to deal with this issue would be using timers which introduce a small delay of milliseconds (for experimental test set) enough to assure an effective reading by FPGA. The experimental set built for this project is shown in Fig. 8.

V. CONCLUSION A controlled sorting system has been presented using

finite state machines as design technique. Moreover, a physical interface has been necessary for connecting the virtual plant to the logical controller implemented in FPGA. The system modeling using finite state machines has proved to be complex in terms of eventual changes in the control specifications. However, the possibility to check the plant behavior in real time is an important

issue for future investigation of other approaches control, such as Petri nets [5] and the Supervisory Control Theory [6]. The use of FPGA rather than other controllers, PLC for example, was due to the cost of the equipment and also for being an application for educational purposes, in which students of technical and technological courses can use the FPGA as a design tool. Considering this, other approaches to the control design can be investigated in the future for other virtual systems available from software ITS PLC, such as batching, palletizer, pick & place and the automatic warehouse.


Page 170

Figure 8. Devices used in the project

REFERENCES [1] Real Games LTDA, “User guide for ITS PLC

PROFESSIONAL EDITION,” Revision 1.3 (2011), pp. 27-32. [2] Actel Corporation, “Designing State Machines for FPGA -

Application Note AC130,” vol. 5, pp. 89-96, September 1997. [3] DE2 Development and Education board, “User Manual”, Ver-

sion 1.41 (2007). [4] Altera Corporation, “Introduction to the Quartus II Manual”,

www.altera.com/literature/manual/introtoquartus2.pdf - 2010. [5] Murata, T. “Petri nets: Propeties, analysis and applications”,

Proceedings of the IEEE 77, vol. 4, pp. 541–580. April 1989. [6] Ramadge, P. J., and Wonham, W. M. “The control of discrete

event systems”, Proceedings of IEEE 77, vol. 1, pp. 81-98, April 1989.


Page 171

using fpga to control a virtual sorting systemjlcurzel/projeto integrador...using fpga to control a...

Documents