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Using on-chip Test Pattern Compression for Full Scan SoC Designs

Helmut LangSenior Staff Engineer

Jens PfeifferCAD EngineerJeff Maguire

In todays mixed signal System-on-Chip designsadvanced Design-for-Test techniques become moreand more important to meet test coverage and qualityrequirements. However, standard strategies often can-not be used because of design specific requirementslike the limitation of available input and output pins.This paper describes the Design-for-Test strategy ofthe latest version of Motorola’s chip family for a mixedsignal application. Deterministic test pattern, whichare generated using an ATPG tool, have been used tostimulate the design and achieve efficient and high testcoverage. The memories are tested by using a memoryBIST implementation. The limitation of available digi-tal input and output pins is solved in two ways. Analog

Principal Sta

Motorola SPS, System-onMunich, G

Helmut.Lang@motorola.com Jens.Pfeiffe

input pins have been modified to serve as digital pinsin test mode. On-chip test pattern compression usingmultiple input shift register (MISR) is used to reducethe number of required output pins. Failure diagnosticcapabilities have been implemented to allow debug ofailing devices. The paper describes the test strateg

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for the System-on-Chip device and outlines the designflow which was used to implement it.

Overview of the Design and Application

Figure 1 shows the basic structure of the application. Tchip set consists of two application specific mixed signaintegrated circuits (IC A and IC B), which do have thecapability, to interact with a micro controller or anoptional DSP core.

IC A is the frontend circuit, which contains the analoginterfaces for the application. Having 40% of the designbeing analog circuitry, the number of available digitalports is very limitied. A new DFT methodology isrequired to achieve a fault coverage of more than 95%.The digital part of the design itself consists of a core,embedded memories and application specific componeThe percentage of digital circuitry in the second appli-cation specific IC is much higher, therefore standard DFmethods can be used.The silicon is manufactured in a high performance dualpoly 0.25µm CMOS process technology. The PowerSupply Voltage is 3.3 V.

Design-for-Test Strategy Overview

The predecessor of the current chip set is tested usingpattern which are derived from application specifisimulation runs. Basic stuck-at fault coverage for thdigital part of the design is achieved by applyin

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r@motorola.com Jeff.Maguire@motorola.com

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functional test pattern without any structural test method.

For the new chip set an enhanced test strategy is requiredto improve test coverage and failure analysis. Theselection of any standard methodology like full or partialscan is constrained by only having a single digital outputpin available. The design also misses the required amount

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of digital input pins for a full scan design. Thus, a new testrategy has to be defined which covers all of the digitpart of the analog mixed signal design. However,achieve a stuck-at test coverage of more than 95%structural test strategy which allows the usageAutomatic Test Pattern Generation tools must be usLogic Built-in Self-Test is found not to be an adequatsolution because of required test coverage.

A new strategy is developed which is outlined below.

• Full scan test strategy is implemented on all digitalblocks of the design.• All scan chains (preferably balanced), are connecteto scan input pins.• All outputs of the chains are fed into a Multiple InpuShift Register (MISR) which provides on-chip test pattercompression.A Multiplexer allows to connect the output of the MISRor the output of a scan chain to the scan-out pin.

An overview of the Design-for-Test architecture is showbelow:

Figure 1:Design-for-Test Architecture Overview

The main advantage of this Design-for-Test strategy is,that only a single digital output pin is required to test thdigital parts of the design. No loss in test coverage musbe obtained. If additional observe points are added to tdesign, which make the “pseudo full scan design” to a fuscan design, an ATPG tool can be used for test patterngeneration. Though these generated test pattern cannoused on the tester, as the additional observe points areavailable on the tester, they can be used to stimulate th

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design during simulation. Simulation results can be usto prepare test pattern. (Please see the paragraph aboImplementation Flow later on).

The number of available input pins during scan test mis increased by modifying analog input pins to allow th

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use as scan input pins. The required modifications to thanalog pins are described later in this paper.

The test strategy for the digital blocks is complemented bthe following items:

• Built-in Self-Test is implemented for embeddedmemories which are not connected to the external bus.• Functional memory testing is used for embeddedmemories which are connected to the external bus.• All modules can be switched off (power-down) toallow IDDQ measurements.• Analog modules are tested by functional testsdeveloped on the tester.

Analog Input Pin Modification

To increase the number of available input pins analog pcells must be modified. The purpose of the new pad cellto use analog I/O’s as scan inputs during scan test mod

This is achieved by the following modification:

Figure 2:Analog Pad Cell used as scan input

An additional buffer (TSTBUF) is connected to the analoI/O cell. This buffer is placed in an analog power domaiand preferably is placed adjacent to the analog I/O padcconcerned (see Figure 2). An input protection network iprovided to the input (IN) of the buffer which consists of aseries resistor (solicited poly resistor) and of secondaryESD protection diodes. Therefore input IN is connectedthe analog I/O padcell. The input IN can be enabled/disabled using the input EN. This input of the buffer isconnected to the device input which controls whether th

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device is in scan test mode or in normal functional mode.Thus, the influence of the additional connection of theanalog input pin to the digital part of the device can beminimized during functional mode.

On-chip Test Pattern Compression

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Since there are a limited amount of device pins and theare many flip-flops in the design, an approach is neededreduce the number of test pins while reducing the depththe scan chains. On-chip test pattern compression isrequired because only a single digital output pin isavailable for testing the digital part of the device. As morthan 20 scan chains are inserted in the various digitalblocks of the design, test results have to be compresseinto single bit information. An on-chip multiple input shiftregister (MISR) is used to perform this task. Since theMISR produces a single scan output, the rest of the chipins can be used to drive the input of all the scan chain

The MISR is implemented as a Type 2 (internal XOR)using a primary polynomial. The MISR is 31-bits wide,and each scan output signal bit feeds into a bit positionthe MISR register. Rather than generating a signature, tMISR will be used to combine all the scan chain outputinto one signal. A MISR was chosen rather than an XOtree to reduce the probability of a fault masking betweethe chains. A single bit of the MISR is brought out to thdevice using a digital output pin. This output is strobedduring scan test mode continuously to avoid aliasing.

Failure Analysis Capabilities

The usage of the on-chip MISR drastically reduces anyfailure analysis capabilities which are accompanied byusing a structural test approach like full scan design.

This reduction is not acceptable for the device. Althougthere is the restriction of only having a single digitaloutput pin, it still needs to be possible to directlyinvestigate the content of each flip-flop of the design.

For this purpose an additional module is implemented tmultiplex a particular scan chain or the MISRcombination of all the scan chains into a single signal thcan be routed to the device output. The architecture of tmodule is shown in Figure 3. A 32:1 multiplexer is used tselect a particular scan chain of the chip or the MISRcombination of all the scan chains. The output of thismultiplexer drives the output, which can be connected tthe chip scan output pin. The 31-bit MISR is used tocompress all the scan chains into a single signal, whichselected when the scan control registers are all zeros. S

chain outputs connected to the multiplexer input signaare selected in order with the scan control signal valuegreater than zero. For example scan_out[0] is selectethe scan control value of ‘00001’ and scan_out[30] isselected if the scan control value is ‘11111’.

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Figure 3:Pattern compression and failure analysisarchitecture

The scan output signal of one scan chain is used as scinput signal of the following scan chain. This feature isused to enhance debug capabilities, to get similar debucapabilities as in a full scan design.

It is key that the registers, which are controlling thedifferent failure analysis modes, are not part of any scachain. They have to be set to a defined value in the setprocedure of the scan test using the external bus of thedevice and have to retain this value until the test isfinished.

The additional logic, which is introduced by the failureanalysis capabilities is not fully covered by the ATPGpattern. Functional test pattern have to be developed afault simulated for these parts of the design.

Details of the on-chip pattern compression and failureanalysis implementation of the device are shown inFigure 3.

Design-for-Test Implementation Flow

The Design-for-Test strategy requires additional steps ithe implementation flow compared to a standard designflow for full scan design. The different steps are shown iFigure 4 and outlined in this paragraph.

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Figure 4:Implementation Flow

Test synthesis of the testability structures is performedusing Synopsys Design Compiler and Design CompilerPlus synthesis tools. The Multiple Input Shift Register(MISR) and the memory BIST implementation isdescribed in Verilog RTL code. Test points to fix Designfor-Test design rule violations, like not transparent latcheduring scan test mode, read/write stability of embeddedRAM memories during shift mode, disabling of clockgating during shift mode, are also included in the RTLcode. The automatic test point insertion by Synopsys DExpert Plus is not used.

It is key for the overall test strategy that there are nosources for Logic X simulation values in the design. LogiX values in simulation would make the MISR resultunpredictable and on-chip test pattern compression wounot be usable. Therefore, all flipflops must be resetableAll on-chip tristate logic, like internal tristate busses, fromprevious designs of the chip set family were removed oconverted to a multiplexed bus approach.

Synopsys DC Expert Plus is used for scan chain inserton top level of the design. Initially the design is compile“test-ready”, which means that scanable flipflops arealready inserted in the design replacing normal flipflopfunctionality, but no scan routing is performed yet. DCExpert plus generates balanced scan chains of equallength to minimize overall scan chain length.

ATPG

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without MISR

including MISR

Pattern preparationgenerate cycle-based pattern

cycle based pattern(WGL format)

Fault coverageinformation

event based patternincluding MISR results

Final pattern

Verilog PLI

For automatic test pattern generation the MentorGraphics’ ATPG tool Fastscan is used. Fastscan suppautomatic test pattern generation for full scan designsa full scan design technique implies scan input and scoutput signals for every scan chain, additional userdefined output pins have to be added to the device in

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Fastscan. These “virtual” output pins are used as scanoutputs during ATPG.

As the Multiple Input Shift Register is not part of any scanchain, the ATPG tool treats these sequential elements ablack boxes and converts them into tied-to-X gates. Thifact has got two major implications: First the MISR itseland the fanout of the MISR is not testable by the ATPGtool. All injected faults of the related gates are ATPGuntestable and therefore lower the test coverage statistiSecond, the MISR output value will be always masked the test pattern generated by the ATPG tool. Therefore, ttest patterns, which also reference the virtual output pinfor the scan chains can not directly be converted into ATformat. The test pattern generated by the ATPG tool caonly be used as simulation stimuli.

The analog blocks of the design are modeled in Fastscas black boxes. As this could lower the achievable testcoverage quite significantly. The interfaces betweenanalog and digital parts must be defined. Ideally first gatwithin the digital blocks interfacing to the analog parts arflipflops, which are part of scan chains.

ATPG patterns are generated in WGL format. This formais the standard format used within Motorola’s SoC DesigSystem Stingray. The design system provides simulatoextensions using the Verilog Programming LanguageInterface (PLI) which allow to apply test pattern in WGLformat to the design during simulation. This is normallyused to verify the correctness of the test pattern duringtiming simulation using a Verilog HDL simulator.Simulation results are compared with expected results the WGL test pattern. Any mismatches duringresimulation will be highlighted.

As already mentioned, in that special case, the WGL tepattern contains data that cannot be used for testing thdevice because the file contains virtual scan outputs anthe MISR output is masked. The PLIs can be used, tostimulate the device and to generate meaningfulsimulation results, which also contain the MISR output.For functional timing simulation on gate level the Verilogsimulator Verilog-XL of Cadence is used.

The simulation output data is generated in event based

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Verilog Change Dump (VCD) format. This event basedformat is converted to a cycle based tester format. TestDevelopment Series software of Fluence (formerly TSSI)is used for this design step. Motorola’s SoC design systemprovides a highly automated flow.

The resulting WGL test pattern file is verified again using

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the WGL PLIs during functional simulation. Additionallythe fault simulation is performed using Cadence VerifauFault Simulator to calculate the test coverage of the tespattern for those faults which can not be tested by theATPG tool (e.g. the MISR gates, which are categorizedATPG untestable during the ATPG process). Bothresimulation and fault simulation is performed includingbackannotation of timing data from place and route(parasitic information) to achieve timing accuratesimulation results.

In the final step the test pattern in WGL format aretranslated into tester specific data. Additional test progradata is derived from the design database to provide alldata required for the full test program. The TeradyneA580 mixed signal tester is used to test the device.

Design-for-Test Implementation Problems

Main problems which have not been foreseen up front aall related to logic X propagation to the Multiple InputShift Register. The Mentor Graphics DFT tool suitesupports logic Built-in Self-Test implementation. In thisflow X propagation is checked during automatic testpattern generation by various DFT rules. As the devicedoes not use a standard BIST methodology the built-inDFT rules could not be used during Fastscan ATPG. Thfirst time X propagation is identified in the design flow, iduring test pattern resimulation and investigation ofsimulation results. This implied a significant iteration loopto correctly setup the ATPG tool by changing the testsetup routine or modifying the design. Normal test pattegenerated by an ATPG tool include a significant numbeof “don’t care” and mask values. Such values can not bhandled by a MISR. Simulation has to provide the exaclogic value.

Logic X sources in the design are especially related toembedded RAMs and analog blocks. Other X sources hbeen solved up front. The initial test setup routine did ninclude a procedure to put the embedded RAMs in adefined state. This would not be a problem for normalATPG. For the on-chip test pattern compression it is amajor problem as RAM outputs will be logic X. Theselogic X values will be captured by sequential elements,which are part of a scan chain during the capture cyclethe scan test and will be propagated into the MISR durin

scan shifting. The test setup of ATPG, which alreadycontained a reset sequence, must be enhanced to loacontents of all embedded RAMS into a defined value.

Analog modules must be modified to output a defined,tristate, logic value, if the device is in scan test mode.

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this was not included in all analog module specificationadditional logic gates are introduced, which tie theinterface signals between analog and digital portions ofthe design to a known state. These fixes are performedthe RTL code. No automatic test point insertion was us

Memory BIST implementation

The System-on-Chip design contains several smallmemories that needed to be tested. Memory BIST wasrequired since some of the ROMs where hidden from thexternal serial bus interface. BIST logic for each memowas deemed to be too much overhead due to the size othe memories. Therefore a minimal global memory BISconcept was designed to achieve a good memory faultcoverage.

Since all RAMs in the design were accessible from theexternal serial bus interface, BIST writing to thememories were accomplished over this bus, using thetester as a BIST writer. Using the tester as the BIST writeprovides the maximum flexibility in the BIST algorithm atthe expense of test time writing the memories over theserial interface. This reduction in test time was of minorissue since the test time is dominated by analog test tim

In addition to the BIST mode control register, eachmemory in the design is driven by an incrementing BISaddress register, which is used to sequentially read eacmemory location of each memory concurrently. Theoutput of the memory read access is then fed into a MISwhich produces a compressed 1-bit output signal that itreated in the same way as an internal scan chain outpThe overhead of the MISR can be reduced by convertingdata register used in normal operation into a MISR. Thinew MISR behaves as a data register during normaloperation, but implements the MISR functionality in theBIST read mode. In addition, a MISR could be shared foseveral local memories by pre-XORing memory outputsand feeding this new XORed value to the input of theMISR.

The BIST address counter is reset only when the inputreset pin is asserted. The value is incremented after earead operation, and is allowed to rap-over when the

maximum value is reached. Memories that do not haven

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memory spaces are disabled during invalid address, sothat unknown values are not propagated to the MISRhardware.

Results

Table 1 shows a statistic of the design and the results,

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which are achieved by using the described Design-for-Test methodologies.

Number of digital signal pins (all /in / out) in scan test mode

30/29/1

Number of flipflops 7735

Number of scan chains 23

Max number of flipflops per scanchain

380

Initial stuck-at fault coverage 92%

Enhanced stuck-at fault coverage 96%

Combinational pattern only cover-age

83%

Additional sequential pattern cover-age

13%

Total number of scan pattern / loads 1200

Number of combinational pattern /loads

1000

Number of sequential pattern / loads 200

As shown in Table 1, the original test pattern set couldfully achieve the goal of a test coverage higher than 9

Total number of test vectors for scan ~600 000

Table 1

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The ATPG tool was not able to efficiently create testpattern for testing logic which surrounds embeddedRAMs within the design. Though RAM Sequentialalgorithms have been used during ATPG, a lot of faults adeclared as ATPG untestable because of limitedcapabilities of the ATPG tool to modify the address rangwhen testing logic surrounding RAMs. To workaroundthis limitation RAMs are modeled as registers with asingle address only and sequential algorithms of theATPG tool are used. The test coverage improved by 4%when using this approach.

Additional fault coverage is achieved by applying IDDqtest vectors to the device. This IDDq vectors complemeto stuck-at fault coverage. IDDq vectors are identifiedusing Synopsys PowerFault IDDq tools.

Conclusion

A new Design-for-Test strategy has been developedsuccessfully for the first SoC device of a new Motorolachip set. This strategy combined the advantages ofautomatic test pattern generation of high test coverage aefficient test pattern generation with the advantages of chip test pattern compression resulting in a methodologfor low pin count SoC devices.

Future SoC devices will use the same or similar strategieImprovements will be made on following designsregarding the initialization and reset sequence for registeand embedded RAMs. Also the Memory Built-in Self-Test for the embedded RAMs will be enhanced toimprovthe test coverage further.

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