Map

Mapping is performed by the MAP program.

During the map phase the SIMPRIM primitives from an NGD netlist are mapped on

specific device resources: LUTs, flip-flops, BRAMs and other. The output of the MAP

program is stored in the NCD format. In contains precise information about switching

delays, but no information about propagation delays (since the layout hasn't been

processed yet.

Place and route

Placement and routing is performed by the PAR program.

Place and route is the most important and time consuming step of the implementation. It

defines how device resources are located and interconnected inside an FPGA.

Placement is even more important than routing, because bad placement would make good

routing impossible. In order to provide possibility for FPGA designers to tweak

placement, PAR has a "starting cost table" option.

PAR accounts for timing constraints set up by the FPGA designer. If at least one

constraint can't be met, PAR returns an error.

The output of the PAR program is also stored in the NCD format.

Timing Constrains

In order to ensure that no timing violation (like period, setup or hold violation) will occur

in the working design, timing constraints must be specified.

Basic timing constraints that should be defined include frequency (period) specification

and setup/hold times for input and output pads. The first is done with the PERIOD

constraint, the second - with the OFFSET constraint.

Timing constraints for the FPGA project are defined in the UCF file. Instead of editing

the UCF file directly, an FPGA designer may prefer to use an appropriate GUI tool.

However, the first approach is more powerful [17].

APPENDIX –B

The 24 -bits Vedic Multiplier is designed using four 12- bit Vedic multiplier and 12-bit

Vedic Multipliers are constructed using four 6- bit Vedic Multiplier and 6-bit Vedic

Multipliers are constructed using four 3-bit Array Multipliers.

The designs of 12 x 12 Vedic Multiplier and 3 x3 Array Multiplier is shown below in

Fig.B1.a and Fig.B1.b

(a) 12-bit Vedic Multiplier design

GA0, GA1, GB1 & GB0 represent equally sized groups of inputs and A & B.

P1, P2, P3 & P4 represent partial products of size 12 bit length.

C1, C2 & C3 represents the carry propagating from one RCA to another RCA.

R represents the outputs.

The design of 6 x 6 bits Vedic Multiplier is structurally similar to that of 12 x 12 bits

Multiplier with 6 bit RCA s. The design of 6 x 6 bits Multiplier is designed using 3 x 3

Multiplier which is as shown in the Fig.B2 (b) and Fig.B2 (c) gives 3 x 3 bits

Multiplication

P11 P02 P10 P01 A0 B0

P12

P20

P21

(b) 3 x 3 Array Multiplier

A[2] A[1] A[0]

X B[2] B[1] B[0]

H

A

F

A

F

A

HA

F

A

F

AP22

P02 P01 P00 PIJ[I][J]=BIAJ

P12 P11 P10

P22 P21 P20

R5 R4 R3 R2 R1 R0

(c) 3 x 3 bits Multiplication

Figure B2 12-bit Vedic Multiplier

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