vedic multiplier 7

ANALYSIS, COMPARISON AND APPLICATION OF VEDIC MULTIPLIERS

7.2.2. Basic Multiplication Algorithm

Multiplication of two floating-point numbers is done in following steps:

Non-signed multiplication of mantissas: it must take account of the integer

part ,implicit in normalization.

The number of bits of the result is twice the size of the operands (48 bits) .

Normalization of the result: the exponent can be modified accordingly.

Addition of the exponents, taking into account the bias value of 127.

Calculation of the sign.

Eg.1 Let's suppose a multiplication of 2 floating-point numbers A and B,

where A=-18.0 and B=9.5. Binary representation of the operands: A = -10010.0; B =

+1001.1

Normalized representation of the operands: A = -1.001x2+4; B = +1.0011x2+3

IEEE representation of the operands:

A = 1 10000011 00100000000000000000000

B = 0 10000010 00110000000000000000000

( I ).Multiplication of the mantissas : We must extract the mantissas, adding a 1 as most

significant bit, for normalization

100100000000000000000000

100110000000000000000000

The 48-bit result of the multiplication is 0x558000000000 only the most

significant bits are useful: after normalization (elimination of the most significant 1),

we get the 23-bit mantissa of the result. This normalization can lead to a correction of

the result's exponent.

In our case, we get: 01 01010110000000000000000 0000000000000000000000

Department of ECE, SITAMS


II . Addition of the exponents : Exponent of the result is equal to the sum of the

operands exponents. A 1 can be added if needed by the normalization of the mantissas

multiplication (this is not the case in our example)

As the exponent fields (Ea and Eb) are biased, the bias must be removed in

order to do the addition. And then, we must to add again the bias, to get the value to

be entered into the exponent field of the result (Er):

Er = (Ea-127) + (Eb-127) + 127 = Ea + Eb – 127

In Eg.1 :Ea 10000011

Eb 10000010

-127 10000001

Er10000110

What is actually 7, the exponent of the result

( III ) Calculation of the sign of the result :

The sign of the result is given by the exclusive-or of the operands signs (Sa and Sb):

MSB(r) = MSB (a) XOR MSB (b)

In our example, we get: MSB(r) = 1 XOR 0 = 1 i.e. a negative sign

( IV ).Composition of the result :

The setting of the 3 intermediate results (sign, exponent and mantissa) gives us the

final result of our multiplication:

1 10000110 01010110000000000000000

A x B = -18.0 x 9.5 = -1.0101011x2134-127 = -10101011.0 = -171.010



7.3 DESIGN OF IEEE 32 BIT FLOATING POINT MULTIPLIER

The multiplication in an FFT process is between an positive or negative integer i.e.,

one of the input is a normalized quantity having an exponent greater than or equal to

zero and other input is a an floating point number which may be zero or an

normalized number. From the view of above requirements an IEEE 32 bit floating

point Multiplier is designed as shown in below figure 7.1.

Input A Input B

31 30 23 22 0 31 30 23 22 0

127 constant

9 bits

8bits R[47] R[46:0]

R[45:23] R[46:24]

8

Exponent unit

Flow

w

Figure 7.1 IEEE 32 Bit Floating Point Multiplier


Sign Exponent Mantissa Sign Exponent Mantissa

+

24V_MUl

Round off

0 1

Sign [31] Exponent [30:23] Mantissa[22:0]

1

0

+ -


1. Data entry unit

Here both the multiplicand and Multiplier of size 32 bit in length are unpacked

into their corresponding sign, exponent and mantissa fields to perform

operation on these fields independently.

2. Integer Multiplier Unit

Here the mantissa of the 32 bit format (i.e. the last 23 bits) of the number is given as

operands for multiplication. The explicit 1 of the format is internally generated

making it a 24 bit Multiplier unit. Hence result produced is a 48 bit value, but only 23

bits are to be extracted as per the IEEE format rules. Extraction of the valid 23 bits is

done by the multiplexer unit which is controlled on the MSB bit of the multiplication

result. The following pseudo code shows the approach used to extract 23 bits output

from the 48 bits result of unsigned integer Multiplier.

Result (47...0);

Output (22...0);

If (MSB of Result == ‘0’)

Output (22...0) = result (45...23);

Else If (MSB of Result == ‘1’)

Output (22...0) = result (46...24);

Exponent -> Exponent +1; -- Do Exponent Adjustment

3. Exponent calculation unit

This unit receives the 8 bit exponent values as operands. The exponents are analyzed

to determine normal or subnormal floating point numbers. If any one of the exponent

is zero then exponents result is zero, else if both the values are added to generate a 9

bit result. Since as per IEEE format the incoming values are biased, a constant value

of 127 is subtracted from result. Here only 8 bits are forwarded to the next stage.



MSB denotes that an exponent overflow or underflow has occurred and hence is

separated out. Next a single one is added to the result if an exponent adjust signal is

received from the Multiplier unit. Again here the MSB is checked for IEEE format

overflow or underflow.

4. Result unit

This unit receives the values calculated by various stages and combines them

in a 32 bit format .Value from the Multiplier constitutes the lower 23 bits. MSB is

obtained from XOR-ing the sign bits of individual operands. Exponent is obtained as

an 8 bit value from the exponent stage.

7.3.1 Unsigned Integer Multiplier Unit

This unit is one of the critical parts of data path. Its purpose is to do unsigned

multiplication of two incoming 24 bit mantissa (with ‘1’ appended as MSB to 23 bits

of actual mantissa’s) to obtain a 48 bit unsigned integer. In order to implement our

unsigned integer Multiplier having two 24 bits binary input strings and resultant 48-

bit output string, we used a very quick and simple technique of multiplication from

ancient Indian system of mathematics - Vedic Mathematics. The technique (formulae)

or sutra (lingo of Vedic Mathematics) used here is called “Urdhva Tiryakbhyam”.

This technique is applicable to all cases of multiplication and can be easily

extended from decimal system to binary system. The literal meaning of this formulae

or sutra is “Vertically & Cross-wise”.

The 24-bit Multipliers design based on Urdhva Tiryakbhyam Sutra contains four 12-

bit Vedic Multipliers and three 24-bit RCA to the sum four partial products and get

the final 48 bits result. The basic design idea is indicated in the below Fig7.2.



Figure 7.2 Basic design idea for 24 x 24 bits Vedic Multiplier using Urdhva

Tiryakbhyam Sutra

From the above Fig.7.2 we can say that the design of 24 x24 bits Vedic

Multiplier is structurally hierarchal and attributed with modularity, as the basic

building blocks of the design are a 3x3 Array Multiplier and 3-bit RCA. The design of

24 x 24 bits Multiplier is shown in below Fig.7.3.

Figure 7.3 24-bit Vedic Multiplier (24V) based on Urdhva Tiryakbhyam Sutra



GA0, GA1, GB1 & GB0 represent equally sized groups of inputs and A & B

P1, P2, P3 & P4 represent partial products of size 24 bit length

C1, C2& C3 represents the carry propagating from one RCA to another RCA

R represents the outputs

7.4 16 -BIT SQUARER DESIGN USING URDHVA TIRYAKBHYAM SUTRA

When both the Multiplier and multiplicand are same the multiplication becomes the

squaring of the given one number. This can be easily done using Urdhva

Tiryakbhyam Sutra.

Consider a number A=X1X0 let S be the Square which is given by

S= A x A

When Squaring is done according to Urdhva Tiryakbhyam Sutra , middle part

of the result is obtained by just doubling one of the cross-wise products indicating the

duplex principle involved in the method as shown in the below Fig.7.4

X1 X0

X1 X0

X1 x X0 : 2 x (X1 x X0) : X0 x X0

Figure 7.4 Duplex principle of Urdhva Tiryakbhyam Sutra

As two cross wise products are alike just calculating one cross- wise product

and doubling it, is sufficient in this Urdhva Tiryakbhyam method to get the total

result.

A squarer design can be done effectively with a Vedic Multiplier based on

Urdhva Tiryakbhyam Sutra [14], [15] because of the duplex principle involved in the

Sutra. The squarer design(16 x16 bit ) using Vedic Multiplier based on this sutra can

done by just removing any Multiplier block in the second stage of multiplication and



an RCA in given design .the design of the squarer is shown in the below Fig.7.5.

(obtained from the Fig.4.17)

Figure 7.4 16 bit Squarer Design using Urdhva Tiryakbhyam Sutra

GA0, GA1, GB1 & GB0 represent equally sized groups of inputs and A & B.

P1, P2, & P4 represent partial products of size 24 bit length.

C2 & C3 represents the carry propagating from one RCA to another RCA.

R represents the outputs.

In the above design it can be observed that because of the duplex principle

involved in Urdhva Tiryakbhyam Sutra there are only three 8V multiplication blocks

and only two 16-bit RCA blocks. The results are obtained within two step of addition

process.

Note: P3 and C1 are absent in the design as there is only one cross wise Multiplier

and no need of an adder block for doubling of the cross wise products.



CHAPTER -8

RESULTS

This chapter presents the simulation and synthesis reports of all the Multipliers

presented in the design and parameters namely latency, throughput ,area and power

are discussed. The FPGA used is Xilinx Spartan3E (Family), XC3S500 (Device),

FG320 (Package), -4 (Speed Grade) and Xilinx Virtex6 low power

(Family) ,XC6VLX75TL (Device ), Lff784 (Package),-1(Speed Grade).

The Simulation and Synthesis tools used for the design is ISim 12.3 V. and Xlinx-

12.3 V.

8.1 SIMULATION RESULTS

Simulation results for Vedic Multipliers, Array and Booth are shown in the below

figures .The simulation report for the 16-bit Vedic Multiplier based on Urdhva

Tiryakbhyam Sutra and Nikhilam Sutra is shown in the below Fig.8.1 &8.2.

Figure 8.1 Simulation results for 16V using Urdhva Tiryakbhyam Sutra (U.T.S)



Figure 8.2 Simulation results for 16Vusing Nikhilam Sutra (N.S.)

Simulation results for Booth and Array Multiplier are presented in the below Fig. 8.3

and Fig.8.4.


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