vedic multiplier part1
TRANSCRIPT
ANALYSIS, COMPARISON AND APPLICATION OF VEDIC MULTIPLIERS
CHAPTER 1
INTRODCUTION
1.1 INTRODUCTION
A typical processor central processing unit devotes a considerable amount of
processing time in performing arithmetic operations, particularly multiplication
operations. Multiplication is one of the basic arithmetic operations and it requires
substantially more hardware resources and processing time than addition and
subtraction.
Digital signal processing (DSP) is the technology that is omnipresent in almost
every engineering discipline. It is also the fastest growing technology of this century
and, therefore, it poses tremendous challenges to the engineering community. Faster
additions and multiplications are of extreme importance in DSP for convolution,
discrete Fourier transforms, Fast Fourier Transforms and digital filters. The core
computing process is always a multiplication routine; therefore, DSP engineers are
constantly looking for new algorithms and hardware to implement them [1].
This chapter gives the brief introduction about the various existing Multiplier designs
and finally presents the proposed concept.
1.2 LITERATURE SURVEY
There are number of techniques that to perform binary multiplication. In general, the
choice is based upon factors such as latency, throughput, area, and design complexity.
More efficient parallel approach uses some sort of array or tree of full adders to sum
partial products. Array Multiplier, Booth Multiplier and Wallace Tree Multipliers are
some of the standard approaches to have hardware implementation of binary
Multiplier which are suitable for VLSI implementation at CMOS level [1].
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ANALYSIS, COMPARISON AND APPLICATION OF VEDIC MULTIPLIERS
1.2.1 Array Multiplier
Array Multiplier [2] is an efficient layout of combinational Multiplier. Multiplication
of two binary numbers can be obtained with one micro-operation by using a
combinational circuit that forms the product bit all at once thus making it a fast way
of multiplying two numbers since only delay is the time for the signals through the
gates that forms the multiplication array.
Array Multiplier gives more power consumption as well as the optimum
number of components required ,but delay for this Multiplier is larger .It also requires
large number of gates because of which area is increased ;due to this array Multiplier
is less economical .Thus ,it is a fast Multiplier but hardware complexity is high.
The Array Multiplier design is shown in the below Fig.1.1
: Partial product inputs. : Output
: Partial sum : Carry
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ANALYSIS, COMPARISON AND APPLICATION OF VEDIC MULTIPLIERS
: Adder element
Figure 1.1 4 x 4 Array Multiplier
1.2.2 Wallace Tree Multiplier
A fast process for multiplication of two numbers were developed which consists of a
three step process of multiplying the two numbers [3] in which the bit products are
formed ,the bit product matrix is reduced to a two row matrix where sum of bit
products and the resulting rows are summed with a fast adder to produce a final
product.
Three bit signals are passed to a one bit full adder (“3W”) which is called a
three input Wallace tree circuit, and the output signal (sum signal) is supplied to the
next stage full adder of the same bit, and the carry output signal thereof is passed to
the next stage full adder of the same number of bit, and the carry output signal thereof
is supplied to the next stage of the full adder located at a one bit higher position [1].
Wallace tree is a tree of carry-save adders arranged as shown in Fig.1.2. A
carry save adder consists of full adders like the more familiar ripple adders, but the
carry output from each bit is brought out to form second result vector rather being
than wired to the next most significant bit. The carry vector is 'saved' to be combined
with the sum later. In the Wallace tree method, the circuit layout is not easy although
the speed of the operation is high since the circuit is quite irregular.
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ANALYSIS, COMPARISON AND APPLICATION OF VEDIC MULTIPLIERS
Figure 1.2 4 x4 Wallace Tree Multiplier
1.2.3 Modified Booth Multiplier
Another improvement in the Multiplier is by reducing the number of partial products
generated .The booth recording Multiplier is one such Multiplier. It scans three bits at
a time to reduce the number of partial products .these three bits are: the two bits from
present pair; and a third bit from the higher order bit of an adjacent lower order pair.
After examining each triplet of bits, the triplets are converted by Booth logic into a set
of five controls used by the adder cells in the array to control the operations
performed by the adder cells [4].
To speed up multiplication booth encoding performs several multiplications at
once [5]. From basis of booth multiplication it can be proved that addition/subtraction
operation can be skipped if the successive bits in the multiplicand are same. Thus in
most cases the delay associated with booth Multiplier is smaller than that with array
Multiplier .However the performance of Booth Multiplier for delay is input data
dependant .In worst case the delay of the booth Multiplier is on par with array
Multiplier. The high performance of booth Multiplier comes with the drawback of
power consumption as it uses large number of adder cells required that consumes
large power. The block diagram of Modified Booth Multiplier is shown in the below
Fig.1.3.
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ANALYSIS, COMPARISON AND APPLICATION OF VEDIC MULTIPLIERS
Figure 1.3 Modified Booth Block Diagram
1.3 PROBLEM FORMULATION
The problems that are to be handled in this present work is
1. To reduce area and delay.
2. To minimize power consumption.
3. To design a Multiplier with regular in structure .
1.4 OBJECTIVE OF THE THESIS
The main objective of this thesis is to analyze the multiplication sutras of Vedic
Mathematics namely Urdhva Tiryakbhyam and Nikhilam Sutras to design an
efficient Multiplier that is better in Design and performance when compared with
Array, Modified Booth and Wallace tree Multipliers.
1.5 ORGANIZATION OF THESIS
Chapter 2 presents basics of multiplication and types of Multipliers.
Chapter3 gives brief introduction to Vedic Mathematics and explains about
multiplication Sutras namely Urdhva Tiryakbhyam and Nikhilam Sutras.
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ANALYSIS, COMPARISON AND APPLICATION OF VEDIC MULTIPLIERS
Chapter 4 presents Algorithms and 16-bit Multiplier designs based on Urdhva
Tiryakbhyam and Nikhilam Sutras.
Chapter 5 Presents the Algorithms and Multiplier designs of 16-bit Array and
Modified Booth Multiplier.
Chapter 6 shows comparison between Vedic, Array and Modified Booth Multipliers
in terms of design and performance.
Chapter 7 design of Applications using Urdhva Tiryakbhyam based Vedic Multiplier
namely IEEE 32 bit floating point Multiplier and a 16-bit Squarer Design.
Chapter 8 Presents the Simulation & Synthesis reports of all the Multipliers
presented in this thesis.
Chapter9 conclusion and future work has been made using the simulation and
Synthesis reports.
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ANALYSIS, COMPARISON AND APPLICATION OF VEDIC MULTIPLIERS
CHAPTER- 2
BASIC CONCEPTS
This chapter divided mainly into two subsections. The first subsection is on the basics
of multiplication i.e. how to perform a multiplication. The second section gives the
attention about the types of Multipliers that are present to perform the multiplication
on the hardware and it mainly focuses on the parallel Multipliers.
2.1 BASICS OF MULTIPLICATION
Multiplication is complex when compared to addition and subtraction .It can be
performed in hardware or software depending on the requirements [6].The basic steps
that involve in multiplication is explained below.
The multiplication process involves generation of partial products one
for each digit of the Multiplier. These partial products are then
summed up to get the final product.
In binary number system the partial products are easily defined. If the
Multiplier is 0 then partial products is 0.if the Multiplier bit is 1, then
partial product is the multiplicand bit.
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ANALYSIS, COMPARISON AND APPLICATION OF VEDIC MULTIPLIERS
The final product is produced by summing the partial products. Before
summing up, each successive partial product is shifted one position left
relative to the preceding than the partial product.
An n-bit (multiplicand) by m-bit (Multiplier) multiplication results in
n bit partial products (n>m)
n x m product elements
n + m bit final product
2.1.1 Unsigned Binary Multiplication
The multiplication of an n-bit by m-bit unsigned binary integers A and B creates the
product P. This multiplication results in m partial products, each of which is n bits. A
partial product involves the formation of an individual computation of each bit or
ai·bj. The n partial products are added together to produce an n + m-bit product as
shown below. This operation on each partial product forms a nice parallelogram
typically called a partial product matrix.
For example, in Fig.2.1 a 4-bit by 4-bit multiplication matrix is shown. In lieu
of each value in the matrix, a dot is sometimes shown for each partial product,
multiplicand, Multiplier, and product. This type of diagram is typically called a dot
diagram and allows arithmetic designers a better idea of which partial products to add
to form the product.
P = A.B
= ( ) . ( )
= … eq. (2.1)
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ANALYSIS, COMPARISON AND APPLICATION OF VEDIC MULTIPLIERS
a3 a2 a1 a0
X b3 b2 b1 b0
a3b0 a2b0 a1b0 a0b0
a3b1 a2b1 a1b1 a0b0
a3b2 a2b2 a1b2 a0b2
a3b3 a2b3 a1b3 a0b3
p7 p6 p5 p4 p3 p2 p1 p0
Figure 2.1 4x4 Bit multiplication matrix
2.2 TYPES OF MULTIPLIERS
A Multiplier is a circuit that performs the process of multiplication which involves
generation of partial products and summing these partial products in some manner to
get the required result. Based on the types of structures Multipliers are classified into
three categories.
I .Serial or Sequential Multipliers.
II .Parallel Multipliers.
III. Serial – Parallel Multipliers
I. Sequential Multipliers
Serial or sequential Multipliers compute the product sequentially usually
utilizing storage elements so that hardware of the Multiplier is reused during iteration.
Sequential Multipliers are preferred when speed is not the main criteria in the circuit
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ANALYSIS, COMPARISON AND APPLICATION OF VEDIC MULTIPLIERS
design but the area. These are the slowest Multipliers as it uses less number of
hardware resources.
II. Parallel Multipliers
Parallel Multipliers computes the partial products in parallel (in general) by using
gates and adders to multiply am-bit number by an n-bit number to completely produce
an n + m product. Parallel Multipliers can also be pipelined to reduce the cycle time
and increase the throughput by introducing storage elements within the Multiplier.
These Multipliers are best choice when the speed is the main criteria but not the area.
These are the fastest Multipliers as it uses more number of hardware resources.
III. Serial-Parallel Multipliers
Serial parallel Multipliers are so called because m-bit Multiplier is fed in serially
(LSB first), while the n-bit multiplicand is held in parallel during the course of
multiplication. The performance of these serial parallel Multipliers is in between
parallel and serial Multipliers.
2.2.1 Designing of Parallel Multipliers
Parallel Multipliers are known for their operation speed, design of such Parallel
Multiplier depends on the basic steps that happen in the parallel Multiplier.
The three basic steps of Multipliers are listed below [6]. Although here are
implementations that can theoretically be reduced to the generation of the shifted
multiples of the multiplicand and multi-operand addition (i.e. the addition of more
than two operands), most Multipliers utilize these steps. Although there are various
different perspectives on the implementation of multiplication, its basic entity usually
is the adder.
1 Partial Product (PP) Generation - utilizes a collection of gates to generate the
partial product bits (i.e. ai· bi).
2 Partial Product (PP) Reduction - utilizes adders (counters) to reduce the
partial products to sum and carry vectors.
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ANALYSIS, COMPARISON AND APPLICATION OF VEDIC MULTIPLIERS
3 Final Carry-Propagate Addition (CPA) - adds the sum and carry vectors to
produce the product.
A well know fact to be remembered is that speed and area criteria cannot be
achieved at the same time .Increase in speed is achieved when hardware resources are
more but this consumes a large amount of area.
2.3 IMPORTANT PROPERTIES OF THE MULTIPLIER
Parallel Multipliers are used for DSP applications such as image processing, filtering,
FFT, DFT etc., as faster multiplications are needed. The choice of the Parallel
Multipliers based on different Algorithms depends on the speed of the operation of
the Multiplier which can be understood by the important Parameters Latency &
Throughput which are defined below.
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