verilog mtech programs
TRANSCRIPT
VERILOG:
BASIC GATES:
module and2(A,B,Y);
input A,B;
output Y;
assign Y = A & B;
endmodule
module tb_and2;
reg A,B;
wire Y;
and2 a2(A,B,Y);
initial
begin
#0 A=0; B=0;
#10 A=0; B=1;
#10 A=1; B=0;
#10 A=1; B=1;
#40 $finish;
end
endmodule
1
module or2(A,B,Y);
input A,B;
output Y;
assign Y = A | B;
endmodule
module tb_or2;
reg A,B;
wire Y;
or2 o2(A,B,Y);
initial
begin
#0 A=0; B=0;
#10 A=0; B=1;
#10 A=1; B=0;
#10 A=1; B=1;
#40 $finish;
end
endmodule
2
module inv1(A,Y);
input A;
output Y;
assign Y = ~A;
endmodule
module tb_inv1;
reg A;
wire Y;
inv1 i1(A,Y);
initial
begin
#0 A=0;
#10 A=1;
#20 $finish;
end
endmodule
3
module nand2(A,B,Y);
input A,B;
output Y;
assign Y = ~(A & B);
endmodule
module tb_nand2;
reg A,B;
wire Y;
nand2 nd2(A,B,Y);
initial
begin
#0 A=0; B=0;
#10 A=0; B=1;
#10 A=1; B=0;
#10 A=1; B=1;
#40 $finish;
end
endmodule
4
module nor2(A,B,Y);
input A,B;
output Y;
assign Y = ~(A | B);
endmodule
module tb_nor2;
reg A,B;
wire Y;
nor2 nr2(A,B,Y);
initial
begin
#0 A=0; B=0;
#10 A=0; B=1;
#10 A=1; B=0;
#10 A=1; B=1;
#40 $finish;
end
endmodule
5
module xor2(A,B,Y);
input A,B;
output Y;
assign Y = A ^ B;
endmodule
module tb_xor2;
reg A,B;
wire Y;
xor2 xr2(A,B,Y);
initial
begin
#0 A=0; B=0;
#10 A=0; B=1;
#10 A=1; B=0;
#10 A=1; B=1;
#40 $finish;
end
endmodule
6
module xnor2(A,B,Y);
input A,B;
output Y;
assign Y = A ~^ B;
endmodule
module tb_xnor2;
reg A,B;
wire Y;
xnor2 xnr2(A,B,Y);
initial
begin
#0 A=0; B=0;
#10 A=0; B=1;
#10 A=1; B=0;
#10 A=1; B=1;
#40 $finish;
end
endmodule
7
//FILPFLOP’s & Latches
module dff1(d,reset,clk,q);
input reset,clk,d;
output q;
reg q;
always @(posedge reset or posedge clk )
begin
if (reset)
q = 'b0;
else q = d;
end
endmodule
module dff(d,reset,clk,q);
input reset,clk;
input [3:0]d;
output [3:0]q;
reg [3:0]q;
always @(posedge reset or posedge clk )
begin
if (reset) q = 4'b0000;
else q = d;
end
endmodule
8
module tb_dff;
reg reset,clk;
reg [3:0]d;
wire [3:0]q;
dff l1(d,reset,clk,q);
initial
clk = 'b0;
always
begin
#10 clk = ~clk;
end
initial
begin
#0 reset = 'b0;#5 reset = 'b1;
#10 reset = 'b0: #40 reset = 'b1; #50 reset = 'b0;
end
initial
begin
# 0 d=4'b1110; #40 d=4'b1101; #80 d=4'b1000;
end
initial
# 180 $finish;
endmodule
9
module nandlatch(preset,clear,q,qbar);
input preset,clear;
output q,qbar;
nand2 nd2(qbar,preset,q);
d2(q,clear,qbar);
endmodule
module tb_nandlatch;
reg preset,clear;
wire q,qbar;
nandlatch n1(preset,clear,q,qbar);
initial
begin
$monitor ("%g preset = %b clear = %b q = %b qbar = %b", $time, preset, clear, q, qbar);
end
initial
begin
#0 preset = 'b1;
#10 preset = 'b0; clear = 'b1: #10 preset = 'b1;
#10 clear = 'b0; #10 clear = 'b1; #10 preset = 'b0;
end
initial
# 180 $finish;
endmodule
10
//GCD
module gcd(x1,x2,gcd);
input [3:0] x1,x2;
output [1:0]gcd;
reg [3:0]gcd;
reg [3:0] a,b;
initial
begin
a = x1;
b = x2;
end
always
begin
if ( a == b) gcd = a;
else if ( a>b ) a = a-b;
else b = b-a;
end
endmodule
11
module tb_gcd;
reg [3:0]x1,x2;
wire [3:0]gcd;
gcd d1(x1,x2,gcd);
initial
begin
#0 x1=4'b1010; x2=4'b0100;
end
initial
#50 $finish;
endmodule
12
//Registers
module pipo(d,reset,clk,load,q);
input [3:0]d;
input reset,clk,load;
output [3:0]q;
reg [3:0]q;
always @(posedge reset or posedge clk or load )
begin
if (reset)
q = 4'b0000;
else
if (load)
q <= d;
end
endmodule
tb_pipo; module
reg reset,clk,load;
reg [3:0]d;
wire [3:0]q;
pipo a1(d,reset,clk,load,q);
initial
clk = 'b0;
always CONT…..
13
begin
#10 clk = ~clk;
end
initial
begin
#0 reset = 'b0;
#5 reset = 'b1;
#10 reset = 'b0;
end
initial
begin
# 0 d=4'b1110;
#40 d=4'b1101;
#40 d=4'b1000;
end
initial
# 180 $finish;
endmodule
14
module piso(d,reset,clk,sout);
input [3:0]d;
input reset,clk;
output sout;
reg sout;
wire [3:1]w;
always @(posedge reset or posedge clk )
begin
if (reset)
w <= 4'b0000;
else
w <= d;
sout <= w[0];
end
endmodule
module sipo(d,reset,clk,q);
input d;
input reset,clk;
output [3:0]q;
reg [3:0]q;
always @(posedge reset or posedge clk )
begin
if (reset) CONT…..
15
q = 4'b0000;
else
if (load)
q <= {d,q[3:1]};
end
endmodule
module tb_sipo;
reg reset,clk;
reg d;
wire [3:0]q;
sipo a1(d,reset,clk,q);
initial
clk = 'b0;
always
begin
#10 clk = ~clk;
end
initial
begin
#0 reset = 'b0;
#5 reset = 'b1;
#10 reset = 'b0;
end
16
initial
begin
# 0 d='b1;
#40 d='b0;
#40 d='b1;
end
initial
# 180 $finish;
endmodule
module siso(d,reset,clk,q);
input d;
input reset,clk;
output q;
reg q;
reg [3:1]w;
always @(posedge reset or posedge clk )
begin
if (reset)
begin
w = 3'b000;
q = 'b0;
end CONT…..
17
else
if (clk)
begin
q <= w[1];
w[0] <= w[1];
w[1] <= w[2];
w[2] <= w[3];
w[3] <= d;
end
end
endmodule
module tb_siso;
reg reset,clk;
reg d;
wire q;
siso a1(d,reset,clk,q);
initial
clk = 'b0;
always
begin
#10 clk = ~clk;
end
initial CONT……..
18
begin
#0 reset = 'b0;
#5 reset = 'b1;
#10 reset = 'b0;
end
initial
begin
# 0 d='b1;
#40 d='b0;
#40 d='b1;
end
initial
# 180 $finish;
endmodule
19
SHIFT REG:
module shiftregs(d,reset,clk,q);
input reset,clk,d;
output q;
wire [2:0]w;
dff1 d1(w[0],reset,clk,q);
dff1 d2(w[1],reset,clk,w[0]);
dff1 d3(w[2],reset,clk,w[1]);
dff1 d4(d,reset,clk,w[2]);
endmodule
module tb_shiftregs;
reg reset,clk,d;
wire q;
shiftregs s1(d,reset,clk,q);
initial
clk = 'b0;
always
begin
#10 clk = ~clk;
end
initial
begin
#0 reset = 'b0; CONT…..
20
#5 reset = 'b1;
#10 reset = 'b0;
end
initial
begin
# 0 d='b1;
#40 d='b0;
#40 d='b1;
end
initial
# 180 $finish;
endmodule
21
module asynreset_regb(d,reset,clk,q);
input reset,clk;
input [3:0]d;
output [3:0]q;
reg [3:0]q;
always @(posedge clk or d)
begin
if (reset)
q = 4'b0000;
else if (clk)
q = d;
end
endmodule
module tb_asynreset_regb;
reg reset,clk;
reg [3:0]d;
wire [3:0]q;
asynreset_regb a1(d,reset,clk,q);
initial
clk = 'b0;
always
begin
#10 clk = ~clk; CONT…..
22
end
initial
begin
#0 reset = 'b0;
#5 reset = 'b1;
#10 reset = 'b0;
#40 reset = 'b1;
#65 reset = 'b0;
end
initial
begin
# 0 d=4'b1110;
#40 d=4'b1101;
#40 d=4'b1000;
end
initial
# 180 $finish;
endmodule
module tb_asynresetregb;
reg reset,clk;
reg [3:0]d;
wire [3:0]q; CONT….
23
asynresetb a1(d,reset,clk,q);
initial
clk = 'b0;
always
begin
#10 clk = ~clk;
end
initial
begin
#0 reset = 'b0;
#5 reset = 'b1;
#10 reset = 'b0;
end
initial
begin
# 0 d=4'b1110;
#40 d=4'b1101;
#40 d=4'b1000;
end
initial
# 180 $finish;
endmodule
24
module bidir(clk,rin,lin,s,d,q);
input [3:0]d;
input [1:0]s;
input clk,lin,rin;
output [3:0]q;
reg [3:0]q;
always @ (posedge clk)
begin
case(s)
2'b00: q <= 4'b0000;
2'b01: q <= d;
2'b10: q <= (d>>rin);
2'b11: q <= (d<<lin);
endcase
end
endmodule
module tb_bidir;
reg rin,lin,clk;
reg [3:0]d;
reg [1:0]s;
wire [3:0]q;
bidir a1(clk,rin,lin,s,d,q);
initial CONT….
25
clk = 'b0;
always
begin
#10 clk = ~clk;
end
initial
begin
#0 rin = 'b1; lin = 'b1;
// #10 rin = 'b1; lin = 'b0;
// #20 rin = 'b0; lin = 'b1;
// #30 rin =’b0; lin=’b0;
end
initial
begin
#0 s = 2'b00; #10 s = 2'b01;
#20 s = 2'b10; #30 s = 2'b11;
end
initial
begin
# 0 d=4'b1110: #40 d=4'b1101; // #40 d=4'b1000;
End
initial
# 180 $finish; endmodule
26
module loadregb(d,reset,clk,load,q);
input reset,clk,load;
input [3:0]d;
output [3:0]q;
reg [3:0]q;
always @(posedge reset or posedge clk or load or d)
begin
if (reset) q = 4'b0000;
else if (clk)
if (load) q = d;
else q = q;
end
endmodule
module loadregs(d,reset,clk,load,q);
input reset,clk,load;
input [3:0]d;
output [3:0]q;
// reg [3:0]q;
wire [3:0]w;
mux2x1 m1(q,d,load,w);
dff d1(w,reset,clk,q);
// assign q = w2;
endmodule
27
module tb_loadregs;
reg reset,clk,load;
reg [3:0]d;
wire [3:0]q;
loadregs l1(d,reset,clk,load,q);
initial
clk = 'b0;
always
begin
#10 clk = ~clk;
end
initial
begin
#0 reset = 'b0;
#5 reset = 'b1;
#10 reset = 'b0;
end
initial
begin
#0 load = 'b1;
#55 load = 'b0;
#35 load = 'b1;
end
28
initial
begin
# 0 d=4'b1110;
#40 d=4'b1101;
#40 d=4'b1000;
end
initial
# 180 $finish;
endmodule
29
module usr(d,reset,clk,rin,lin,s,q);
input reset,clk,rin,lin;
input [3:0]d;
input [1:0]s;
output [3:0]q;
reg [3:0]q;
always @ (posedge clk, posedge reset,s)
begin
if ( reset )
q = 4'b0000;
else if (clk)
case(s)
2'b00: q = d;
2'b01: q = (d << lin);
2'b10: q = (d >> rin);
endcase
end
endmodule
30
module tb_usr;
reg reset,clk,rin,lin;
reg [3:0]d;
reg [1:0]s;
wire [3:0]q;
usr s1(d,reset,clk,rin,lin,s,q);
initial
clk = 'b0;
always
begin
#10 clk = ~clk;
end
initial
begin
#0 reset = 'b0;
#5 reset = 'b1;
#10 reset = 'b0;
end
initial
begin
# 0 d=4'b1111;
// #40 d='b0;
// #40 d='b1;
31
end
initial
begin
rin = 'b1; lin ='b1;
end
initial
begin
#20 s = 2'b00;
#30 s = 2'b01;
#40 s = 2'b10;
end
initial
# 180 $finish;
endmodule
32
//Adders
module rca(x,y,cin,cout,sum);
parameter n=4;
input [n-1:0]x;
input [n-1:0]y;
input cin;
output cout;
output [n-1:0]sum;
reg [n-1:0]sum;
reg cout;
reg [n:0]c;
integer i;
always @(x or y or cin)
begin
c[0] = cin;
for (i=0;i<=n-1;i=i+1)
begin
sum[i] = x[i] ^ y[i] ^ c[i];
c[i+1] = (x[i]&y[i]) | (x[i]&c[i]) | (y[i]&c[i]);
end
cout = c[n];
end
endmodule
33
module tb_rca;
parameter n = 4;
reg cin;
reg [n-1:0]x;
reg [n-1:0]y;
wire cout;
wire [n-1:0]sum;
rca r1(x,y,cin,cout,sum);
initial
begin
# 0 x = 4'b1111; y = 4'b1111; cin = 1'b1;
# 10 x = 4'b0000; y = 4'b0101; cin = 1'b1;
# 20 $finish;
end
endmodule
34
module fa_has(A,B,CIN,S,COUT);
input A,B,CIN;
output S,COUT;
wire w1,w2,w3;
xor x1(w1, A, B);
xor x2(S,w1,CIN);
and a1(w2, A, B);
and a2(w3,w1,CIN);
or o1(COUT,w3,w2);
endmodule
module tb_faha;
reg A,B,CIN;
wire S,COUT;
fa_has F1(A,B,CIN,S,COUT);
initial
begin
#0 A=0; B=0; CIN =0;
#10 A=0; B=1; CIN =0;
#10 A=1; B=0; CIN=0;
#10 A=1; B=1;CIN=0;
#10 A=0; B=0; CIN =1;
#10 A=0; B=1; CIN =1;
#10 A=1; B=0; CIN=1;
35
#10 A=1; B=1;CIN=1;
#80 $finish;
end
endmodule
36
module fab(A,B,CIN,S,COUT);
input A,B,CIN;
output S,COUT;
reg S,COUT;
always @ (A,B,CIN)
begin
S = A ^ B ^ CIN;
COUT = (A & B) | (A & CIN) | (B & CIN);
end
endmodule
module tb_fab;
reg A,B,CIN;
wire S,COUT;
fab F1(A,B,CIN,S,COUT);
initial
begin
#0 A=0; B=0; CIN =0; #10 A=0; B=1; CIN =0;
#10 A=1; B=0; CIN=0; #10 A=1; B=1;CIN=0;
#10 A=0; B=0; CIN =1; #10 A=0; B=1; CIN =1;
#10 A=1; B=0; CIN=1; #10 A=1; B=1;CIN=1;
#80 $finish; end
endmodule
37
module fad(A,B,CIN,S,COUT);
input A,B,CIN;
output S,COUT;
assign S = A ^ B ^ CIN;
assign COUT = (A & B) | (A & CIN) | (B & CIN);
endmodule
module tb_fad;
reg A,B,CIN;
wire S,COUT;
fad F1(A,B,CIN,S,COUT);
initial
begin
#0 A=0; B=0; CIN =0;
#10 A=0; B=1; CIN =0;
#10 A=1; B=0; CIN=0;
#10 A=1; B=1;CIN=0;
#10 A=0; B=0; CIN =1;
#10 A=0; B=1; CIN =1;
#10 A=1; B=0; CIN=1;
#10 A=1; B=1;CIN=1;
#80 $finish;
end
endmodule
38
module fas(A,B,CIN,S,COUT);
input A,B,CIN;
output S,COUT;
wire w0,w1,w2,w3,w4;
begin
xor x1( w0, A , B);
xor x2(S, w0, CIN);
and a1(w1, A, B);
and a2(w2, A, CIN);
and a3(w3, B, CIN);
or o1(COUT, w1, w2, w3);
end
endmodule
module tb_fas;
reg A,B,CIN;
wire S,COUT;
fas f1(A,B,CIN,S,COUT);
initial
begin
#0 A=0; B=0; CIN =0;
#10 A=0; B=1; CIN =0;
#10 A=1; B=0; CIN=0;
#10 A=1; B=1;CIN=0; cont…..
39
#10 A=0; B=0; CIN =1;
#10 A=0; B=1; CIN =1;
#10 A=1; B=0; CIN=1;
#10 A=1; B=1;CIN=1;
#80 $finish;
end
endmodule
40
module hab(A,B,S,CY);
input A,B;
output S,CY;
reg S,CY;
always @ (A,B)
begin
S = A ^ B;
CY = A & B;
end
endmodule
module tb_hab;
reg A,B;
wire S,CY;
hab h1(A,B,S,CY);
initial
begin
#0 A=0; B=0;
#10 A=0; B=1;
#10 A=1; B=0;
#10 A=1; B=1;
#40 $finish;
end
endmodule
41
module had(A,B,S,CY);
input A,B;
output S,CY;
assign S = A ^ B;
assign CY = A & B;
endmodule
module tb_had;
reg A,B;
wire S,CY;
had h1(A,B,S,CY);
initial
begin
#0 A=0; B=0;
#10 A=0; B=1;
#10 A=1; B=0;
#10 A=1; B=1;
#40 $finish;
end
endmodule
42
module has(A,B,S,CY);
input A,B;
output S,CY;
xor x1( S, A, B);
and a1(CY, A, B);
endmodule
module tb_has;
reg A,B;
wire S,CY;
has h1(A,B,S,CY);
initial
begin
#0 A=0; B=0;
#10 A=0; B=1;
#10 A=1; B=0;
#10 A=1; B=1;
#40 $finish;
end
endmodule
43
//Multiplexers
module compmux1(a,b,q);
input [2:0]a,b;
input [2:0]q;
wire s;
function compare;
input [2:0]ina, inb;
begin
if (ina <= inb)
compare = 1;
else
compare = 0;
end
endfunction
assign s = compare(a,b);
assign q = ((a & s) | ( b & (~s)));
endmodule
module compmux(a,b,q);
input [2:0]a,b;
input [2:0]q;
function [2:0]compare;
input [2:0]ina, inb;
begin cont……
44
if (ina <= inb)
compare = ina;
else
compare = inb;
end
endfunction
assign q = compare(a,b);
endmodule
module tb_compmux;
reg [2:0]a,b;
wire [2:0]q;
compmux1 d1(a,b,q);
initial
begin
#0 a=3'b100; b=3'b011;
#10 a=3'b111; b=3'b101;
//#10 a=1; b=0;
//#10 a=1; b=1;
#40 $finish;
end
endmodule
45
module mux2x1(I0,I1,load,Y);
input [3:0] I0,I1;
input load;
output [3:0]Y;
reg [3:0]Y;
always @ (I0, I1, load)
begin
case(load)
'b0: Y = I0;
'b1: Y = I1;
endcase
end
endmodule
module muxb(I,S,Y);
input [3:0]I;
input [1:0]S;
output Y;
reg Y;
always @ (I, S)
begin
case(S)
2'b00: Y = I[0];
2'b01: Y = I[1]; cont……..
46
2'b10: Y = I[2];
2'b11: Y = I[3];
endcase
end
endmodule
module tb_muxb;
reg [3:0]I;
reg [1:0]S;
wire Y;
muxb m1(I,S,Y);
initial
begin
#0 I=4'b1010; S=2'b00;
#10 I=4'b1010; S=2'b01;
#10 I=4'b1010; S=2'b10;
#10 I=4'b1010; S=2'b11;
#10 I=4'b1001; S=2'b00;
#10 I=4'b1001; S=2'b01;
#10 I=4'b1001; S=2'b10;
#10 I=4'b1001; S=2'b11;
#80 $finish;
end
endmodule
47
module muxd(I,S,Y);
input [3:0]I; input [1:0]S;
output Y;
begin
assign Y = ((~S[1]) & (~S[0]) & I[0]) | ((~S[1]) & (S[0]) & I[1]) | ((S[1]) & (~S[0]) & I[2]) | ((S[1]) & (S[0]) & I[3]);
end endmodule
module tb_muxd;
reg [3:0]I;
reg [1:0]S;
wire Y;
muxd m1(I,S,Y);
initial
begin
#0 I=4'b1010; S=2'b00;
#10 I=4'b1010; S=2'b01;
#10 I=4'b1010; S=2'b10;
#10 I=4'b1010; S=2'b11;
#10 I=4'b1001; S=2'b00;
#10 I=4'b1001; S=2'b01;
#10 I=4'b1001; S=2'b10;
#10 I=4'b1001; S=2'b11; #80 $finish;
End endmodule
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module muxs(I,S,Y);
input [3:0]I;
input [1:0]S;
output Y;
wire w0,w1,w2,w3,w4,w5;
begin
not n1(w0,S[0]);
not n2(w1,S[1]);
and a1(w2,w1,w0,I[0]);
and a2(w3,w1,S[0],I[1]);
and a3(w4,S[1],w0,I[2]);
and a4(w5,S[1],S[0],I[3]);
or o1(Y,w2,w3,w4,w5);
end
endmodule
module tb_muxs;
reg [3:0]I;
reg [1:0]S;
wire Y;
muxs m1(I,S,Y);
initial
begin
#0 I=4'b1010; S=2'b00; cont…….
49
#10 I=4'b1010; S=2'b01;
#10 I=4'b1010; S=2'b10;
#10 I=4'b1010; S=2'b11;
// INPUT DATA CHANGED ALONG WITH SELECT PINS
#10 I=4'b1001; S=2'b00;
#10 I=4'b1001; S=2'b01;
#10 I=4'b1001; S=2'b10;
#10 I=4'b1001; S=2'b11;
#80 $finish;
end
endmodule
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//Decoders
module decb(En,I,Y);
input [2:0]I;
input En;
output [7:0]Y;
reg [7:0]Y;
always@(En, I)
begin
case({En,I})
4'b1000: begin Y[0] = 'b1; Y[7:1]=7'b0000000; end
4'b1001: begin Y[0] = 1'b0; Y[1] = 'b1; Y[7:2] = 6'b000000; end
4'b1010: begin Y[1:0] = 2'b00; Y[2] = 'b1; Y[7:3] = 5'b00000; end
4'b1011: begin Y[2:0] = 3'b000; Y[3] = 'b1; Y[7:4] = 4'b0000; end
4'b1100: begin Y[3:0] = 4'b0000; Y[4] = 'b1; Y[7:5] = 3'b000; end
4'b1101: begin Y[4:0] = 5'b00000; Y[5] = 'b1; Y[7:6] = 2'b00; end
4'b1110: begin Y[5:0] = 6'b000000; Y[6] = 'b1; Y[7] = 'b0; end
4'b1111: begin Y[6:0] = 7'b0000000; Y[7] = 'b1; end
default: Y=8'b00000000;
endcase
end
endmodule
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module tb_decb;
reg [2:0]I;
reg En;
wire [7:0]Y;
decb d1(En,I,Y);
initial
begin
#0 I=3'b000; En='b1;
#10 I=3'b001; En='b1;
#10 I=3'b010; En='b1;
#10 I=3'b011; En='b1;
#10 I=3'b100; En='b1;
#10 I=3'b101; En='b1;
#10 I=3'b110; En='b1;
#10 I=3'b111; En='b1;
# 10 I=3'b000; En='b0;
#80 $finish;
end
endmodule
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module decd(En,I,Y);
input [2:0]I;
input En;
output [7:0]Y;
assign Y[0] = En & (~I[2]) & (~I[1]) & (~I[0]);
assign Y[1] = En & (~I[2]) & (~I[1]) & I[0];
assign Y[2] = En & (~I[2]) & I[1] & (~I[0]);
assign Y[3] = En & (~I[2]) & I[1] & I[0];
assign Y[4] = En & (I[2]) & (~I[1]) & (~I[0]);
assign Y[5] = En & (I[2]) & (~I[1]) & I[0];
assign Y[6] = En & (I[2]) & I[1] & (~I[0]);
assign Y[7] = En & (I[2]) & I[1] & I[0];
endmodule
module tb_decd;
reg [2:0]I;
reg En;
wire [7:0]Y;
decd d1(En,I,Y);
initial
begin
#0 I=3'b000; En='b1;
#10 I=3'b001; En='b1;
#10 I=3'b010; En='b1; cont…..
53
#10 I=3'b011; En='b1;
#10 I=3'b100; En='b1;
#10 I=3'b101; En='b1;
#10 I=3'b110; En='b1;
#10 I=3'b111; En='b1;
#10 I=3'b000; En='b0;
#80 $finish;
end
endmodule
module decs(En,I,Y);
input [2:0]I;
input En;
output [7:0]Y;
wire w0,w1,w2;
not n1(w0,I[0]);
not n2(w1,I[1]);
not n3(w2,I[2]);
and a1(Y[0],En,w2,w1,w0);
and a2(Y[1],En,w2,w1,I[0]);
and a3(Y[2],En,w2,I[1],w0);
and a4(Y[3],En,w2,I[1],I[0]);
and a5(Y[4],En,I[2],w1,w0);
and a6(Y[5],En,I[2],w1,I[0]); cont…..
54
and a7(Y[6],En,I[2],I[1],w0);
and a8(Y[7],En,I[2],I[1],I[0]);
endmodule
module tb_decs;
reg [2:0]I;
reg En;
wire [7:0]Y;
decs m1(En,I,Y);
initial
begin
#0 I=3'b000; En='b1;
#10 I=3'b001; En='b1;
#10 I=3'b010; En='b1;
#10 I=3'b011; En='b1;
#10 I=3'b100; En='b1;
#10 I=3'b101; En='b1;
#10 I=3'b110; En='b1;
#10 I=3'b111; En='b1;
# 10 I=3'b000; En='b0;
#80 $finish;
end
endmodule
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//Encoders
module encb(En,I,Y);
input [7:0]I;
input En;
output [2:0]Y;
reg [2:0]Y;
always@(En, I)
begin
case({En,I})
9'b100000001: Y = 3'b000;
9'b100000010: Y = 3'b001;
9'b100000100: Y = 3'b010;
9'b100001000: Y = 3'b011;
9'b100010000: Y = 3'b100;
9'b100100000: Y = 3'b101;
9'b101000000: Y = 3'b110;
9'b110000000: Y = 3'b111;
default: Y='b0;
endcase
end
endmodule
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module tb_encb;
reg [7:0]I;
reg En;
wire [2:0]Y;
encb d1(En,I,Y);
initial
begin
#0 I=8'b00000001; En='b1;
#10 I=8'b00000010; En='b1;
#10 I=8'b00000100; En='b1;
#10 I=8'b00001000; En='b1;
#10 I=8'b00010000; En='b1;
#10 I=8'b00100000; En='b1;
#10 I=8'b01000000; En='b1;
#10 I=8'b10000000; En='b1;
#10 I=8'b00000000; En='b1;
#10 I=8'b10101010; En='b0;
#90 $finish;
end
endmodule
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module encd(En,I,Y);
input [7:0]I; input En;
output [2:0]Y;
assign Y[0] = En & (I[7] | I[5] | I[3] | I[1]);
assign Y[1] = En & (I[7] | I[6] | I[3] | I[2]);
assign Y[2] = En & (I[7] | I[6] | I[5] | I[4]);
endmodule
module tb_encd;
reg [7:0]I; reg En;
wire [2:0]Y;
encd d1(En,I,Y);
initial
begin
#0 I=8'b00000001; En='b1;
#10 I=8'b00000010; En='b1;
#10 I=8'b00000100; En='b1;
#10 I=8'b00001000; En='b1;
#10 I=8'b00010000; En='b1;
#10 I=8'b00100000; En='b1;
#10 I=8'b01000000; En='b1;
#10 I=8'b10000000; En='b1;
#10 I=8'b00000000; En='b0; #80 $finish;
End endmodule
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module encs(En,I,Y);
input [7:0]I;
input En;
output [2:0]Y;
wire [2:0]w;
or o1(w[0],I[7],I[5],I[3],I[1]);
or o2(w[1],I[7],I[6],I[3],I[2]);
or o3(w[2],I[7],I[6],I[5],I[4]);
and a1(Y[0],En,w[0]);
and a2(Y[1],En,w[1]);
and a3(Y[2],En,w[2]);
endmodule
module tb_encs;
reg [7:0]I;
reg En;
wire [2:0]Y;
encs d1(En,I,Y);
initial
begin
#0 I=8'b00000001; En='b1;
#10 I=8'b00000010; En='b1;
#10 I=8'b00000100; En='b1;
#10 I=8'b00001000; En='b1; cont…..
59
#10 I=8'b00010000; En='b1;
#10 I=8'b00100000; En='b1;
#10 I=8'b01000000; En='b1;
#10 I=8'b10000000; En='b1;
#10 I=8'b00000000; En='b0;
#80 $finish;
end
endmodule
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//Counters
module syncounter(reset,clk,q);
input reset,clk;
output [3:0]q;
reg [3:0]q;
always @(posedge reset or posedge clk)
begin
if (reset)
q = 4'b0000;
else if (clk)
q = q+1;
end
endmodule
module tb_syncounter;
reg reset,clk;
wire [3:0]q;
syncounter s1(reset,clk,q);
initial
clk = 'b0;
always
begin
#10 clk = ~clk;
end
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initial
begin
reset = 0;
#5 reset = 1;
#10 reset = 0;
end
initial
# 180 $finish;
endmodule
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module updown(direction,reset,clk,q);
input direction,reset,clk;
output [3:0]q;
reg [3:0]q;
always @(posedge reset or posedge clk)
begin
if (reset)
q <= 4'b0000;
else if (clk)
begin
if (direction)
q <= q+1;
else
q <= q-1;
end
end
endmodule
module tb_updown;
reg direction,reset,clk;
wire [3:0]q;
updown s1(direction,reset,clk,q);
initial
clk = 'b0; cont….
63
always
begin
#10 clk = ~clk;
end
initial
begin
reset = 0;
#5 reset = 1;
#10 reset = 0;
end
initial
begin
direction = 0;
#100 direction = 1;
#100 direction = 0;
end
initial
# 180 $finish;
endmodule
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//User Defined Primitive
primitive udp_or(y,a,b);
output y;
input a,b;
table
? 1 : 1;
1 ? : 1;
0 0 : 0;
endtable
endprimitive
module udpor(Y,A,B);
input A,B;
output Y;
udp_or(y,a,b);
endmodule
module tb_udpor;
reg A,B;
wire Y;
udp_or d1(Y,A,B);
initial
begin
#0 A=0; B=0;
#10 A=0; B=1; cont……
65
#10 A=1; B=0;
#10 A=1; B=1;
#40 $finish;
end
endmodule
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// Traffic light controller
`timescale 1ns / 1ps
module trafficsignal(hwy,cntry,x,clock,clear);
output [1:0] hwy,cntry;
//2 bit op for 3 states of sig
//green,yell,red
reg [1:0] hwy,cntry;
//op sig as reg
input x;
input clock,clear;
parameter red=2'd0,
yellow=2'd1,
green=2'd2;
parameter s0=3'd0,s1=3'd1,s2=3'd2,s3=3'd3,s4=3'd4;
reg[2:0] state;
reg [2:0] next_state;
always @(posedge clock)
if (clear)
state<=s0;
else
state<=next_state;
always @(state)
begin cont…..
67
hwy=green;
cntry=red;
case(state)
s0: ;
s1:hwy=yellow;
s2:hwy=red;
endmodule
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