Vertex 2008July 28–August 1, 2008, Utö Island,

Sweden

CMOS pixel vertex detector at STAR

Michal Szelezniakon behalf of:LBNL: E. Anderssen, L. Greiner, H. Matis, T. Stezelberger, X. Sun, Ch. Vu, H. Wieman

IPHC: A. Besson, A. Brogna, G. Claus, C. Colledani, A. Dorokhov, G. Doziere, W. Dulinski, M.Goffe, D. Grandjean, A. Himmi, Ch. Hu, K. Jaaskelainen, M. Koziel, F. Morel, A.Shabetai, I.Valin, M. Winter

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

22

Outline

PIXEL detector as a part of the Heavy Flavor Tracker

PIXEL detector characteristics

MAPS as the sensor technology for PIXEL

Development of MAPS for PIXEL

Development of the readout electronics for PIXEL

Summary and future work

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

33

HFT and PIXEL detector

TPC points at the SSD ~ 1 mm SSD points at the IST ~ 300 µm IST points at the PIXEL ~ 250 µm PIXEL points at the vertex <30 µm

PIXEL at 2.5 and 8 cm

IST at 14 cm

SSD at 23 cm

Heavy Flavor Tracker (HFT)

Resolve displaced vertices (>60 µm)

Heavy Flavor Tracker (HFT) will extend the physics reach of the STAR experiment for precision measurement of the yields and spectra of particles containing heavy quarks

The key requirement for the physics program is to:

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

44

Two layers at 2.5 & 8 cm radii Sensor spatial resolution < 10 μm Coverage 2π in φ and |η|<1 Over 400 M pixels 0.28 % radiation length/layer (VXD3 0.4%, ALICE pixel detector ~1%) Thinned silicon sensors (50 μm thickness) Air cooled Power dissipation ~100 mW/cm2

Quick extraction and detector replacement Stability and insertion reproducibility within a 30 μm window Integration time <200 μs (L=8×1027) Radiation environment at the level of up to 300 krad/year and 10×1012/cm2

Neq /year

PIXEL detector characteristics

Very challenging mechanical and sensor design

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

55

PIXEL detector design

Ladder with 10 MAPS sensors (~ 2×2 cm each)

MAPSRDObuffers/drivers

4-layer kapton cable with aluminium traces

Mechanical support with kinematic mounts

2 layers

Cabling and cooling infrastructure

Detector extraction at one end of the cone

New beryllium beam pipe (0.5 mm thickness, 2 cm radius)

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

66

Monolithic Active Pixel SensorsProperties:

Standard commercial CMOS technology Sensor and signal processing are integrated in

the same silicon wafer Signal is created in the low-doped epitaxial layer

(typically ~10-15 μm) → MIP signal is limited to <1000 electrons

Charge collection is mainly through thermal diffusion (~100 ns), reflective boundaries at p-well and substrate → cluster size is about ~10 pixels (20-30 μm pitch)

100% fill-factor Only NMOS transistors inside the pixels

MAPS technology is an attractive choice for the PIXEL detector

MAPS pixel cross-section (not to scale)

MAPS and competition MAPS Hybrid Pixel

SensorsCCD

Granularity + - +

Small material budget + - +

Readout speed + ++ -

Radiation tolerance + ++ -

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

77

Sensor prototypes for Pixel

MimoSTAR 2 prototype in AMS 0.35 technology

– 128 × 128 pixel (30 µm pitch)

– 4 ms integration time

– Analog readout– Radiation tolerant

diode design (elimination of the thick oxide from the vicinity of the charge collecting diode)

– JTAG controlled configuration

MAPS show promising performance for the PIXEL detector

Based on tests of several different prototypesS/N>12 allows detection efficiency >99.6%

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

88

MimoSTAR3 – large area prototype Extension of MimoSTAR 2 AMS 0.35 Analog readout Pixel array 320 × 640 30 µm pixel pitch 2 parallel outputs 10 parallel sub-arrays Integration time 2 ms

Low fabrication yield in the first run

Dead pixels in the center of the sensors

Mean pixel values

Edge Center

No contact

Two fix the problem 2 masks were modified to reduce:

– Surface of active area – Density of metal 1 layer

Yield improved from <20% for old layout to >80% for the new layout

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

99

Transition from analog to binary readout

Typical sensor readout– Raster scan – Charge integration time = array

readout time– Multiplexing sub-arrays decreases

integration time

Column parallel readout architecture– All columns are readout in parallel and

then multiplexed to one output– Charge integration time = column

readout time

On-chip data sparsification overcomes limitation in the readout speed

Analog readout – simpler architecture but ultimately slower readoutDigital readout – offers increased speed but requires on-chip discriminators or ADCs

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

1010

Prototypes Mimosa 8 and Mimosa 16 developed by IPHC and DAPNIA feature binary readout – a major step towards on-chip data sparsificaiton

VREF1 PWR_ON

MOSCAP

RESET

VREF2 VDD

PWR_ON

VR1VR2

READ

CALIB

ISF

PIXEL

COLUMN CIRCUITRY

OFFSET COMPENSATED COMPARATOR

(COLUMN LEVEL CDS)

SOURCEFOLLOWER

latch

Q

Q_

READ

READ

+

+

+

+

+ +

-

- -

-

LATCH

CALIB

READ

Sensor with binary readout

Mimosa 8/16 (TSMC 0.25/AMS 0.35) 128 × 32 pixels with 25 μm pitch In-pixel CDS Column level offset-compensated discriminators

Mimosa 8/16 pixel and column level circuitry

Y. Degerli et al, IEEE TNS, vol 53, no 6, 2006, pp 3949 - 3955 Y. Degerli et al, IEEE TNS, vol 52, no 6, 2005, pp 3186 - 3193

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

1111

Mimosa 16 performance

Meets PIXEL requirements

extension of Mimosa 16 to full reticle– Integration time of 640 µs– Continuous binary readout of all pixels

This chip is ready for production

Phase-1 prototype for PIXEL

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

1212

Final sensor for the PIXEL detector Phase-1 combined with on-chip zero

suppression

On-chip zero suppression has been successfully implemented and tested at IPHC as a small size prototype

~ 3 mm

The prototype zero-suppression circuitry works up to 115 MHz

Radiation hardness tests are in preparation

S0 S1 S15

N Hits N Hits

-

Col

umn

-0

Col

umn

-63

Col

umn

-0

Col

umn

-63

Col

umn

-63

Col

umn

-0

A/D A/D… A/D A/D A/D A/D

…

…

…

…

…

…

…

…

S1 S2 Sn

Memory with 600 states stored and serial transmission

Col

umn

-0

Col

umn

-63

Col

umn

-0

Col

umn

-63

Col

umn

-63

Col

umn

-0

A/D A/D… A/D A/D A/D A/D

…

…

…

…

…

…

…

…

(6 states)

Priority Look-Aheadalgorithm

Selection of 9 states among n x 6 states for each row

(6 states)

Priority Look-Aheadalgorithm

(6 states)

Priority Look-Aheadalgorithm

Memory 1

Memory 2

core of the zero suppression

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

1313

PIXEL detector readout Coupled nature of readout and sensor development

2011 (planned)

Install final detector

2010 (planned)

Install 3-module engineering prototype (based on Phase1)

First prototypes in hand and tested

Pixel

Sensors CDS

ADC Data

sparsification

readout

to DAQ

analogsignals

Complementary detector readout

MimoSTAR sensors 4 ms integration time

Ultimate sensors < 200 μs integration time

analog

digital digital signals

Disc.

CDS

Phase-1 sensors 640 μs integration time

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

1414

Telescope and readout prototype in STARLeo Greiner presented MimoSTAR2-based telescope prototype with prototype PIXEL readout system at Vertex 2007

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

1515

Readout system - physical layout

10 parallel independent readout modules (4 ladders per module)

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

1616

LVDS data transfer The final detector system is expected

to have LVDS data transfers at the maximum rate of 160 MHz

Ladder mock-up with 1-to-4 LVDS fanout buffers

Mass termination board + LU monitoring

Virtex-5 based RDO system with RORC link to PC

Virtex-5 individual IODELAY was adjusted for each channel

Buffered path 160 MHz 2.3 m cables

Bit Error Rate < 10-14

42 AWG wires

24 AWG wires

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

1717

Summary Full reticle 2 × 2 cm Phase-1 should be available at the end of this

year – detector engineering prototype (3/10 of the complete detector) will be

constructed and should allow to perform physics measurements in 2010

The readout concept has been validated with LVDS readout test and the full readout system production prototypes are being developed

New prototypes with on-chip discriminators are capable of the required S/N ratio for >99% detection efficiency but with a limited safety margin

Limited S/N makes the sensors susceptible to radiation damage– ionizing damage increase of leakage current and noise– non-ionizing damage charge losses in bulk

Resistance to radiation damage level that can be expected in the STAR environment with the final luminosity (8×1027 /cm2/s ) is being carefully studied.

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

1818

Possible significant improvement of radiation tolerance can be achieved with different fabrication technologies:

– Graded substrate and deep p-implants simulations indicate reduction of charge collection time from ~100

ns to ~20 ns First prototypes are under test

– High resistivity substrate On-going investigation of technology with pin diodes 1 k cm would allow ~10 µm depletion of epi layer (~14 µm total

thickness) with 3-5 V A prototype sensor has been submitted for production Results should be available next year – in time for Vertex 2009

On-going and future development

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

1919

Thank you for your attention

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

2020

Backup slides

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

2121

~100 µm

Extend the physics reach of the STAR experiment for precision measurement of the yields and spectra of particles containing heavy quarks:

– Study charm and beauty energy losses to test pQCD in a hot and dense medium at RHIC

– Charm flow to test thermalization at RHIC– Direct reconstruction of charm

Detect charm decays with small cτ, including D0 and Λc+

Method:

Heavy Flavor Tracker @ STAR

Resolve displaced vertices (>60 µm)

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

2222

MimoSTAR3 – large area prototype Extension of MimoSTAR 2 AMS 0.35 Analog readout Pixel array 320 × 640 2 parallel outputs 10 parallel sub-arrays Integration time 2 ms

10.7 mm

19.3 mm

Low fabrication yield in the first run

Dead pixels in the center of the sensors

Mean pixel values

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

2323

MimoSTAR3 – low yield investigation

No problems were observed on the small surface area prototypes on the same wafer

Vias are the same size Different distance between metal layers

Corner Center

Metal 4

Metal 3

Metal 2

Metal 1

No contact

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

2424

MimoSTAR3 - layout modification

Yield improved from <20% for old layout to >80% for the new layout

old layout vs.

new layout

2 masks were modified to reduce:– Surface of active area – Density of metal 1 layer (GND)

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

2525

Readout path

10 parallel independent readout modules

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

2626

Fast, column-parallel architectureVREF1 PWR_ON

MOSCAP

RESET

VREF2 VDD

PWR_ON

VR1VR2

READ

CALIB

ISF

PIXEL

COLUMN CIRCUITRY

OFFSET COMPENSATED COMPARATOR

(COLUMN LEVEL CDS)

SOURCEFOLLOWER

latch

Q

Q_

READ

READ

+

+

+

+

+ +

-

- -

-

LATCH

CALIB

READ

PWR_ON

RESET

READ

CALIB

LATCH

CDS at column level (reduces Fixed Pattern Noise below temporal noise)

122 , inrefCsfrefCALIB VVVVVV

)( 122

122

2

ininsfref

inrefsfin

sfCinREAD

VVVV

VVVV

VVVV

VREAD,CALIB

VCVin1,2

12122

2_ 1 offRREADoffREADS VVVAV

AA

V

READSoffoffRCALIBout VVVVVAAV _21112

1212 RRREADCALIBout VVVVAAV

VS_READ

A1 Voff1 A2, Voff2

Developed in IPHC - DAPNIA collaboration

Michal Szelezniak 17th International Workshop on Vertex detectors, July 28–August 1, 2008

2727

LVDS data transfer – test results

Buffered path 160 MHz 1.0 m cables Un-buffered path 160 MHz 1.0 m cables

Buffered path 160 MHz 2.3 m cables

Bit Error Rate < 10-14