very high speed digital subscriber line (vdsl)
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© UNIVERSITY of NEW HAMPSHIRE INTEROPERABILITY LABORATORY
VDSL MCM SimulationVDSL MCM Simulation
Tim ClarkVDSL Consortium
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VDSL MCM Simulation
Presentation ContentPresentation Content Simulation Overview Constellation Encoding and Multi-Carrier
Modulation Reed-Solomon Forward Error Correction Convolutional Interleaving Channel Model Equalization (TEQ and FEQ) Bit Allocation Training
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VDSL MCM Simulation
Simulation OverviewSimulation Overview Simulation done with code in MATLAB Simulates a DSLAM transmitter, twisted-pair
channel, and remote receiver Simulation process:
* Generate a frame of random binary data* Encode and modulate at the transmitter* Apply channel attenuation and add crosstalk to signal* Equalize, demodulate, and decode at the receiver* Compare binary data and CRC* Calculate BER and FER
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VDSL MCM Simulation
Block DiagramBlock Diagram
RandomBinaryData
CRCGeneration
CRCGeneration
Reed-SolomonEncoding
Reed-SolomonEncoding
ConvolutionalInterleaving
QAMConstellationEncoder
IFFT CyclicExtension
Scrambler
Scrambler
CRCCheck
CRCCheck
Reed-SolomonDecoding
Reed-SolomonDecoding
StripCyclic
ExtensionFFT
ConvolutionalDe-Interleaving
Descrambler
Descrambler
QAMConstellationDecoder
SyndromeDetector
SyndromeDetector
Twisted-PairChannel
Crosstalk
Transmitter
Receiver
TEQ&
FEQ
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VDSL MCM Simulation
Fast and Slow Data PathsFast and Slow Data Paths Data is split evenly between an interleaved (slow)
path and a non-interleaved (fast) path Interleaving provides resistance to burst errors but
introduces latency Each path has a separate CRC, scrambler, and FEC Data is joined together before modulation
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VDSL MCM Simulation
Cyclic Redundancy Check (CRC)Cyclic Redundancy Check (CRC) CRC Generation Algorithm:
1. Left-shift the input by 8 bits2. Divide by the CRC generator polynomial
G(D) = D8 + D4 + D3 + D2 + 13. The remainder is the checksum and is appended to the frame
CRC Check Algorithm1. Remove checksum from received frame2. Use same algorithm to calculate checksum for received frame3. If the two agree, set the syndrome to 0
Otherwise, set the syndrome to 1
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VDSL MCM Simulation
Scrambler/DescramblerScrambler/Descrambler
Scrambler output is the sum of the current bit and the 18th and 23rd delayed bits:
x(n) = m(n) + m(n-18) + m(n-23) Addition is modulo-2, equivalent to exclusive-OR
+ D18 D23D
+
... ...m(n)
x(n)
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VDSL MCM Simulation
Forward Error CorrectionForward Error Correction VDSL uses Reed-Solomon coding for FEC A RS codeword contains N=K+R bytes:
* N = codeword length* K = message length* R = redundancy length
RS code parameters are specified as (N,K)* The simulation uses either (240,224) or (144,128)* RS coding can correct R/2 byte errors per codeword
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VDSL MCM Simulation
Reed-Solomon CodingReed-Solomon Coding R redundant bytes are calculated by dividing the K
message bytes by a generator polynomial over the Galois Field GF(256)
MATLAB has built-in functions for encoding and decoding RS codewords
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VDSL MCM Simulation
InterleavingInterleaving VDSL uses a convolutional interleaving algorithm
to protect data against burst errors by spreading them out over multiple Reed-Solomon codewords
Interleaving parameters:* I = number of interleaver branches* M = incremental delay* D = interleaving depth = M x I + 1
Can correct byte errors Introduces a delay of M x I x (I-1) bytes
NIR2
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VDSL MCM Simulation
Convolutional Interleaving (1)Convolutional Interleaving (1) Interleaver has I branches of length M x (I-1) + 1 Algorithm:
1. Interleaver memory is initialized with zeros2. Input data is read into interleaver I bytes at a time3. Each interleaver branch is delayed in increments of M4. Data is output from front of interleaver5. Left-shift interleaver memory
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VDSL MCM Simulation
Convolutional Interleaving (2)Convolutional Interleaving (2)
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VDSL MCM Simulation
QAM ConstellationsQAM Constellations A sequence of bits is mapped to a complex number
representing a constellation point Can use 1 to 15 bits per constellation point Corresponds to constellation size of 21 to 215 = 2 to 32K
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VDSL MCM Simulation
DMT ModulationDMT Modulation Discrete Multi-Tone Uses 4095 4-kHz bands Each band can carry a different number of bits Construct an array of 4096 complex numbers Take IFFT Result is the DMT signal Demodulated by the FFT, reverse-mapping
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VDSL MCM Simulation
Cyclic Extension (1)Cyclic Extension (1) Eliminates inter-symbol interference Simplifies equalizers Beginning samples are added to the end, last
samples are added to the beginning, then whole thing is windowed
At receiver, cyclic extension is stripped from received symbol
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VDSL MCM Simulation
Cyclic Extension (2)Cyclic Extension (2)
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VDSL MCM Simulation
Channel ModelChannel Model Channel transfer function is calculated using ABCD
modeling IFFT transfer function to get channel impulse
response Convolve DMT signal with impulse response to get
attenuated signal Add crosstalk
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CrosstalkCrosstalk VDSL self-crosstalk is added to signal Simulates up to 20 other VDSL modems using the
same spectrum operating in the same binder group
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VDSL MCM Simulation
TrainingTraining At beginning of simulation, modems perform a
training session that involves discovery of the channel and bit allocation
Channel discovery for calculating equalizer coefficients
Channel equalizers designed to negate channel effects
Bit allocation determines how many bits are carried on each tone
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VDSL MCM Simulation
Bit AllocationBit Allocation Shannon Capacity formula:
Number of bits on each tone is calculated from the SNR corresponds to a BER of 10-7
Bits are adjusted such that total number of bits fits an integer number of Reed-Solomon codewords
Creates a bit allocation profile that tells both receivers how many bits are modulated on each tone, i.e. what constellation size to map to
55.9
)/1(log2/1 2 SNRb
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VDSL MCM Simulation
Frequency-Division DuplexingFrequency-Division Duplexing Upstream and Downstream are multiplexed by
assigning each tone to a direction Although 4096 tones extend beyond 17 MHz,
current frequency plans only allocate transmission up to 12 MHz
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Spectrum Allocation PlansSpectrum Allocation Plans
138 kHz 5.3 MHz 8.4 MHz3.7 MHz 12 MHz
138 kHz 5.2 MHz 7 MHz2.9 MHz 12 MHz
Frequency Plan 998
Frequency Plan 997
Downstream
Upstream
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VDSL MCM Simulation
Time-domain equalization (TEQ)Time-domain equalization (TEQ) Designed to reduce the impulse response of the
channel Eliminates ISI Send a signal known to both modems Wiener filter block-data formulation Result is an FIR filter
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VDSL MCM Simulation
Frequency-domain equalization (FEQ)Frequency-domain equalization (FEQ) Negates combination of the channel and TEQ filter Channel attenuation for each tone is calculated by
sending a known signal and comparing to the received signal
Channel TEQ FEQ
=1
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VDSL MCM Simulation
ReferencesReferencesANSI / T1E1
* T1.424 Trial Standard Multi Carrier Modulation: Part III