vhdl mealy and moore model 순차논리회로 (fsm) 의 종류 - mealy 순차회로 : 회로의...
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9YABS21muxMULTIPLEXER
VHDL Mealy and Moore model 순차논리회로 (FSM) 의 종류 - Mealy 순차회로 : 회로의 출력이 현재상태와 현재입력에 의해 결정
Next State
Logic
(combinational)
Current stateRegister
(sequential)Inputs
Outputs
Current State
Output
Logic
(combinational)
Next State
Asynchronous reset
9YABS21muxMULTIPLEXER
VHDL Mealy and Moore model
- Mealy 순차회로 : 회로의 출력이 현재상태와 현재입력에 의해 결정
Y=(A+B)x′ , A(t+1)=Ax + Bx, B(t+1)=A′x
9YABS21muxMULTIPLEXER
VHDL Mealy and Moore model 순차논리회로 (FSM) 의 종류 - Moore 순차회로 : 회로의 출력이 현재상태에 의해서만 결정
Next State
Logic
(combinational)
Current stateRegister
(sequential)Inputs
Outputs
Current State
Output
Logic
(combinational)
Next State
Asynchronous reset
9YABS21muxMULTIPLEXER
VHDL Mealy and Moore model - Moore 순차회로 : 회로의 출력이 현재상태에 의해서만 결정
Y=AB, TA=Bx, TB=x
9YABS21muxMULTIPLEXER
VHDL Mealy and Moore model
다음의 회로는 Mealy 인가 Moore 인가 ?
clock
(1)
LogicOutput
Reg.input
clock
output
(2)
InputReg.
Logic
input
output
(3)
InputReg.
9YABS21muxMULTIPLEXER
FSM 을 위한 VHDL 기술은 두 부분으로 나누어 진다 .
1. A Combinatorial part – input signal 이 바뀔 때 마다 동작한다 .
(Sensitivity list - input signals, state) comb : process (input_signals, state) ... if (input = ”01”) then a.output:= ..... a.next_state:= ....
2. A sequential part – Clock 이 바뀔 때 마다 동작한다 .
(Sensityivity list - only clock or clock, reset) seq : process(clk) ... If (clk’event) and (clk = ’1’) then...
VHDL Mealy and Moore model
VHDL 구문
9YABS21muxMULTIPLEXER
VHDL Mealy and Moore model
Next State
Logic
(combinational)
Current stateRegister
(sequential)Inputs
Outputs
Current State
Output
Logic
(combinational)
Next State
2 개 (blue and red) 혹은 3 개의 Process (red) 문으로 회로를 표현 가능
9YABS21muxMULTIPLEXER
VHDL Mealy and Moore model
- Process 문을 이용하여 Logic 및 Register 의 동작을 표시
- State 의 데이터 type 는 열거형 (enumeration type) 사용
- 초기상태를 반드시 규정 : reset conditions
- next state 로 의 전이 (transition) 은 case 문사용
- 입력 조건은 if~else 을 사용
-모든 조건에 대하여 상태 출력을 할당
- feedback 엔 signal 과 변수 모두 사용 가능
FSM 을 위한 VHDL 기술 방법 .
9YABS21muxMULTIPLEXER
VHDL Mealy and Moore model
Sequential description
ARCHITECTURE behave OF d_register ISBEGIN PROCESS(clk) BEGIN IF clk’EVENT AND (clk=‘1’) THEN q<=D; END IF; END PROCESS;END behave;
9YABS21muxMULTIPLEXER
VHDL Mealy and Moore model
CLK 의 표현 방법
1. IF 문을 이용한 CLK 의 표현
if SIGNAL’event and SIGNAL = ’1’ -- rising edgeif NOT SIGNAL’stable and SIGNAL = ’1’ -- rising edgeif SIGNAL’event and SIGNAL = ’0’ -- falling edgeif NOT SIGNAL’stable and SIGNAL = ’0’ -- falling edge
2. Wait 문을 이용한 CLK 의 표현
wait until CLK = ’1’; -- rising edge triggered wait until CLK = ’0’;--falling edge triggered
9YABS21muxMULTIPLEXER
VHDL Mealy and Moore model
In general, the following guidelines apply when we describe the clock :
Synchronous processes (processes that compute values only on clock edges) must be sensitive to the clock signal. Use wait-until or if.
Asynchronous processes (processes that compute values on clock edges and when asynchronous conditions are TRUE) must be sensitive to the clock signal (if any), and to inputs that affect asynchronous behavior. Use “if” only.
9YABS21muxMULTIPLEXER
VHDL Mealy and Moore model
Mealy Machine Example
S0
S1
0/00
1/10
1/00
0/01
입력 : I 출력 : Y1, Y2
2 개의 process 문을 이용하여 표현
9YABS21muxMULTIPLEXER
Library ieee; Use ieee.std_logic_1164.all;ENTITY Meal ISPORT(clk : IN STD_LOGIC; reset : IN STD_LOGIC; I : IN STD_LOGIC; Y1, Y2 : OUT STD_LOGIC);END Meal;
ARCHITECTURE a OF Meal ISTYPE STATE_TYPE IS (s0, s1);SIGNAL state: STATE_TYPE;
BEGINPROCESS (clk, reset)BEGIN IF reset = '0' THEN state <= s0; ELSIF clk'EVENT AND clk = '1' THEN CASE state IS
WHEN s0 => IF I='1' THEN state <= s1; ELSE state <= s0; END IF;
WHEN others => IF I='0' THEN state <= s0; ELSE state <= s1; END IF;
END CASE;
VHDL Mealy and Moore model
9YABS21muxMULTIPLEXER
END IF;END PROCESS;
PROCESS(state, I) BEGIN if( state= s0 and I='1') then Y1 <='1'; else Y1 <='0'; end if; if( state= s1 and I='0') then Y2 <='1'; else Y2 <='0'; end if; END PROCESS;END a;
VHDL Mealy and Moore model
9YABS21muxMULTIPLEXER
S0000
S1010
0
0
1
Moore Machine Example
VHDL Mealy and Moore model
S2101
1
1
입력 : I 출력 : Y(2:0)
2 개의 process 문을 이용하여 표현
9YABS21muxMULTIPLEXER
VHDL Mealy and Moore model Library ieee; Use ieee.std_logic_1164.all;ENTITY Moor ISPORT(clk : IN STD_LOGIC; reset : IN STD_LOGIC; I : IN STD_LOGIC; y : OUT STD_LOGIC_vector(2 downto 0));END Moor;
ARCHITECTURE a OF Moor ISTYPE STATE_TYPE IS (s0, s1,s2);SIGNAL state: STATE_TYPE;
BEGINPROCESS (clk, reset)BEGIN IF reset = '0' THEN state <= s0; ELSIF clk'EVENT AND clk = '1' THEN CASE state IS
WHEN s0 => IF I='1' THEN
state <= s1;ELSE
state <= s0; END IF;
9YABS21muxMULTIPLEXER
WHEN s1 => IF I='1' THEN
state <= s2;ELSE
state <= s1; END IF;
WHEN others => IF I='1' THEN
state <= s0;ELSE
state <= s2; END IF;
END CASE; END IF;END PROCESS;
PROCESS (state)BEGIN
CASE state ISWHEN s0 =>
y <= "000";WHEN s1 =>
y <= "010";WHEN others =>
y <= "101"; END CASE;END PROCESS;END a;
VHDL Mealy and Moore model