vhdl module5 rev e - wpiusers.wpi.edu/~rjduck/vhdl module5 rev e.pdf · jim duckworth, wpi 2...

Jim Duckworth, WPI Sequential Logic - Module 51

Sequential Logic

Module 5


Latches and Flip-Flops

• Implemented by using signals in IF statements that are not

completely specified

• Necessary latches or registers are inferred by the synthesis

tool.

• Transparent Latch

• Edge-triggered flip-flop

• Reset

– Asynchronous

– Synchronous

• Counters

• Shift Registers

• Finite State Machines (Module 6)


Combinational Logic - review

• All input signals specified in sensitivity list

• All conditions evaluated

PROCESS (a, b, sel)

BEGIN

IF sel = ‘1’ THEN

y <= a;

ELSE

y <= b;

END IF;

END PROCESS;

y

sel

a

b


Transparent (Flow-Through) Latch

• IF statement not completely specified - missing ELSE part

• Output follows input when enable high but stores old value

when enable goes low

PROCESS (enable, d)

BEGIN

IF enable = ‘1’ THEN

q <= d;

END IF;

END PROCESS;

q

d

enable

enable

d

q


• Positive edge-triggered flip flop

PROCESS (clk)

BEGIN

IF clk’EVENT AND clk = ‘1’ THEN

q <= d;

END IF;

END PROCESS;

Edge-Triggered Flip-Flop

q

d

clk

d

clk

q


Flip-flop (cont’d)

• clk’EVENT is an example of a function signal attribute

– returns TRUE if event (change in value) occurred on signal

– can be used to detect an edge

– when combined with a further test (AND clk = ‘1’) we can

determine that it was a rising edge


Latch and Flip-Flop


Clocked Process - general format

ARCHITECTURE behav OF flip-flop IS

BEGIN

PROCESS (clock signal, [asynchronous signals])

BEGIN

IF asynchronous conditions THEN

sequential statements for reset or preset;

ELSIF clock_edge THEN

sequential statements for clock_edge;

END IF;

END PROCESS;

END behav;

• Sensitivity list must always include clk and asynchronous

signals

• All signal assignments in process result in flip-flops


Adding asynchronous clear and preset signals

ENTITY dtype IS

PORT(clk, d, clr, pre : IN std_logic;

q, n_q : OUT std_logic);

END dtype;

ARCHITECTURE behav OF dtype IS

SIGNAL temp_q : std_logic; -- internal signal

BEGIN

PROCESS (clk, clr, pre)

BEGIN

IF clr = ‘1’ THEN -- clear operation

temp_q <= ‘0’;

ELSIF pre = ‘1’ THEN -- preset operation

temp_q <= ‘1’;

ELSIF clk’EVENT AND clk = ‘1’ THEN -- clock

temp_q <= d;

END IF;

END PROCESS;

q <= temp_q;

n_q <= NOT temp_q;

END behav;


D-type flip-flop

• Process sensitive to clk, clr, and pre

• Waits for an event on any of these signals

• If active-high clear signal is ‘1’ then temp_q is set to ‘0’

• If active-high preset signal is ‘1’ then temp_q is set to ‘1’

• Else on a clk rising edge the value of d is assigned to

temp_q.

• Three concurrent statements:

– Process statement

– q is set to the value of temp_q signal

– n_q is set to inverse of temp_q signal

• Synthesis results in one flip-flop


Two flip-flops produced if two signals used


Flip-flop (cont’d)

• Variations can be easily achieved

– negative-triggered clock

– synchronous active-low clear

ARCHITECTURE behav OF flip-flop IS

BEGIN

PROCESS (clk)

BEGIN


IF n_clr = ‘0’ THEN

q <= ‘0’

ELSE

q <= d;

END IF;

END IF;

END PROCESS;

END behav;


• Five-bit counter with asynchronous reset

• Using integer type

• (could also use std_logic_vector with unsigned library)

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY count17 IS

PORT(clk, reset : IN std_logic;

q : OUT integer RANGE 0 TO 17);

END count17;

Counter


Counter (cont’d)

ARCHITECTURE behav OF count17 is

SIGNAL count : integer RANGE 0 TO 17; -- internal signal

BEGIN

PROCESS(clk, reset) -- sensitivity list

BEGIN

IF reset = ‘1’ THEN -- asynch reset

count <= 0;

ELSIF clk’EVENT AND clk = ‘1’ THEN -- positive edge

IF count = 17 THEN

count <= 0; -- terminal count

ELSE

count <= count + 1;

END IF;

END IF;

END PROCESS;

q <= count; -- concurrent statement

END behav;


5-bit Counter Synthesis


5-Bit Counter Schematic


Counter with Synchronous Preset and Clear

ENTITY cnt4pre IS

PORT(clk, pre, n_clr : IN std_logic;

d : IN integer RANGE 0 TO 12;

q : OUT integer RANGE 0 TO 12);

END cnt4pre;

ARCHITECTURE behav OF cnt4pre IS

SIGNAL count : integer RANGE 0 TO 12;

BEGIN

PROCESS (clk)

BEGIN


IF n_clr = ‘0’ THEN -- synchronous clear

count <= 0;

ELSIF pre = ‘1’ THEN

count <= d;

ELSE

IF count = 12 THEN

count <= 0;

ELSE

count <= count + 1;

END IF;

END IF;

END IF;

END PROCESS;

q <= count;

END behav;


Synthesis Results – change to vectors


Schematic


Create Test Bench

• Project => New Source => VHDL Test Bench


Behavioral Simulation Results (ISE)


Behavioral Simulation (ModelSim)


ModelSim Waveform Results


Shift Registers

• Example of 4-bit shift register with

– parallel load

– shift left and shift right capability

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY shift IS

PORT(load, clk, left_right : IN std_logic;

d : IN std_logic_vector(3 DOWNTO 0);

q : OUT std_logic_vector(3 DOWNTO 0));

END shift;


Shift Register (cont’d)

ARCHITECTURE behav OF shift IS

SIGNAL temp : std_logic_vector(3 DOWNTO 0);

BEGIN

PROCESS(clk) -- all operations synchronous

BEGIN

IF clk'EVENT AND clk = '1' THEN

IF load = '1' THEN

temp <= d;

ELSIF left_right = '0' THEN -- shift left;

temp <= temp(2 DOWNTO 0) & '0';

ELSE

temp <= '0' & temp(3 DOWNTO 1); -- right

END IF;

END IF;

END PROCESS;

q <= temp;

END behav;


Synthesis Results


Shift Register Schematic


Shift Register - Behavioral Simulation

LFSR

• Input bit driven by XOR of some bits (feedback taps) of

shift reg value

• Initial value called seed

• Eventually enters repeating cycle

• n-bit LSR has 2n-1 states (0000 missing state)

• Sequence can appear random – generate PRN


Example 6-bit LFSR

• Taps at position 1 and 4, output at lsb


vhdl module5 rev e - wpiusers.wpi.edu/~rjduck/vhdl module5 rev e.pdf · jim duckworth, wpi 2...

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