FREDY AGUASGINETH BUSTOS

VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.

There are five types of design units in VHDL

entity declarationArchitectureConfigurationpackage declarationpackage body

A VHDL entity specifies the name of the entity, its ports and all information related to it. Entity led isPort (A,B,C: in STD_LOGIC;F: out STD_LOGIC);End led;

A B C D0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 0

. . . .

. . . .

. . . .1 1 1 01 1 1 1

Port: input or output. All ports must have: name, data type and mode

TYPE CHARACTERISTICSBIT In these signals take only the values of "1" and "0"

Boolean In this type signals only take values True and False

Std_logicIn these signals take 9 values , among them are: "1", "0", "Z" (for 3.er state), "-" (for optional).

IntegerIn such signals take integer values . The 1s and 0s are written without "

Bit_VectorIn this type of signal values are a string of ones and zeros. Example: "1000"

Std_Logic_Vector

In this type the signal values are a range of permissible values for the nine std_logic type.

CharacterIt contains all the ISO 8-bit characters, where the first 128 are the ASCII characters.

Declaration of entities through libraries and packages

Librerías IEEE y WORK.IEEE: paquete

std_logic_1164

WORK: numeric_std, std_arith.

Paquete: contains preset algorithms

ArchitectureIn general, programming styles used in architectures el desing know classified as

Functional (Behavioral). Defines a process described sequentially. Data Flow (Dataflow). Includes structure and behavior Structural (Structural). Defining interconnections and components.

Functional (Behavioral)architecture ARQ1 of COMPARA is begin process (A,B) begin if (A=B) then C <= ‛1’ after 1 ns; else C <= ‛0’ after 2 ns; end if; end process; End ARQ1

Data Flow (Dataflow)Entity XR2 is generic (m: time := 1.0 ns); -- Tiempo de retardo port (X,Y: in bit; Z: out bit);End XR2;architecture DATAFLOW of XR2 isbegin Z <= X xor Y after m; --Retardo genéricoend DATAFLOW;

StructuralEntity COMPARA is --Entity port (A,B: in bit; C: out bit);End COMPARA;

architecture STRUCT of COMPARA isSIGNAL I: bit; --Declaration of

componentscomponent XR2 port (x,y: in bit; z: out bit); end component;component INV port (x: in bit; z: out bit); end component;begin U0: XR2 port map (A,B,I); --Components U1: INV port map (I,C) --utilizadosend STRUCT;

It is the structure that defines the operation of an entity.

ARCHITECTURE dataflow of mux ISSIGNAL select : INTEGER;BEGINselect <= 0 WHEN s0 = „0‟ AND s1 = `0´ELSE1 WHEN s0 = „1‟ AND s1 = `0´ELSE 2 WHEN s0 = „0‟ AND s1 = `1´ELSE3 ;z <= a AFTER 0.5 NS WHEN select = 0 ELSEb AFTER 0.5 NS WHEN select = 1 ELSEc AFTER 0.5 NS WHEN select = 2 ELSEd AFTER 0.5 NS;END dataflow;