vhdl record final
DESCRIPTION
vhdlTRANSCRIPT
VHDL PROGRAMS
AND GATE:
AND GATE WAVE FORM:
OR GATE:
OR GATE WAVEFORM:
Exp no: 1 BASIC GATES
Date:
AIM: To design and write the source code in VHDL for basic gates and to compile then
simulate the same using Modelsim simulator.
SOFTWARE REQUIRED: Model technology MODELSIM XE 5.7c.
VHDL CODES:
(i) AND Gate:
library ieee;
use ieee.std_logic_1164.all;
entity and_gate is
port (A,B: in std_logic;
Y: out std_logic);
end and_gate;
architecture and_gate_arch of and_gate is
begin Y <= A and B;
end and_gate_arch;
(ii) OR Gate:
library ieee;
use ieee.std_logic_1164.all;
entity or_gate is
port (A,B: in std_logic;
Y: out std_logic);
end or_gate;
architecture or_gate_arch of or_gate is
begin Y <= A or B;
end or_gate_arch;
NOT GATE:
NOT GATE WAVEFORM:
NAND GATE:
NAND GATE WAVEFORM:
(iii) NOT Gate:
library ieee;
use ieee.std_logic_1164.all;
entity not_gate is
port (A: in std_logic;
Y: out std_logic);
end not_gate;
architecture not_gate_arch of not_gate is
begin
Y <= not A;
end not_gate_arch;
(iv) NAND Gate:
library ieee;
use ieee.std_logic_1164.all;
entity nand_gate is
port (A,B: in std_logic;
Y: out std_logic);
end nand_gate;
architecture nand_gate_arch of nand_gate is
begin
Y <= A nand B;
end nand_gate_arch;
NOR GATE:
NOR GATE WAVEFORM
XOR GATE:
XOR GATE WAVEFORM:
(v) NOR Gate:
library ieee;
use ieee.std_logic_1164.all;
entity nor_gate is
port (A,B: in std_logic;
Y: out std_logic);
end nor_gate;
architecture nor_gate_arch of nor_gate is
begin
Y <= A nor B;
end nor_gate_arch;
(vi) XOR Gate:
library ieee;
use ieee.std_logic_1164.all;
entity xor_gate is
port (A,B: in std_logic;
Y: out std_logic);
end xor_gate;
architecture xor_gate_arch of xor_gate is
begin
Y <= A xor B;
end xor_gate_arch;
XNOR GATE:
XNOR GATE WAVEFORM:
3I/P AND GATE:
3I/P AND GATE WAVEFORM:
(vii) XNOR Gate:
library ieee;
use ieee.std_logic_1164.all;
entity xnor_gate is
port (A,B: in std_logic;
Y: out std_logic);
end xnor_gate;
architecture xnor_gate_arch of xnor_gate is
begin
Y <= A xnor B;
end xnor_gate_arch;
(viii) MULTI INPUT GATES:
(a) 3ip AND Gate:
library ieee;
use ieee.std_logic_1164.all;
entity and_3ip is
port (A,B,C: in std_logic;
Y: out std_logic);
end and_3ip;
architecture and_3ip_arch of and_3ip is
begin
Y <= A and B and C;
end and_3ip_arch;
4I/P AND GATE:
4I/P AND GATE WAVEFORM:
3I/P OR GATE:
3I/P OR GATE WAVEFORM:
(b) 4ip AND Gate:
library ieee;
use ieee.std_logic_1164.all;
entity and_4ip is
port (A,B,C,D: in std_logic;
Y: out std_logic);
end and_4ip;
architecture and_4ip_arch of and_4ip is
begin
Y <= (A and B) and (C and D);
end and_4ip_arch;
(c) 3ip OR Gate:
library ieee;
use ieee.std_logic_1164.all;
entity or_3ip is
port (A,B,C: in std_logic;
Y: out std_logic);
end or_3ip;
architecture or_3ip_arch of or_3ip is
begin
Y <= A or B or C;
end or_3ip_arch;
4 I/P OR GATE:
4 I/P OR GATE WAVEFORM:
(d) 4ip OR Gate:
library ieee;
use ieee.std_logic_1164.all;
entity or_4ip is
port (A,B,C,D: in std_logic;
Y: out std_logic);
end or_4ip;
architecture or_4ip_arch of or_4ip is
begin
Y <= (A or B) or (C or D);
end or_4ip_arch;
RESULT:
Thus source codes in VHDL for Basic gates have been written, compiled and simulated
using modelsim simulator. The functionality of the various codes were also verified by
obtaining test bench waveforms.
HALF ADDER:
HALF ADDER WAVEFORM:
Exp no: 2 HALF ADDER DESIGN
Date:
AIM: To design and write the source code in VHDL for half adder in all models and to
compile then simulate the same using Modelsim simulator.
SOFTWARE REQUIRED: Model technology MODELSIM XE 5.7c.
VHDL CODES:
(i) HALF ADDER (Structural modeling):
library ieee;
use ieee.std_logic_1164.all;
entity halfadder_struct is
port(a,b:in std_logic;
s,c:out std_logic);
end halfadder_struct;
architecture ha_sm of halfadder_struct is
component xor_gate is
port(a,b:in std_logic;
y:out std_logic);
end component;
component and_gate is
port(a,b:in std_logic;
y:out std_logic);
end component;
begin
x: xor_gate port map(a,b,s);
z: and_gate port map(a,b,c);
end ha_sm;
(ii) HALF ADDER (Behavioral modeling):
library ieee;
use ieee.std_logic_1164.all;
entity halfadder_behav is
port(a,b:in std_logic;
s,c:out std_logic);
end halfadder_behav;
architecture ha_bm of halfadder_behav is
begin
process(a,b)
begin
if(a='0' and b='0') then s<='0';c<='0';
elsif(a='0' and b='1') then s<='1';c<='0';
elsif(a='1' and b='0')then s<='1';c<='0';
elsif(a='1' and b='1')then s<='0';c<='1';
end if;
end process;
end ha_bm;
(iii) HALF ADDER (Data flow modeling):
library ieee;
use ieee.std_logic_1164.all;
entity halfadder_df is
port(a,b:in std_logic; s,c:out std_logic);
end halfadder_df;
architecture ha_df of halfadder_df is
begin s<= (a xor b); c<= (a and b);
end ha_df;
RESULT:
Thus source codes in VHDL for Half Adders have been written, compiled and simulated
using modelsim simulator. The functionality of the various codes was also verified by
obtaining test bench waveforms.
FULL ADDER:
TRUTH TABLE:
FULL ADDER WAVEFORM:
Exp no: 3 FULL ADDER DESIGN
Date:
AIM: To design and write the source code in VHDL for full adder in all models and to
compile then simulate the same using Modelsim simulator.
SOFTWARE REQUIRED: Model technology MODELSIM XE 5.7c.
VHDL CODES:
(i) FULL ADDER (Structural modeling):
library ieee;
use ieee.std_logic_1164.all;
entity fulladder_struct is
port(a,b,cin:in std_logic;
s,c:out std_logic);
end fulladder_struct;
architecture fa_sm of fulladder_struct is
component xor_gate is
port(a,b:in std_logic;
y:out std_logic);
end component;
component and_gate is
port(a,b:in std_logic;
y:out std_logic);
end component;
component or_gate is
port(a,b:in std_logic;
y:out std_logic);
end component;
signal w1,w2,w3:std_logic;
begin
x: xor_gate port map(a,b,w1);
x1: xor_gate port map(w1,cin,s);
z: and_gate port map(a,b,w3);
z1: and_gate port map(w1,cin,w2);
m: or_gate port map(w2,w3,c);
end fa_sm;
(ii) FULL ADDER (Behavioral modeling):
library ieee;
use ieee.std_logic_1164.all;
entity fulladder_behav is
port(a,b,cin:in std_logic;
s,c:out std_logic);
end fulladder_behav;
architecture fa_bm of fulladder_behav is
begin
process(a,b,cin)
begin
if(a='0' and b='0' and cin='0')then s<='0';c<='0';
elsif(a='0' and b='0' and cin='1')then s<='1';c<='0';
elsif(a='0' and b='1' and cin='0')then s<='1';c<='0';
elsif(a='0' and b='1' and cin='1')then s<='0';c<='1';
elsif(a='1' and b='0' and cin='0')then s<='1';c<='0';
elsif(a='1' and b='0' and cin='1')then s<='0';c<='1';
elsif(a='1' and b='1' and cin='0')then s<='0';c<='1';
elsif(a='1' and b='1' and cin='1')then s<='1';c<='1';
end if;
end process;
end fa_bm;
(iii) FULL ADDER (Data Flow modeling):
library ieee;
use ieee.std_logic_1164.all;
entity fulladder_df is
port(a,b,cin:in std_logic;
s,c:out std_logic);
end fulladder_df;
architecture fa_df of fulladder_df is
begin s<= (a xor b) xor cin;
c<= (a and b) or (b and cin) or (a and cin);
end fa_df;
(iv) FULL ADDER USING 2-HALF ADDERS:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity fulladder is
port(a,b,cin:in std_logic;
s,c:out std_logic);
end fulladder;
architecture fa_ha of fulladder is
component halfadder_df is
port(a,b:in std_logic;
s,c:out std_logic);
end component;
component or_gate is
port(a,b:in std_logic;
y:out std_logic);
end component;
signal s1,c1,c2: std_logic;
begin
x1: halfadder_df port map(a,b,s1,c1);
x2: halfadder_df port map(s1,cin,s,c2);
x3: or_gate port map(c2,c1,c);
end fa_ha;
RESULT:
Thus source codes in VHDL for Full Adders have been written, compiled and simulated
using modelsim simulator. The functionality of the various codes was also verified by
obtaining test bench waveforms.
FOUR BIT ADDER:
TRUTH TABLE:
FOUR BIT ADDER WAVEFORM:
:
Exp no: 4 FOUR BIT ADDER DESIGN
Date:
AIM: To design and write the source code in VHDL for 4-bit adder using full adder and
to compile then simulate the same using Modelsim simulator.
SOFTWARE REQUIRED: Model technology MODELSIM XE 5.7c.
VHDL CODE:
FOUR BIT ADDER USING FULL ADDER (Structural modeling):
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity four_bit is
port (a,b:in std_logic_vector(3 downto 0); cin: in std_logic;
s:out std_logic_vector(3 downto 0); cout:out std_logic);
end four_bit;
architecture adder of four_bit is
component fulladder_df
port (a,b,cin:in std_logic;
s,c:out std_logic);
end component;
signal c0,c1,c2:std_logic;
begin
x1:fulladder_df port map(a(0),b(0),cin,s(0),c0);
x2:fulladder_df port map(a(1),b(1),c0,s(1),c1);
x3:fulladder_df port map(a(2),b(2),c1,s(2),c2);
x4:fulladder_df port map(a(3),b(3),c2,s(3),cout);
end adder;
RESULT:
Thus source codes in VHDL for Four Bit adder using Full Adders have been written,
compiled and simulated using modelsim simulator. The functionality of the various
codes was also verified by obtaining test bench waveforms.
4:1 MUX:
TRUTH TABLE:
4:1 MUX WAVE FORM:
Exp no: 5 MULTIPLEXER DESIGNS
Date:
AIM: To design and write the source code in VHDL for 4x1 and 16x1 using 4x1 and to
compile then simulate the same using Modelsim simulator.
SOFTWARE REQUIRED: Model technology MODELSIM XE 5.7c.
VHDL CODE:
(i) 4x1 MUX (Structural modeling):
library ieee;
use ieee.std_logic_1164.all;
entity muxstruct_4 is
port(a:in std_logic_vector(3 downto 0);
s:in std_logic_vector(1 downto 0);
y: out std_logic);
end muxstruct_4;
architecture muxstruct_4_arch of muxstruct_4 is
component and_3ip is
port(a,b,c:in std_logic;
y:out std_logic);
end component;
component or_gate is
port(a,b:in std_logic;
y:out std_logic);
end component;
component not_gate is
port(a:in std_logic; y:out std_logic);
end component;
signal w1,w2,w3,w4,w5,w6,w7,w8:std_logic;
begin
n1:not_gate port map(s(0),w1);
n2:not_gate port map(s(1),w2);
x1:and_3ip port map(a(0),w1,w2,w3);
x2:and_3ip port map(a(1),w1,s(1),w4);
x3:and_3ip port map(a(2),s(0),w2,w5);
x4:and_3ip port map(a(3),s(0),s(1),w6);
o1:or_gate port map(w3,w4,w7);
o2:or_gate port map(w5,w6,w8);
o3:or_gate port map(w7,w8,y);
end muxstruct_4_arch;
(ii) 4x1 MUX USING CASE STATEMENT:
library ieee;
use ieee.std_logic_1164.all;
entity mux_4 is
port(a:in std_logic_vector(3 downto 0); s:in std_logic_vector(1
downto 0);
y: out std_logic);
end mux_4;
architecture mux_4_arch of mux_4 is
begin
process(a,s)
begin
case (s) is
when "00"=> y<=a(3);
when "01"=> y<=a(2);
when "10"=> y<=a(1);
when "11"=> y<=a(0);
when others=>null;
end case;
end process;
end mux_4_arch;
16:1 MUX USING 4:1 MUX:
(iii) 4x1 MUX (Behavioral modeling):
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity mux4x1_behav is
port(a,b,c,d : in std_logic;
s0,s1 : in std_logic;
q : out std_logic);
end mux4x1_behav;
architecture mux_4x1_b of mux4x1_behav is
begin
process(a,b,c,d,s0,s1)
begin
if s0 ='0' and s1 ='0' then q <= a;
elsif s0 ='1' and s1 ='0' then q <= b;
elsif s0 ='0' and s1='1' then q <= c;
else q <=d;
end if;
end process;
end mux_4x1_b;
(iv) 16x1 MUX using 4x1 MUX(Structural modeling):
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity mux_16x1 is
port(a:in std_logic_vector(15 downto 0);
s: in std_logic_vector(3 downto 0);
z:out std_logic);
end mux_16x1;
16:1 MUX USING 4:1 MUX WAVEFORM:
architecture mux_16x1_arch of mux_16x1 is
signal z1,z2,z3,z4:std_logic;
component mux4x1_behav is
port(a,b,c,d,s0,s1:in std_logic;
q:out std_logic);
end component;
begin
m1: mux4x1_behav port map(a(0),a(1),a(2),a(3),s(0),s(1),z1);
m2: mux4x1_behav port map(a(4),a(5),a(6),a(7),s(0),s(1),z2);
m3: mux4x1_behav port map(a(8),a(9),a(10),a(11),s(0),s(1),z3);
m4: mux4x1_behav port map(a(12),a(13),a(14),a(15),s(0),s(1),z4);
m5: mux4x1_behav port map(z1,z2,z3,z4,s(2),s(3),z);
end mux_16x1_arch;
(v) 16x1 MUX USING CASE STATEMENT:
library ieee;
use ieee.std_logic_1164.all;
entity muxcase_16 is
port(a,b,c,d:in std_logic_vector(3 downto 0);
s:in std_logic_vector(3 downto 0);
y: out std_logic);
end muxcase_16;
architecture muxcase_16_arch of muxcase_16 is
begin
process(a,b,c,d,s)
begin
case s is
when "0000"=> y<=a(3);
when "0001"=> y<=a(2);
when "0010"=> y<=a(1);
when "0011"=> y<=a(0);
when "0100"=> y<=b(3);
when "0101"=> y<=b(2);
when "0110"=> y<=b(1);
when "0111"=> y<=b(0);
when "1000"=> y<=c(3);
when "1001"=> y<=c(2);
when "1010"=> y<=c(1);
when "1011"=> y<=c(0);
when "1100"=> y<=d(3);
when "1101"=> y<=d(2);
when "1110"=> y<=d(1);
when "1111"=> y<=d(0);
when others=>null;
end case;
end process;
end muxcase_16_arch;
RESULT:
Thus source codes in VHDL for 4x1 Mux and 16x1 Mux using 4x1 Mux have been
written, compiled and simulated using modelsim simulator. The functionality of the
various codes was also verified by obtaining test bench waveforms.
ENCODER:
TRUTH TABLE:
ENCODER WAVEFORM:
Exp no: 6 ENCODER AND DECODER DESIGNS
Date:
AIM: To design and write the source code in VHDL for 8 to 3 encoder & 3 to 8 decoder
and to compile then simulate the same using Modelsim simulator.
SOFTWARE REQUIRED: Model technology MODELSIM XE 5.7c.
VHDL CODE:
(i) 8 : 3 ENCODER(behavioral modeling):
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port ( a : in std_logic_vector (7 downto 0);
y : out std_logic_vector (2 downto 0));
end encoder;
architecture behavioral of encoder is
begin
process(a)
begin
if(a(0)='1')then y<="000";
elsif(a(1)='1')then y<="001";
elsif(a(2)='1')then y<="010";
elsif(a(3)='1')then y<="011";
elsif(a(4)='1')then y<="100";
elsif(a(5)='1')then y<="101";
elsif(a(6)='1')then y<="110";
elsif(a(7)='1')then y<="111";
end if;
end process;
end behavioral;
DECODER:
TRUTH TABLE:
(ii) 3 : 8 DECODER (Structural modeling):
library ieee;
use ieee.std_logic_1164.all;
entity decoder_3to8 is
port( a0, a1, a2 : in std_logic;
d0, d1, d2, d3, d4, d5, d6, d7 : out std_logic);
end decoder_3to8;
architecture decoder of decoder_3to8 is
component and_3ip is --import and gate entity
port( a, b, c : in std_logic;
y : out std_logic);
end component;
component not_gate is --import not gate entity
port( a : in std_logic;
y : out std_logic);
end component;
signal inva0, inva1, inva2 : std_logic;
begin
gi1: not_gate port map(a0, inva0);
gi2: not_gate port map(a1, inva1);
gi3: not_gate port map(a2, inva2);
ga1: and_3ip port map(inva0, inva1, inva2, d0);
ga2: and_3ip port map( a0, inva1, inva2, d1);
ga3: and_3ip port map(inva0, a1, inva2, d2);
ga4: and_3ip port map( a0, a1, inva2, d3);
ga5: and_3ip port map(inva0, inva1, a2, d4);
ga6: and_3ip port map( a0, inva1, a2, d5);
DECODER WAVEFORM:
ga7: and_3ip port map(inva0, a1, a2, d6);
ga8: and_3ip port map( a0, a1, a2, d7);
end decoder;
RESULT:
Thus source codes in VHDL for 8: 3 Encoder and 3: 8 Decoder have been written,
compiled and simulated using modelsim simulator. The functionality of the various
codes was also verified by obtaining test bench waveforms.
SR- FLIP FLOP:
TRUTH TABLE:
EXPRESSION:
Q = S + (not R) Q
SR-FLIP FLOP WAVEFORM:
CLR S R Q Qbar
0 X X 0 1
1 0 0 Q NQ
1 0 1 0 1
1 1 0 1 0
1 1 1 X X
Exp no: 7 FLIP-FLOP DESIGNS
Date:
AIM: To design and write the source code in VHDL for basic Flip-Flops and to compile
then simulate the same using Modelsim simulator.
SOFTWARE REQUIRED: Model technology MODELSIM XE 5.7c.
VHDL CODES:
(i) SR- FLIP FLOP (Behavioral modeling):
library ieee;
use ieee.std_logic_1164.all;
entity SR_ff is
port(s,r,clk:in std_logic; q,q1,z:inout std_logic);
end SR_ff;
architecture sr_arch of SR_ff is
begin
process(clk)
begin
if clk='1' then z<=s or ((not r) and q);
q<=z;
q1<=not z;
end if;
end process;
end sr_arch;
D FLIP FLOP:
TRUTH TABLE:
D FLIP FLOP WAVEFORM:
(ii) D- FLIP FLOP (Behavioral modeling):
library ieee;
use ieee.std_logic_1164.all;
entity DFF_v is
port (d,clk,clr: in bit;
Q,QB: out bit);
end DFF_V;
architecture dff_v_arch of dff_v is
begin
process (d,clk,clr)
begin
if clr='0' then q<='0'; qb<='1';
elsif(clk='1' and clk'event)then
q<=d; qb<=not d;
end if;
end process;
end dff_v_arch;
JK- FLIP FLOP:
TRUTH TABLE:
JK- FLIP FLOP WAVEFORM:
(iii) JK- FLIP FLOP (Behavioral modeling):
library ieee;
use ieee.std_logic_1164.all;
entity jkff is
port(j,k,clk,clr:in std_logic;
q,qn:inout std_logic);
end jkff;
architecture jk_ff of jkff is
begin
process(clk,clr,j,k)
begin
if clr='0'then q<='0'; qn<='1';
elsif(clk'event and clk='1') then
if(j='0' and k='0')then q<=q; qn<=qn;
elsif(j='1'and k='0')then q<='1'; qn<='0';
elsif(j='0'and k='1')then q<='0'; qn<='1';
elsif(j='1'and k='1')then q<=not q; qn<=not qn;
end if;
end if;
end process;
end jk_ff;
T- FLIP FLOP:
TRUTH TABLE:
T- FLIP FLOP WAVEFORM:
CLR T Q Qbar
0 X 0 1
1 0 Q NQ
1 1 NQ 0
(iv) T- FLIP FLOP (Behavioral modeling):
library ieee;
use ieee.std_logic_1164.all;
entity t_ff is
port (tin,clk,rst: in std_logic;
Q: inout std_logic; Qbar: out std_logic);
end t_ff;
architecture tff_arch of t_ff is
begin
Qbar <= not Q;
process(tin,clk,rst)
begin
if(rst='1') then Q<='0';
else
Q<= Q xor Tin;
end if;
end process;
end tff_arch;
RESULT:
Thus source codes in VHDL for Flip-Flops have been written, compiled and simulated
using modelsim simulator. The functionality of the various codes was also verified by
obtaining test bench waveforms
UP-DOWN COUNTER:
TRUTH TABLE:
I/P UP/DOWN COUNT
1111 0 1110
1110 0 1101
1101 0 1100
1100 0 1011
1011 0 1010
1010 0 1001
1001 0 1000
1000 0 0111
0111 0 0110
0110 0 0101
0101 0 0100
0100 0 0011
0011 0 0010
0010 0 0001
0001 0 0000
0000 1 0001
0001 1 0010
0010 1 0011
0011 1 0100
0100 1 0101
0101 1 0110
0110 1 0111
0111 1 1000
1000 1 1001
1001 1 1010
1010 1 1011
1011 1 1100
1100 1 1101
1101 1 1110
1110 1 1111
Exp no: 8 UP-DOWN COUNTER DESIGN
Date:
AIM: To design and write the source code in VHDL for basic Up-Down Counter and to
compile then simulate the same using Modelsim simulator.
SOFTWARE REQUIRED: Model technology MODELSIM XE 5.7c.
VHDL CODE:
UP-DOWN COUNTER:
--UP DOWN COUNTER
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ud_cntr is
port ( clk,clr,up_down: in std_logic;
q : out std_logic_vector (3 downto 0));
end ud_cntr;
architecture behavioral of ud_cntr is
signal tmp: std_logic_vector(3 downto 0);
begin
process(clk,clr)
begin
if(clr='1')then tmp<="0000";
elsif(clk'event and clk='1')then
if(up_down='1')then tmp<=tmp + 1 ;
else
tmp<=tmp - 1;
end if;
UP-DOWN COUNTER WAVEFORM:
end if;
end process;
q<=tmp;
end behavioral;
RESULT:
Thus source codes in VHDL for Up-Down counter have been written, compiled and
simulated using modelsim simulator. The functionality of the various codes was also
verified by obtaining test bench waveforms.
TRUTH TABLE:
BINARY INTEGER
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8
1001 9
1010 10
1011 11
1100 12
1101 13
1110 14
1111 15
FUNCTION WAVEFORM:
Exp no: 9 FUNCTION, PROCEDURE, GENERIC AND PACKAGE
Date:
AIM: To design and write the source code in VHDL for basic Function, Procedure,
Generic & Package and to compile then simulate the same using Modelsim simulator.
SOFTWARE REQUIRED: Model technology MODELSIM XE 5.7c.
VHDL CODES:
(i) FUNCTION:
--conversion of 4-bit binary to decimal
library ieee;
use ieee.std_logic_1164.all;
entity function1 is
port(x:in bit_vector(3 downto 0);
y:out integer);
end function1;
architecture function11 of function1 is
function bin_integer(bin:in bit_vector(3 downto 0))
return integer is
variable result:integer;
begin
result:=0;
for i in 0 to 3
loop
if bin(i)='1' then result:=result+2**i;
end if;
end loop;
return result;
end bin_integer;
PROCEDURE WAVEFORM:
begin
y<=bin_integer(x);
end function11;
(ii) PROCEDURE:
--conversion of 4-bit binary to decimal
library ieee;
use ieee.std_logic_1164.all;
entity procedure1 is
port(x:in bit_vector(3 downto 0);
y:out integer);
end procedure1;
architecture procedure11 of procedure1 is
procedure bin_integer(bin:in bit_vector(3 downto 0);
int:out integer) is
variable result:integer;
begin
result:=0;
for i in 0 to 3
loop
if bin(i)='1' then result:=result+2**i;
end if;
end loop;
int:=result;
end bin_integer;
begin
process(x)
variable temp1:integer;
GENERIC WAVEFORM:
begin
bin_integer(x,temp1);
y<=temp1;
end process;
end procedure11;
(iii) GENERIC:
--and gate using generic
library ieee;
use ieee.std_logic_1164.all;
entity generic_and is
generic(n:integer:=2);
port(a:in bit_vector(n downto 0);
y:out bit);
end generic_and;
architecture behav of generic_and is
begin
process(a)
variable and_out:bit;
begin
and_out:='1';
for k in 0 to n loop
and_out:=and_out and a(k);
exit when and_out='0';
end loop;
y<=and_out;
end process;
end behav;
PACKEGE WAVEFORM:
(iv) PACKAGE:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package generic_pack is
constant n:integer:=2; --type pack is array(n downto 0) of
std_logic;
end generic_pack;
//MAIN PROGRAM:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.generic_pack.all;
entity generic_and1 is
port(a:in bit_vector(n downto 0);
y:out bit);
end generic_and1;
architecture behav of generic_and1 is
begin
process(a)
variable and_out:bit;
begin
and_out:='1';
for k in 0 to n loop
and_out:=and_out and a(k);
exit when and_out='0';
end loop;
y<=and_out;
end process;
end behav;
RESULT:
Thus source codes in VHDL for Function, Procedure, Generic & Package have been
written, compiled and simulated using modelsim simulator. The functionality of the
various codes was also verified by obtaining test bench waveforms.
ALU CIRCUIT:
ALU WAVEFORM:
Exp no: 10 ALU DESIGN
Date:
AIM: To design and write the source code in VHDL for ALU design and to compile
then simulate the same using Modelsim simulator.
SOFTWARE REQUIRED: Model technology MODELSIM XE 5.7c.
VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity simple_alu is
port( Clk : in std_logic; --clock signal
A,B : in signed(7 downto 0); --input operands
Op : in unsigned(2 downto 0); --Operation to be performed
R : out signed(7 downto 0) --output of ALU );
end simple_alu;
architecture Behavioral of simple_alu is
signal Reg1,Reg2,Reg3 : signed(7 downto 0) := (others => '0');
begin
Reg1 <= A;
Reg2 <= B;
R <= Reg3;
process(Clk)
begin
if(rising_edge(Clk)) then --Do the calculation at the positive edge of clock cycle.
case Op is
when "000" =>
Reg3 <= Reg1 + Reg2; --addition
when "001" =>
Reg3 <= Reg1 - Reg2; --subtraction
when "010" =>
Reg3 <= not Reg1; --NOT gate
when "011" =>
Reg3 <= Reg1 nand Reg2; --NAND gate
when "100" =>
Reg3 <= Reg1 nor Reg2; --NOR gate
when "101" =>
Reg3 <= Reg1 and Reg2; --AND gate
when "110" =>
Reg3 <= Reg1 or Reg2; --OR gate
when "111" =>
Reg3 <= Reg1 xor Reg2; --XOR gate
when others =>
NULL;
end case;
end if;
end process;
end Behavioral;
RESULT:
Thus source codes in VHDL for ALU design have been written, compiled and simulated
using modelsim simulator. The functionality of the various codes was also verified by
obtaining test bench waveforms.
TEST BENCH HALF ADDER WAVEFORM:
TEST BENCH FULL ADDER WAVEFORM:
Exp no: 11 TEST BENCH
Date:
AIM: To design and write the source code in VHDL for TEST BENCH for Half adder
and Full adder and to compile then simulate the same using Modelsim simulator.
SOFTWARE REQUIRED: Model technology MODELSIM XE 5.7c.
VHDL CODE:
(i)TEST BENCH FOR HALF ADDER:
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
entity ha_tb is
end;
architecture beh of ha_tb is
signal a,b : std_logic;
signal sum,cout : std_logic;
component ha
port(a,b : in std_logic;
sum,cout : out std_logic);
end component;
begin
g1: ha port map (
a =>a,
b =>b,
sum =>sum,
cout=>cout );
a <= '0','1' after 100 ns, '0' after 200 ns,'1' after 300 ns;
b <= '1','0' after 100 ns, '1' after 200 ns,'0' after 300 ns;
end beh;
(ii)TEST BENCH FOR FULL ADDER:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity fa_tb is
end;
architecture beh of fa_tb is
signal a,b,c : std_logic;
signal sum,cout : std_logic;
component fa
port(a,b,c : in std_logic;
sum,cout : out std_logic);
end component;
begin
g1: fa port map (
a =>a,
b =>b,
c =>c,
sum =>sum,
cout=>cout);
a <= '0','1' after 100 ns, '0' after 200 ns,'1' after 300 ns;
b <= '1','0' after 100 ns, '1' after 200 ns,'0' after 300 ns;
c <= '0','1' after 100 ns, '0' after 200 ns,'1' after 300 ns;
end beh;
RESULT:
Thus source codes in VHDL for TEST BENCH of half adder and full adder have been
written, compiled and simulated using modelsim simulator.
VERILOG HDL PROGRAMS
BASIC GATE WAVEFORM:
Exp no: 1 BASIC GATES
Date:
AIM: To design and write the source code in Verilog HDL for basic gates and to
compile then simulate the same using Modelsim simulator.
SOFTWARE REQUIRED: Model technology MODELSIM XE 5.7c.
VERILOG HDL CODE:
module basic_gates(a,b,y,y1,y2,y3,y4,y5,y6);
input a,b;
output y,y1,y2,y3,y4,y5,y6;
and(y,a,b); //assign y=a&b
or(y1,a,b); //assign y=a|b
not(y2,a); //assign y=~a
assign y3 = ~(a&b); //nand
assign y4 = ~(a|b); //nor
assign y5 = a^b; //xor(y,a,b)
assign y6 = ~(a^b); //x-nor
endmodule
RESULT:
Thus source codes in Verilog HDL for Basic gates have been written, compiled and
simulated using modelsim simulator. The functionality of the code was also verified by
obtaining test bench waveforms.
HALF ADDER WAVE FORM:
FULL ADDER WAVE FORM:
FOUR BIT ADDER WAVE FORM:
Exp no: 2 BASIC ADDERS
Date:
AIM: To design and write the source code in Verilog HDL for basic Adders and test
bench for the same and to compile then simulate the same using Modelsim simulator.
SOFTWARE REQUIRED: Model technology MODELSIM XE 5.7c.
VERILOG HDL CODES:
(i) HALF ADDER:
(a) Structural description:
module ha_stuct(a,b,s,c);
input a,b;
output s,c;
xor g1(s,a,b);
and g2(c,a,b);
endmodule
(b) Data-flow description:
module ha_df (a,b,s,c);
input a,b;
output s,c;
assign s = a^b;
assign c = a&b;
endmodule
(c) Behavioral description:
module ha_behav (a,b,s,c);
input a,b;
output s,c;
assign {c,s}=a+b;
endmodule
HALF ADDER TEST BENCH WAVE FORM:
FULL ADDER TEST BENCH WAVE FORM:
(d) Test bench for Data-flow description:
module ha_test_bench;
reg A,B;
wire Sum,Ca;
ha_df l1(.A(A),.B(B),.Sum(Sum),.Ca(Ca));
initial
begin
$monitor (A,B,Sum,Ca);
A = 1'b0;
B = 1'b1;
#50 B = 1'b0;
#50 A = 1'b1;
#50 B = 1'b1;
end
endmodule
(ii) FULL ADDER:
(a) Structural description:
module fa_struct(a,b,cin,s,cout);
input a,b,cin;
output s,cout;
wire s1,c1,c2;
xor g1 (s1,a,b);
and g2 (c1,a,b);
xor g3 (s,s1,cin);
and g4 (c2,s1,cin);
or g5 (cout,c2,c1);
endmodule
(b) Data flow description:
module fa_df(a,b,cin,s,cout);
input a,b,cin;
output cout,s;
assign s=a^b^cin;
assign cout=(a&b)|(b&cin)|(a&cin);
endmodule
(c) Behavioral description:
module fa_behav(a,b,cin,s,cout);
input a,b,cin;
output s, cout;
assign {cout,s}=a+b+cin;
endmodule
(d) Test bench for Data-flow description:
module fa_tb;
reg a, b, cin;
wire s, ca;
fa1 l1(.a(a), .b(b), .cin(cin), .s(s), .ca(ca));
initial
begin
$monitor (a,b,cin,s,ca);
a = 1'b0;
b = 1'b0;
cin = 1'b0;
#50 cin = 1'b1;
#50 b = 1'b1;
#50 cin = 1'b0;
#50 a = 1'b1;
#50 b = 1'b0;
#50 cin = 1'b1;
#50 b = 1'b1;
end
endmodule
(iii) 4-BIT ADDER:
module four_bit_adder(A,B,Cin,S,Ca);
input [3:0] A,B;
input Cin;
output [3:0] S;
output Ca;
assign {Ca,S} = A + B + Cin;
endmodule
RESULT:
Thus source codes in Verilog HDL for Basic Adders have been written, compiled and
simulated using modelsim simulator. The functionality of the code was also verified by
obtaining test bench waveforms.
4x1 MULTIPLEXER WAVE FORM:
16x1 MULTIPLEXER USING 4x1 MUX WAVE FORM:
Exp no: 3 MULTIPLEXER DESIGN
Date:
AIM: To design and write the source code in Verilog HDL for 4x1 &16x1 mux using
4x1 mux and to compile then simulate the same using Modelsim simulator.
SOFTWARE REQUIRED: Model technology MODELSIM XE 5.7c.
VERILOG HDL CODES:
(i) 4x1 MUX:
module muxx(a,b,c,d,s,y);
input a,b,c,d;
input [1:0] s;
output y;
reg y;
always @(*)
case(s)
2'b00 : y = a;
2'b01 : y = b;
2'b10 : y = c;
2'b11 : y = d;
endcase
endmodule
(ii) 16x1 MUX USING 4x1:
module mux16_1 (a,s,y);
input [3:0]s;
input [15:0]a;
output y;
wire w0,w1,w2,w3,w4;
muxx l0(a[0],a[1],a[2],a[3],s[1:0],w0);
muxx l1(a[4],a[5],a[6],a[7],s[1:0],w1);
muxx l2(a[8],a[9],a[10],a[11],s[1:0],w2);
muxx l3(a[12],a[13],a[14],a[15],s[1:0],w3);
muxx l4(w0,w1,w2,w3,s[3:2],y);
endmodule
RESULT:
Thus source codes in Verilog HDL for 4x1 Mux &16x1 using 4x1 Mux have been
written, compiled and simulated using modelsim simulator. The functionality of the code
was also verified by obtaining test bench waveforms.
8:3 ENCODER WAVE FORM:
3:8 DECODER:
Exp no: 4 ENCODER AND DECODER DESIGN
Date:
AIM: To design and write the source code in Verilog HDL for 4x1 &16x1 mux using
4x1 mux and to compile then simulate the same using Modelsim simulator.
SOFTWARE REQUIRED: Model technology MODELSIM XE 5.7c.
VERILOG HDL CODES:
(i) 8:3 ENCODER:
module encoder1(in,out);
input [7:0]in;
output [2:0]out;
reg [2:0]out;
always @ (in)
begin
if(in==8'b00000001) out=0;else
if(in==8'b00000010) out=1;else
if(in==8'b00000100) out=2;else
if(in==8'b00001000) out=3;else
if(in==8'b00010000) out=4;else
if(in==8'b00100000) out=5;else
if(in==8'b01000000) out=6;else
if(in==8'b10000000) out=7;else
out=3'bx;
end
endmodule
(ii) 3:8 DECODER:
module dcdr3_8 (d,a);
input [2:0] a;
output [7:0] d;
reg [7:0] d;
always @(a)
begin
if(a==3'b000) d<= 8'b00000001; else
if(a==3'b001) d<= 8'b00000010; else
if(a==3'b010) d<= 8'b00000100; else
if(a==3'b011) d<= 8'b00001000; else
if(a==3'b100) d<= 8'b00010000; else
if(a==3'b101) d<= 8'b00100000; else
if(a==3'b110) d<= 8'b01000000; else
d<= 8'b10000000;
end
endmodule
RESULT:
Thus source codes in Verilog HDL for Encoder and Decoder have been written,
compiled and simulated using modelsim simulator. The functionality of the code was
also verified by obtaining test bench waveforms.
SR- FLIP FLOP WAVE FORM:
D- FLIP FLOP WAVE FORM:
Exp no: 5 FLIP-FLOP DESIGNS
Date:
AIM: To design and write the source code in Verilog HDL for basic Flip-Flops and to
compile then simulate the same using Modelsim simulator.
SOFTWARE REQUIRED: Model technology MODELSIM XE 5.7c.
VERILOG HDL CODES:
(i) SR- FLIP FLOP:
module sr_ff(s,r,clk,q,qb);
input s,r,clk;
output q,qb;
reg q;
assign qb = ~q;
always @ (posedge clk)
case({s,r})
2'b00 : q=q;
2'b01 : q=1'b0;
2'b10 : q=1'b1;
2'b11 : q=1'bz;
endcase
endmodule
(ii) D-FLIP FLOP:
module d_ff(d,s,r,clk,q,qb);
input d,s,r,clk;
output q,qb;
reg q;
assign qb = ~q;
always @(negedge s or negedge r or posedge clk)
JK- FLIP FLOP WAVE FORM:
T- FLIP FLOP WAVE FORM:
begin
if(r==0) q<=0; else
if(s==0) q<=1; else
q<=d;
end
endmodule
(iii) JK-FLIP FLOP:
module jk_ff1(j,k,preset,clear,clk,q,qb);
input j,k,clk,preset,clear;
output q,qb;
reg q;
assign qb = ~q;
always @ (negedge preset or negedge clear or posedge clk)
begin
if(clear==0) q<=0;
else if(preset==0) q<=1;
else if(j==0&k==0) q=q;
else if(j==0&k==1) q=j;
else if(j==1&k==0) q=j;
else if(j==1&k==1) q=~q;
else
$display("unspecified control signals");
end
endmodule
(iv) T- FLIP FLOP:
module t_ff(s,r,clk,q,qb);
input s,r,clk;
output q,qb;
d_ff d1(~q,s,r,clk,q,qb);
endmodule
RESULT:
Thus source codes in Verilog HDL for Flip-Flops have been written, compiled and
simulated using modelsim simulator. The functionality of the various codes was also
verified by obtaining test bench waveforms.
UP-DOWN COUNTER WAVE FORM:
Exp no: 6 UP-DOWN COUNTER DESIGN
Date:
AIM: To design and write the source code in Verilog HDL for basic Up-Down Counter
and to compile then simulate the same using Modelsim simulator.
SOFTWARE REQUIRED: Model technology MODELSIM XE 5.7c.
VERILOG HDL CODE:
UP-DOWN COUNTER:
module up_down(clk,r,upd,count);
input clk,r,upd;
output [3:0]count;
reg [3:0]count;
always @ (posedge clk or posedge r)
begin
if(r==1) count<=4'b0000;
else
if(upd==1) count<=count+1;
else count<=count-1;
end
endmodule
RESULT:
Thus source codes in VHDL for Up-Down counter have been written, compiled and
simulated using modelsim simulator. The functionality of the various codes was also
verified by obtaining test bench waveforms.
UNIVERSAL SHIFT REGISTER WAVE FORM:
Exp no: 7 UNIVERSAL SHIFT REGISTER
Date:
AIM: To design and write the source code in Verilog HDL for basic Up-Down Counter
and to compile then simulate the same using Modelsim simulator.
SOFTWARE REQUIRED: Model technology MODELSIM XE 5.7c.
VERILOG HDL CODE:
UNIVERSAL SHIFT REGISTER:
module universal_shift_reg(clk,clr,rin,lin,s,d,q);
input clk,clr,rin,lin;
input [2:0]s;
input[7:0]d;
output [7:0]q;
reg [7:0]q;
always @ (posedge clk or posedge clr)
begin
if(clr) q<=0; else
case(s)
0:q<=q; //hold
1:q<=d; //load
2:q<={rin,q[7:1]}; //shift right
3:q<={q[6:0],lin}; //shift left
4:q<={q[0],q[7:1]}; //shift circular right
5:q<={q[6:0],q[7]}; //shift circular left
6:q<={q[7],q[7:1]}; //arithmetic right
7:q<={q[6:0],1'b0}; //arithmetic left
endcase
end
endmodule
RESULT:
Thus source codes in Verilog HDL for Universal shift register have been written,
compiled and simulated using modelsim simulator. The functionality of the various
codes was also verified by obtaining test bench waveforms.
FUNCTION WAVE FORM:
TASK WAVE FORM:
Exp no: 8 FUNCTION AND TASK
Date:
AIM: To design and write the source code in Verilog HDL for basic Function, & Task
and to compile then simulate the same using Modelsim simulator.
SOFTWARE REQUIRED: Model technology MODELSIM XE 5.7c.
VERILOG HDL CODES:
(i) FUNCTION:
module func_eg(a,b,c);
input a,b;
output c;
function func;
input x,y;
func = ( x + y);
endfunction
assign c = func (a,b);
endmodule
(ii) TASK:
- - Reversing of 4-bit binary
module task_exa(data_in, data_out);
input [3:0] data_in;
output[3:0] data_out;
reg [3:0] data_out;
task reverse_bit;
input [3:0] dat_in;
output[3:0] dat_out;
integer k;
begin
for(k=0;k<4;k=k+1)
dat_out[4-k-1]=dat_in[k];
end
endtask
always @(data_in)
reverse_bit(data_in,data_out);
endmodule
RESULT:
Thus source codes in Verilog HDL for Function & Task have been written, compiled and
simulated using modelsim simulator. The functionality of the various codes was also
verified by obtaining test bench waveforms.
ALU DESIGN WAVE FORM:
Exp no: 9 ALU DESIGN
Date:
AIM: To design and write the source code in Verilog HDL for basic ALU Design and to
compile then simulate the same using Modelsim simulator.
SOFTWARE REQUIRED: Model technology MODELSIM XE 5.7c.
VERILOG HDL CODES:
(i) ALU DESIGN:
module alu_design (a,b,s,t,u,v,w,x,y,z);
input [3:0] a,b;
output [3:0] s,t,u,v,w,x,y,z;
assign s = a | b;
assign t = ~a;
assign u = a + b;
assign v = a - b;
assign w = a / b;
assign x = a % b;
assign y = a * b;
assign z = a & b;
endmodule
RESULT:
Thus source codes in Verilog HDL for ALU Design have been written, compiled and
simulated using modelsim simulator. The functionality of the various codes was also
verified by obtaining test bench waveforms.
AND GATE:
a
b
a b
y
AND GATE WAVE FORM:
INVERTER:
a y
INVERYER WAVE FORM:
Exp no: 10 SWITCH LEVEL DESIGN
Date:
AIM: To design and write the source code in Verilog HDL for Switch level designing
and to compile then simulate the same using Modelsim simulator.
SOFTWARE REQUIRED: Model technology MODELSIM XE 5.7c.
VERILOG HDL CODES:
(i) AND Gate:
module and_gate_switch_level(a,b,y);
input a,b;
output y;
wire s;
supply1 vdd;
supply0 gnd;
nmos l1(s,vdd,a);
nmos l2(y,s,b);
pmos l3(y,gnd,a);
pmos l4(y,gnd,b);
endmodule
(ii) INVERTER:
module inv_sld(a,y);
input a;
output y;
supply1 vdd;
supply0 gnd;
NAND GATE:
a b
a
b
y
NAND GATE WAVE FORM:
pmos l1(y,vdd,a);
nmos l2(y,gnd,a);
endmodule
(iii) NAND Gate:
module nand_gate_switch_level(a,b,y);
input a,b;
output y;
wire s;
supply1 vdd;
supply0 gnd;
pmos p1(y,vdd,a);
pmos p2(y,vdd,b);
nmos n1(s,gnd,a);
nmos n2(y,s,b);
endmodule
(iv) NOR Gate:
module nor_gate_switch_level(a,b,y);
input a,b;
output y;
wire s;
supply1 vdd;
supply0 gnd;
pmos p1(s,vdd,a);
pmos p2(y,s,b);
NOR GATE:
a
b
a b
y
NOR GATE WAVE FORM:
nmos n1(y,gnd,a);
nmos n2(y,gnd,b);
endmodule
RESULT:
Thus source codes in Verilog HDL for Switch level designing have been written,
compiled and simulated using modelsim simulator. The functionality of the various
codes was also verified by obtaining test bench waveforms.