vhdl statements

VHDL STATEMENTS

Cristian Sisterna

UNSJ

VHDL Modeling Real Systems

The operations in real systems are executedconcurrently.

The VHDL language describes real systems as a setof components (statements) that operateconcurrently.

Each of these components is described withconcurrent statements.

The complexity of each component may vary from asimple logic gate to a processor

© Cristian Sisterna DSDA

2

VHDL Concurrent Statements

Then main concurrent statements are:

The signal assignment statement

Simple signal assignment statement

Conditional signal assignment statement

Selective signal assignment statement

The component instantiation statement

The generate statement

The process statement (inside a process the statements are executed sequentially)


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Processes

Processes are composed of sequential statements, but process declarations are concurrent statements.

The main features of a process are the following:

It is executed in parallel with other processes;

It cannot contain concurrent statements;

It defines a region of the architecture where statements are executed sequentially;

It must contain an explicit sensitivity list or a wait statement

It allows functional descriptions, similar to the programming languages;

It allows access to signals defined in the architecture in which the process appears and to those defined in the entity to which the architecture is associated.


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Understanding Sequential & Concurrent Statements


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concurrent

sequential

sequential

concurrent

concurrent

concurrent

VHDL CONCURRENT STATEMENTS

Concurrent Signal Assignment Statements

This statement is executed in parallel with other concurrent statements or other processes.

There are three types of concurrent signal assignment statements:

▫ simple signal assignment

▫ conditional signal assignment

▫ selected signal assignment


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© Cristian

Sisterna

DSDA

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Simple Signal Assignment Statement


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The order in which the statements are written is irrelevant

© Cristian

Sisterna

DSDA

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Selected Signal Assignment

with <selection_signal> select

target_signal <= <expression> when <value1_ss>,

<expression> when <value2_ss>,

...

<expression> when <last_value_ss>,

<expression> when others;

Cristian Sisterna DSDA

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Syntax

A selective signal assignment describes logic based on mutually exclusive combinations of values of the

selection signal


• There is no priority. Each branch has identical priority

• All values of <selection_signal> must be listed in the when clauses and will be mutually exclusive

• All the possible values of the expression are reachable

• A branch can depend on a range of the possible values of <selection_signal>


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• unaffected can be used to indicate that the target signal does not change for that condition

• <value1_ss> can not be an expression

• <selection_signal> and <expression> are the sensitivity list of this statement


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Selected Signal Assignmententity compares is

port( a, b, c, d, w, x, y, z: in std_logic;

j: out std_logic);

end compares;

architecture beh of compares is

signal tmp: std_logic_vector(3 downto 0);

begin

tmp <= (a,b,c,d)

with tmp select

j <= w when “1000”,

x when “0100”,

y when “0010”,

z when “0001”,

'0‘when others;

end beh;


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RTL View Technology View

Selected Signal Assignmententity compares is

port( a, b, c, d, w, x, y, z: in std_logic;

j: out std_logic);

end compares;

architecture beh of compares is

signal tmp: std_logic_vector(3 downto 0);

begin

tmp <= (a,b,c,d)

with tmp select

j <= w when “1000”,

x when “0100”,

y when “0010”,

z when “0001”,

‘-’when others;

end beh;


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Selective Signal Assignment


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Selected Signal Assignmentwith std_logic_vector'(a, b, c) select

q <= "01" when "100",

"01" when "101",

“10" when "110",

"01" when "111",

"10" when "010",

"10" when "011",

"11" when "001",

"00" when others;


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with std_logic_vector'(A, B, C) select

q <= "01" when "100“ | “101 | “111”,

“10" when " “ | “010”| “011”,

"11" when "001",

"00" when others;



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library ieee;

use ieee.std_logic_1164.all;

entity truth_table is

port(a, b, c: in std_logic;

y: out std_logic) ;

end truth_table;

architecture behave of truth_table is

signal s1: std_logic_vector(2 downto 0);

begin

s1 <= a & b & c; -- concatenate a, b, c

with s1 select

y <= ‘1’ when “000” | “010” | “100” ,

‘0’ when “001” | “011” | “101”,

‘-’ when others;

end behave;‘-’ means don’t care

A B C Y

0 0 0 1

0 0 1 0

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 -

1 1 1 -

“|” means OR only when used in “with” or “case”

Example: Truth Table



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SynthesisResult

RTL View

TechnologyView

Selective Signal Assignmententity gen_tst is

generic(ancho: integer:=4);

port (

i_data : in std_logic_vector(ancho-1 downto 0);

o_data : out std_logic_vector(ancho-1 downto 0));

end gen_tst;


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architecture beh of gen_tst is

begin

with i_data select

o_data <= x"f" when "0001",

x"a" when "0101",

x"0" when others;

end beh;

architecture beh of gen_tst is

signal int_data: integer range 0 to 2**ancho;

begin

int_data <= to_integer(unsigned(i_data));

with int_data select

o_data <= x"f" when 1,

x"a" when 5,

x"0" when others;

end beh;

© Cristian

Sisterna

DSDA

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Conditional Signal Assignment

Cristian SisternaDSDA

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target_signal <=

<expression> when <boolean_condition> else

<expression> when <boolean_condition> else

....

<expression> when <boolean_condition>[else

<expression>];

Syntax

A conditional signal assignment describes logic based on unrelated boolean_conditions, the first condition that is true

the value of expression is assigned to the target_signal



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• Assign a value to the target signal based on a condition<boolean_condition>

• There is an explicit priority

• <expression> and <boolean_condition> are the

sensitivity list of this statement

• Each <boolean_condition> is independent from the others

z <= (a xor b) when mux_s = ‘0’ else

b;

boolean_conditionexpression

• The <target> signal must always be assigned a value

• The source expression must be of the same type as the target signal

• The last branch must be an unconditional else so that one of the source expressions will be always assigned to the target_signal



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dbus <= data when enable = ‘1’ else ‘Z’;

dbus <= data when enable = ‘1’ else (others=>‘Z’);

Main usage



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library ieee;

use ieee.std_logic_1164.all;

entity my_tri is

generic(bus_ancho: integer := 4);

port(

a : in std_logic_vector(bus_ancho-1 downto 0);

en: in std_logic;

y : out std_logic_vector(bus_ancho-1 downto 0)

);

end my_tri;

architecture behave of my_tri is

begin

y <= a when en = ‘1’ else (others => ‘z’) ;

end behave;

EN

A(0) Y(0)

EN

A(1) Y(1)

EN

A(2) Y(2)

EN

A(3) Y(3)

© Cristian

Sisterna

DSDA

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The Role of Components in RTL VHDL

© Cristian SisternaDSDA

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Hierarchy in VHDL

Components

Divide & Conquer

Each subcomponent can be designed and completely tested

Create library of components (technology independent if possible)

Third-party available components

Code for reuse

Hierarchy in VHDL - Components


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High-Speed

DDR ADC

Ethernet

FPGA

Hierarchy in VHDL - Components© Cristian SisternaDSDA

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Component Declaration

A component is declared inside the architecture part of the entity in which the component will be used


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Component instantiation is a concurrent statement that is used to connect a component I/Os to the internal signals or to the I/Os of the higher lever

component

Component Instantiation

VHDL Components

• Components are design entities that are used in other design entities

• ‘Traditional’ method

▫ In order to use an entity within another entity, a component declaration is necessary for the entity to be used

▫ The interconnections between the component and the entity’s signals is declared in the component instantiation

• ‘New’ method

▫ Just a specific component instantiation is needed


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Component Declaration Statement

• Define a sub-component within an entity (component)

• It can be declared in the architecture declarativepart or in the package declaration (items declared in a package can be used in an entity-architecture pairby using the library and the package names)

• Specify the component external interface: ports, mode and type and also the component name (itlooks like an entity declaration)


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component comp_name [is]

[generic

(generic_interface_list);]

port (port_interface_list);

end component [component_name];


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comp_name entity’s name

generic_interface_list do not need to be

declared in the component declaration

port_interface_list must be identical to the

I/O ports in the component’s entity



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Top

Nand2

D_FF

Counter

BRAM

OutputsInputs

Component Declaration


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entity nand2 is

port (a, b: in std_logic,

z: out std_logic);

end;

architecture rtl of nand2 is

…

end;

entity top is

port(…

);

end;

achitecture structural of top is

component nand2


z : out std_logic);

end component;

…

begin

….

end;

ComponentDeclaration

Component Instantiation Statement

• component_label it labels the instance by giving a name to theinstanced

• generic_assocation_list assign new values to the default generic values (given in the entity declaration)

• port_association_list associate the signals in the top entity/architecture with the ports of the component. There are twoways of specifying the port map:

• Positional Association / Name Association


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component_label: component_name

[generic map (generic_assocation_list)]

port map (port_association_list);

Positional Association

▫ Each actual in the component instantiation is mapped by position with each port in the component declaration

▫ That is, the first port in the component declarationcorresponds to the first actual in the componentinstantiation, the second with the second and so on


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• The I/Os in the component declaration, are called formals

• The signals to be conected to the component to instantiate in the component instantiation, are called actuals

In positional association, an association list is of the form

(actual1, actual2, actual3, … actualn);

Positional Association - Example


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-- component declaration

component NAND2


z: out std_logic);

end component;

. . . . .

-- component instantiation

U1: NAND2 port map (S1, S2, S3);

-- S1 is associated with a

-- S2 is associated with b

-- S3 is associated with z

actuals

formals

Named Association - ExampleIn named association, an association list is of the form

(formal1=>actual1, formal2=>actual2, … formaln=>actualn);


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component NAND2

port (a, b: in std_logic;

z: out std_logic);

end component;


U1: NAND2 port map (a=>S1, z=>S3, b=>S2);

-- S1 associated with a, S2 with b and S3 with z

Connected to Component I/O Port Internal Signal or Entity

I/O Port

Association Rules

• The type of the formal and the actual being associated must be the same

• The modes of the ports must conform the rule that if the formal is readable, so must the actual be. If the formal is writable so must the actual be

• If an actual is a port of mode in, it may no be associated with a formal of mode out or inout

• If the actual is a port of mode out, it may not be associated with a formal of mode in or inout

• If the actual is a port of mode inout, it may be associated with a formal of mode in, out or inout


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‘New’ Syntax for Component

Instantiation


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component NAND2


z: out std_logic);

end component;


U1: entity work.NAND2 port map (a=>S1, z=>S3, b=>S2);

-- S1 associated with a, S2 with b and S3 with z

Unconnected Outputs

• When a component is instanced, one of the outputs sometimes has to be unconnected

• This can be done using the keyword open


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architecture rtl of top_level is

component ex4


q1, q2: out std_logic;

end component;

begin

U1: ex4 port map(a=>a, b=>b, q1=>dout, q2=>open);

end;

Unconnected inputs• Leaving floating inputs is a very bad poor technique

• If an input on a component is not to be used, the signal should be connected to VCC or GND.

• VHDL ’87: It is not permissible to map the input directly in the port map, an internal signal must be used


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architecture rtl of top_level is

component ex4

port (a, b : in std_logic;

q1, q2: out std_logic;

end component;

begin

U1: ex4 port map(a=>’0’, b=>b, q1=>dout, q2=>open);

end rtl;

Component declaration/instantiation ex. © Cristian SisternaDSDA

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entity GATING is

port (A, CK, MR, DIN: in BIT;

RDY, CTRLA: out BIT);

end GATING;

architecture STRUCT of GATING is

component AND2

port( X, Y: in bit;

Z: out bit);

end component;

component DFF

port (D, CLOCK: in BIT;

Q, QBAR: out BIT);

end component;

component NOR2

port ( DA, DB: in BIT;

DZ: out BIT);

end component;

signal S1, S2: BIT;

begin

D1: DFF port map (D=>A, CLOCK=>CK, Q=>S1,

QBAR=>S2);

A1: AND2 port map (X=>S2, Y=>DIN, Z=>CTRLA);

N1: NOR2 port map (S1, MR, RD1);

end STRUCT;

component - Example © Cristian SisternaDSDA

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entity GATING is

port (A, CK, MR, DIN: in BIT;

RDY, CTRLA: out BIT);

end GATING;

architecture STRUCT of GATING is

signal S1, S2: BIT;

begin

D1: entity work.DFF port map (D=>A, CLOCK=>CK, Q=>S1, QBAR=>S2);

A1: entity work.AND2 port map(S2, DIN, CTRLA);

N1: entity work.NOR2 port map (S1, MR, RD1);

end STRUCT;

Generic Map

• If generic components have been specified in the component to be instanced, their value can be changed during instantiation using the command generic map

• By using generics, it is possible to design components which can be parameterized

• Positional and named association can be used


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generic map (generic_assocation_list);

generic usage - Example


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architecture ejemplo of regist_variable is

component dff

generic ( width: positive);

port (rst, clk: in std_logic;

d: in std_logic_vector(width-1 downto 0);

q: out std_logic_vector(width-1 downto 0));

end component;

constant width_16: positive:= 16;

constant width_32: positive:= 32;

signal d8, q8: std_logic_vector(7 downto 0);



generic usage - Example (cont’)


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begin

ff8: dff port map (rst, clk, d8, q8);

ff16: dff generic map(width_16)

port map (rst, clk, d16, q16);

ff32: dff generic map(width_32)

port map (rst=>rst,clk=>clk,d=>d32, q=>q32);

end ejemplo;

Named versus Positional


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dramfifo_0: dramfifo

PORT MAP(

reg_data => reg_data ,

dram_state_ps => dram_state_ps ,

dram_cnt_ps => dram_cnt_ps ,

dram_cycle_type => dram_cycle_type ,

addr_adv => addr_adv ,

line_shift => line_shift ,

cycle_start => cycle_start ,

done => done ,

any_rdgnt => any_rdgnt ,

any_wrgnt => any_wrgnt ,

test_mode => test_mode ,

scl_ratio_ack => scl_ratio_ack ,

y_wrptrlo_wen => y_wrptrlo_wen ,

y_wrptrhi_wen => y_wrptrhi_wen ,

u_wrptrlo_wen => u_wrptrlo_wen ,u_wrptrhi_wen => u_wrptrhi_wen . . . . .,

Named versus Positional


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dramfifo_0: dramfifo

PORT MAP(

reg_data,

dram_state_ps,

dram_cnt_ps,

dram_cycle_type,

addr_adv,

line_shift,

cycle_start,

done,

any_rdgnt,

any_wrgnt,

test_mode,

scl_ratio_ack,

y_wrptrlo_wen,

y_wrptrhi_wen,

u_wrptrlo_wen,u_wrptrhi_wen, . . . .


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Generate Statements

• Concurrent statements can be conditionally selectedor replicated using the generate statement

• generate is a concurrent statement containingfurther concurrent statements that are to bereplicated

• There are two forms of the generate statement:▫ for-generate scheme: concurrent statements can be

replicated a predetermined number of times▫ if-generate scheme: concurrent statements can be

conditionally elaborated


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Generate Statements

• generate statement resembles a macro expansion

• If the same component has to be instanced several times in the same architecture, it will be very effective to include the port map statement in a loop


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for-generate

gen_label: FOR <identifier> IN <discrete_range> GENERATE

[block_declarative part]

[begin]

concurrent_statements;

END GENERATE [gen_label];


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• The value in the discrete range must be globally static

• During the elaboration phase, the set of concurrent statements are replicated once for each value of the discrete range

• There is an implicit declaration for the generate identifier. No declaration is necessary for this identifier

• A label is required in the generate statement

Syntax

for-generate Example


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entity reg_xx is

generic (bus_w:integer := 4);

port(clk, clr: in std_logic;

d: in std_logic_vector (bus_w-1 downto 0);

q: out std_logic_vector (bus_w-1 downto 0));

end reg_xx;

architecture estructural of reg_xx is


component dff is

port (clk, clr, d, pr: in std_logic;

q: out std_logic);

end component;

begin

-- component instantiation with generate

reg_xx: for i in d’range generate

bit:dff port map(clk=>clk,clr=>clr,d=>d(i),q=>q(i),pr=>’0’);

end generate reg_xx;

end estructural;



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for-generate - exercise


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Hex-7Segment

Decoder

Counter 2

Counter 3

Counter 4

Counter 1

Sel

d

c

b

a



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entity for_generate_mux is

port(

c1, c2, c3, c4: in std_logic_vector (3 downto 0);

sel : in std_logic_vector (1 downto 0);

mux_o: out std_logic_vector (3 downto 0));

end for_generate_mux;

architecture behavioral of for_generate_mux is

component mux_4_2 is

port ( mux_din : in std_logic_vector (3 downto 0);

mux_dout : out std_logic;

sel : in std_logic_vector (1 downto 0));

end component;

type my_array is array(0 to 3) of std_logic_vector(3 downto 0);

signal test: my_array;



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begin

t: for i in mux_o'range generate

test(i) <= c1(i) & c2(i) & c3(i) & c4(i);

u1: mux_4_2 port map(

mux_din => test(i),

mux_dout => mux_o(i),

sel => sel);

end generate t;

end behavioral;



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High-Speed

ADC(Max104)

x8

x8

FPGA

.

.

.

DDR Clock

IBUFDS

IBUFDS



63

library IEEE;

use IEEE.STD_LOGIC_1164.all;

package VCOMPONENTS is

. . . .

-- IBUFDS: Differential Input Buffer

-- Virtex-II/II-Pro, Spartan-3

-- Xilinx HDL Libraries Guide version 11.1i

component IBUFDS

generic map ( IOSTANDARD => "LVDS_25")

port map (

O => O, -- buffer output

I => I, -- Diff_p clock buffer input

IB => IB -- Diff_n clock buffer input);

end component;

. . . .

end package VCOMPONENTS;

I

IB

O

Xilinx’s Primitive



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abus_diff_sstl2: for i in 0 to 7 generate

u_abus: IBUFDS

--generic map ( IOSTANDARD => "SSTL2_II")

port map(

O => a_bus(i),

I => a_bus_p(i),

IB=> a_bus_n(i)

);

end generate abus_diff_sstl2;

pbus_diff_sstl2: for i in 0 to 7 generate

u_pbus: IBUFDS

--generic map ( IOSTANDARD => "SSTL2_II")

port map(

O => p_bus(i),

I => p_bus_p(i),

IB=> p_bus_n(i)

);

end generate pbus_diff_sstl2;

I

IB

O

if-generate

• The if-generate statement allows for conditional selection of concurrent statements based on the value of an expression

• The expression must be a globally static expression

• The if-generate statement does not have else, elsif, endif


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g_label: IF <condition> GENERATE

[begin]

concurrent_statements;

END GENERATE [g_label];

Syntax: if-generate, concurrent statements can be condisionally

elaborated

if-generate


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component flip-flop is

port(clk, clr, d, p: in std_logic;

q, qb: out std_logic);

end component;

. . .

shift_reg_32: for i in 31 downto 0 generate

i31: if (i=31) generate

bit31: flip_flop port map(clk, clr, shift_in, gnd, internal(i-1), qb=>open);

end generate i31;

i30_1: if (i<31 and i>0) generate

bit30_1: flip_flop port map(clk, clr, internal(i), gnd, internal(i-1), qb=>open);

end generate i30_1;

i0: if (i=0) generate

bit0: flip_flop port map(clk, clr, internal(i), gnd, shift_out, qb=>open);

end generate i0;

end generate shift_reg_32;

if-generate


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if-generate


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Another important use of conditional generate statements is to conditionally include or omit part of the design. Usually depending on the value of a generic constant.

Typical examples: Logic added just for debugging purposesAdditional processes or component instances used only during simulation

if-generate


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entity my_system is

generic ( debug: boolean := true)

port (

. . .

);

end entity my_system;

architecture rtl of my_system is

. . .

begin

. . .

debug_comp: if debug generate

.. .

end generate debug_comp;

. . .

end architecture;

vhdl statements

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