VHDL 프로그래밍VHDL 래밍

1. 문법기초-간단한 조합 회로 및 문법

학습 목표학습 목표

VHDL 기술과 소프트웨어와 차이 파악

Signal assignment의 의미 파악

Architecture body의 개념 파악Architecture body의 개념 파악

Entity declaration의 개념 파악y 의 개 파악

Process 문의 사용법

Variable과 signal의 차이 파악

Library Use Package의 사용법Library, Use, Package의 사용법

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간단한 논리 회로 예제간단한 논리 회로 예제

A

B Xt1

B

BC

X

C

CA

Yt2

At3

Boolean 수식X = AB + BC, Y = BC + CAX AB BC, Y BC CA

t2=BC, X = AB + t2, Y = t2 + CA

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Boolean VHDLBoolean VHDL

t2=BC, X = AB + t2, Y = t2 + CAB l /l i

t2 <= B and C;

Boolean/logic op

t2 <= B and C;

X <= (A and B) or t2; 문장끝 ‘;’Y <= t2 or (C and A);

A i tAssignment op.

i bl ?variable?

signal (time, value)

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signal (time, value)

Wire ? In VHDLWire ? In VHDL

Signal (시간에 따라 다른 값을 가짐)Y <= t2 or (C and A);

X <= (A and B) or t2;X < (A and B) or t2;

t2 <= B and C;

T i l ?To use signals?

Define Before Use!!Define Before Use!!

Where?

Within Architecture body !!

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Architecture BodyArchitecture Body

architecture netlist of first is

i l 2 d l i signal t2 : std_logic;

begin

Y <= t2 or (C and A);

X <= (A and B) or t2;X < (A and B) or t2;

t2 <= B and C;

end netlist;end netlist;

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소프트웨어와 다른 점 ?소프트웨어와 다른 점 ?

각 문장이 병렬로 수행됨

따라서 문장 순서가 중요하지 않음따라서, 문장 순서가 중요하지 않음.

Concurrent Signal Assignment 문Concurrent Signal Assignment 문아래 두 개의 H/W 기술은 같은 동작아래 두 개의 / 기 동작

t2 <= B and C; X <= (A and B) or t2;;

X <= (A and B) or t2;

( ) ;

t2 <= B and C;

Y <= t2 or (C and A); Y <= t2 or (C and A);

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신호 할당 문은 언제 수행되나?신호 할당 문은 언제 수행되나?

RHS의 한 신호에 값의 변화가 있을 때

(Event가 생겼을 때)(Event가 생겼을 때)

X <= (A and B) or t2;X < (A and B) or t2;

AAB

t2

X

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E tit 선언?Entity 선언?

AB X

t1

BC

2CCA

Yt2

t3t3

Entity first is

Port (A, B, C : in std_logic;inout

( , , g ;

X, Y : out std_logic);

End first;

buffer

99//5353

End first;std_logic ??

std logicstd_logic

전선/node/wire를 모델링하는 type 가질 수 있는 값?

‘0’ Forcing 00 -- Forcing 0‘1’ -- Forcing 1‘Z’ -- High Impedanceg p‘-’ -- Don’t care‘U’ -- Uninitialized‘X’ Forcing UnknownX -- Forcing Unknown‘W’ -- Weak Unknown‘L’ -- Weak 0‘H’ -- Weak 1

IEEE의 std logic 1164 package에 정의된 typeIEEE의 std_logic_1164 package에 정의된 type(std_logic, std_logic_vector )

1010//5353

td l i 을 사용하려면?std_logic을 사용하려면?

library IEEE ;

use IEEE.std_logic_1164.all;

Library : 여러 가지 패키지 포함Library : 여러 가지 패키지 포함

Use : library의 특정 패키지 사용y

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Lib i d P kLibraries and Packages

Standard Library: IEEE, STDIEEE libraryIEEE librarystd_logic_1164

std_logic, std_logic_vectorstd_logic_arith, std_logic_unsigned, std_logic_signed, std_logic_textio STD library : 기본적으로 포함됨.

library WORK, STD;use STD STANDARD all;use STD.STANDARD.all;

1212//5353

A h B d E tit d l 외에?Arch. Body, Entity decl. 외에?Primary unitPrimary unitDesign unit

Package

declaration

Entity

declarationdeclaration

package Architecture

declaration

package

bodyArchitecture

body

Configuration

declarationSecondary unit

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A th t d ibAnother way to describe

Y <= t2 or (C and A); process (A,B,C)

i bl 2 d l iX <= (A and B) or t2;

t2 <= B and C;

variable t2 : std_logic;

begint2 <= B and C; begin

t2 := B and C;Sequential exec t2 : B and C;

X <= (A and B) or t2;S i i i li

Sequential exec.( ) ;

Y <= t2 or (C and A); Sensitivity list

RHS signalsend process;

RHS signals

In Sig Assignment1414//5353

In Sig. Assignment.

A hit t b d ( d t d)Architecture body (updated)

architecture netlist of first is

begin

process (A,B,C)p ( , , )

variable t2 : std_logic;

beginbegin

t2 := B and C;

X <= (A and B) or t2;X <= (A and B) or t2;

Y <= t2 or (C and A);

end process;end process;

end netlist;

1515//5353

Y< t id fY<=… outside of process

hi li f fi iarchitecture netlist of first is

begin

process (A,B,C)

variable t2 : std_logic;

begin

t2 := B and C;

X <= (A and B) or t2;

end process;p ;

Y <= (B and C) or (C and A);

end netlist;end netlist;

No Problem?1616//5353

No Problem?

T h AND t ?To share AND gate ?

architecture netlist of first is

Signal t2 : std logic;Signal t2 : std_logic;

begin

t2 B d Ct2 <= B and C;

process (A, B, t2)

b ibegin

X <= (A and B) or t2;

end process;

Y <= t2 or (C and A);

end netlist;

1717//5353

Th d f t t tThe order of statements

architecture netlist of first is

beginbegin

process (A,B,C)

i bl t2 td l ivariable t2 : std_logic;

begin

2 d t2 := B and C;

Y <= t2 or (C and A);

X <= (A and B) or t2;

end process;

end netlist;

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ALU (1/2)ALU (1/2)

library IEEE;use IEEE.std_logic_1164.all;_ g _use IEEE.std_logic_arith.all;use IEEE.std_logic_unsigned.all;

entity alu isport (p (

A, B, M : IN std_logic_vector(2 downto 0);Y : out std_logic_vector(2 downto 0);CO : out std logicCO : out std_logic);

end alu;

1919//5353

ALU (2/2)hit t b h f l i

ALU (2/2)architecture behav of alu issignal temp : std_logic_vector(3 downto 0);begin

y <= temp(2 downto 0);y <= temp(2 downto 0);CO <= temp(3);

process (A, B, M)beginbegin

temp <= (others => '0');case M is

when "000" => temp(2 downto 0) <= not A;when 000 > temp(2 downto 0) < not A;when "001" => temp(2 downto 0) <= A xor B;when "010" => temp(2 downto 0) <= A or B;when "011" => temp(2 downto 0) <= A and B;p( )when "100" => temp <= ('0' & A) + B;when "101" => temp <= ( A(2) & A) + (not (B(2) & B)) + 1;when "110" => temp <= ('0' & A) + 1;when others => temp(2 downto 0) <= A;

end case;end process;

2020//5353

end behav;

문법 기초문법 기초

주석, 식별자, Literal 상수

Object class(객체의 종류)

variable signal constant filevariable, signal, constant, file

Object Data type

Scalar, composite, file, access

O t ( ith ti & l i l)Operators (arithmetic & logical)

Design units & LibrariesDesign units & Libraries

2121//5353

Comments in VHDLComments in VHDL

‘--’로 시작, 행의 끝까지

-- this is a comment

Entity test is

. . .

End test;

-- the beginning of architecture

. . .

2222//5353

Identifiers in VHDLIdentifiers in VHDL

Identifier (식별자) – 변수, 신호, 상수, name 등.

Letter로 시작Letter로 시작

<< “VHDL은 대소문자 구별이 없음!!” >>

다음에 letter, digit, ‘_’가 옴.

‘_’ (underscore)는 연속해 올 수 없음!

2323//5353

Literals in VHDLLiterals in VHDL

정수형 literal

21, 0, 1E2, 123_000

실수형 literal실수형 literal

11.0, 0.436, 3.141_592_6, 2.0E+4

문자형 literal

‘1’ ‘A’ ‘%’1 , A , %

2424//5353

Literals in VHDL (계속)Literals in VHDL (계속)

Base를 포함한 숫자형 literal

2#1111 1100# 16#FC#2#1111_1100#, 16#FC#,

016#0FC#, 7#510# (모두 252 의미),

스트링 literal

“ d# d ”“ad# sd ”

비트 스트링 literal

Prefix: B, O, X (Binary, Octal, Hexa)

X”F FF” O”7777”X”F_FF”, O”7777”, B”1111_1111_1111”

2525//5353

Objects in VHDLObjects in VHDL

Object: 사용자가 정의해서 사용하는 객체들

Object class(객체의 종류): 사용방식Object class(객체의 종류): 사용방식

variables, signals, constants, files, g , ,

Object type(객체의 type): 데이터유형

Scalar, composite, file, access

2626//5353

Object data typesObject data types

VHDL object types

scalar type composite typeaccess type File type

enumeration real Physical recordarrayIntegerenumeration real Physical yInteger

2727//5353

Object class (constant)Object class (constant)

변경불가

Entity, architecture, process, package 내에서 선언 가능내에서 선언 가능

예:

Constant vcc: real := 4.5;

C t t fi bit t “1010”Constant five : bit_vector := “1010”;

2828//5353

Object class (variable)Object class (variable)

변경 가능 (즉시 변경됨 – signal과 차이)

Process, subprogram(proc., func.)내에서만선언 가능

예:

i bl i d i t 1 t 60variable index : integer range 1 to 60;

variable R : std logic vector(7 downto 0); _ g _ ( )

할당연산자 (variable assignment operator)

R “10101111” i d 27R := “10101111”; index := 27;

2929//5353

Object class (signal)Object class (signal)

Entity, architecture내에서 선언, process 내에서는 선언 불가서는 선언 불가.

Entity decl.의 port들은 모두 signal임.

선언 예:

Signal count : integer range 1 to 31;Signal count : integer range 1 to 31;

Signal ground : bit := ‘0’;

할당 연산자: 신호 (time, value) pair로 표현

Ground <= ‘0’; count <= 23 after 20 ns;Ground <= 0 ; count <= 23 after 20 ns;

3030//5353

Object class (file)Object class (file)

VHDL-87에서 (IEEE std 1076-1987)

File <id> : <name> is [in|out] <logical name>;File <id> : <name> is [in|out] <logical_name>;

File infile : TEXT is in “sample.dat”;

VHDL 93 (IEEE std 1076 1993)VHDL-93 (IEEE std 1076-1993)

File <id> : <file_type_name> [open file open mode] is <logical name>file_open_mode] is <logical_name>

File infile : text open read_mode is “sample.dat”

File infile : text;File infile : text;

file_open(infile, “sample.dat”, read_mode);

fil l (i fil )file_close(infile)

3131//5353

Object data type (scalar type)Object data type (scalar type)

Enumeration type : ordered listStd_ulogic, std_logic, bit 등Type bit is (‘0’, ‘1’);type state is (s0, s1, s2);

Integer typeInteger type Real type Physical type : 시간 등 단위가 있는 수Type time is range -…. To + ….;Unitsfs; -- femto secondfs; femto secondps = 1000 fs; ns = 1000 ps;. . .End units

3232//5353

Object data type (composite)Object data type (composite)

Array type : 주의!!: 첨자표시 ‘(‘, ‘)’Type string is array (positive range <> ) of

character;Type mem is array(0 to 1023, 7 downto 0) of bit;

R d tRecord typeType instruction is recordO fi ld : OPR;Op_field : OPR;OPD1 : integer range 0 to 127;OPD2 : integer range 0 to 127;OPD2 : integer range 0 to 127;End record;Variable cmd : instruction;Variable cmd : instruction;. . .cmd opd1 := 2; cmd opr := ADD;

3333//5353

cmd.opd1 := 2; cmd.opr := ADD;

Object data type (file type)Object data type (file type)

선언t <fil t > i fil f <t >;type <file_type_name> is file of <type_name>;

type vec_file is file of std_logic_vector(15 downto 0);

사용사용file fileA : vec_file is in “test.dat”;

3434//5353

Object data type (access)Object data type (access)

C에서 pointer type과 같음.C에서 pointer type과 같음.

정의는 되어 있으나 거의 사용되지 않음

3535//5353

SubtypeSubtype

이미 정의된 type(base type)에 어떤 조건을 추가해 새 이름의 t 정의건을 추가해 새 이름의 type 정의.

예:예:

Subtype eightval is integer range 0 to 7;

Signal b : subtype;

Subtype 사용하지 않고도 range제한가Subtype 사용하지 않고도 range제한가능.

Signal b : integer range 0 to 7;

3636//5353

산술 및 논리 연산자산술 및 논리 연산자

Logical operatorLogical operator

Relational operator

Adding operator

SiSign

Multiplying operatorMultiplying operator

기타 operator

3737//5353

연산자 우선 순위연산자 우선 순위

구분 종류우선순위

구 류순위

논리연산자 and, or, nand, nor, xor 6리 자 , , , ,

관계연산자 =, /= , <, >, >=, <= 5

덧셈연산자 +, -, & 4

부호 + 3부호 +, - 3

곱셈연산자 *, /, mod, rem 2곱셈연산자 , /, mod, rem 2

기타연산자 **, abs, not 1

3838//5353

논리연산자 사용 예논리연산자 사용 예

잘못된논리 올바른논리연산자연산자사용예 사용예

A < ( and ) or ;A <= x and y or zA <= x nor y nor z;

A <= (x and y) or z ;B <= (x nor y) nor z;

A <= x nor y nor z;y

C <= x and y and z;

3939//5353

Concatenation연산자 사용 예Concatenation연산자 사용 예

signal sig6 : std_logic_vector(5 downto 0);( )signal sig4 : std_logic_vector(3 downto 0) ;

signal sig3 : std_logic_vector(2 downto 0);i l i 2 td l i t (1 d t 0)signal sig2 : std_logic_vector(1 downto 0);

signal S1 : std_logic_vector(3 downto 0);i l S2 : td l i t (4 d t 0);signal S2 : std_logic_vector(4 downto 0);

sig3 <= sig2 & ‘1’ ;sig6 <= “00” & sig4;sig6 <= 00 & sig4; sig8 <= sig2 & sig6;S1 <= “00” & “10” ;S1 <= 00 & 10 ;S2 <= ‘0’ & S1;

4040//5353

Remainder OperatorRemainder Operator

Integer division and remainder are defined by the following relation:by the following relation:

A = (A/B)*B + (A rem B)

where (A rem B) has the sign of A and an absolute value less than the absolute value of B.a ue o

4141//5353

Modulus OperatorModulus Operator

The result of the modulus operation is such that (A mod B) has the sign of B and that (A mod B) has the sign of B and absolute value less than the absolute value f B i dditi f i t l N of B; in addition, for some integer value N,

this result must satisfy the relation:

A = B*N + (A mod B)A = B*N + (A mod B)

4242//5353

/ rem mod 연산자의 사용 예/, rem, mod 연산자의 사용 예

A B A/B A rem B A mod B

11 4 2 3 3

11 -4 -2 3 -1

-11 4 -2 -3 1

-11 -4 2 -3 -311 4 2 3 3

4343//5353

Work LibraryWork Library

WORK library ?

현재 읽히는 VHDL 코드의 분석결과가default로 저장되는 위치.

라이브러리: 논리적 이름, 물리적 이름

물리적 이름: HDD의 디렉토리 (f ld ) 이름물리적 이름: HDD의 디렉토리 (folder) 이름

논리적 이름: VHDL 소스 내에서의 lib.이름

둘간 대응 시키는 일 simulator의 환경 설정에서 할 일서 할 일

4444//5353

VHDL analysisVHDL analysis

WORK 2VHDL

analyzer

WORK LIB2

VHDL

IEEE STD

VHDLsources

library

VHDL

simulatorSimulation

commands

simulation results

( f simulator commands(waveform or text)

4545//5353

표준 자료형과 표준 패키지표준 자료형과 표준 패키지

중요 표준 패키지

std.textio, std.standard

ieee std logic 1164ieee.std_logic_1164,

std_logic_unsigned, std_logic_arith

4646//5353

Std standard 패키지Std.standard 패키지

Boolean, character, integer, real, time, string, bit, bit_vector : type

Natural positive : subtypeNatural, positive : subtype

4747//5353

Std textio 패키지Std.textio 패키지

Plain text file 입출력 위한 데이터 타입, 함수선언선언

Type: TEXT(file of character), LINE(access t i )string)

Input(“STD_INPUT” file), output(“STD_OUTPUT” file) : file object

READ, WRITE, READ LINE, WRITE LINE 등READ, WRITE, READ_LINE, WRITE_LINE 등입출력 function

4848//5353

IEEE std logic 1164 packageIEEE.std_logic_1164 package

Std_logic, std_ulogicStd logic vector std ulogic vectorStd_logic_vector, std_ulogic_vector“and”, “nand”, “or”, “nor”, “xor”, “xnor”, “not” (logical operator )not (logical operator )Type conversion functionsT bit( td ( )l i bit)To_bit(std_(u)logic bit)To_bitvector, to_stdUlogic(bit std_Ulogic)

(To_stdLogicVector(bitvector std_logic_vector

Falling_edge, rising_edge : 함수

4949//5353

Std logic 1164 std logic arithStd_logic_1164, std_logic_arith

std_logic_1164

std_logic std_logic_vector

unsigned signed

std_logic_arith

t UNSIGNED i (NATURAL ) f STD LOGICtype UNSIGNED is array (NATURAL range <>) of STD_LOGIC;

type SIGNED is array (NATURAL range <>) of STD_LOGIC;

5050//5353

Std logic unsigned/signedStd_logic_unsigned/signed

산술/관계연산자 (내부적으로 unsigned/signed type으로 해석해서 계산하는) – overloaded둘 중 하나만 사용해야 혼돈이 없음둘 중 하나만 사용해야 혼돈이 없음.예: function "+"(L: std logic vector; R: std logic vector)function (L std_logic_vector; R std_logic_vector) return STD_LOGIC_VECTOR;function "+"(L: STD_LOGIC_VECTOR; R: INTEGER)

t STD LOGIC VECTOR;return STD_LOGIC_VECTOR;function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD LOGIC VECTOR;return STD_LOGIC_VECTOR;function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;f ti " "(L STD LOGIC R STD LOGIC VECTOR)function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;

5151//5353

Std logic unsigned/signedStd_logic_unsigned/signed

필요성?

내부 계산을 signed로 하고 싶을 때

Library ieee;Library ieee;

Use ieee.std_logic_1164.all;

Use ieee.std_logic_arith.all;

Use ieee std logic signed all;Use ieee.std_logic_signed.all;

5252//5353

Std logic arithStd_logic_arith

Integer, unsigned, signed, std_logic_vector간 conversion 함수 제공예: (size: 결과의 비트 수)예: (size: 결과의 비트 수)function CONV_INTEGER(ARG: INTEGER)

return INTEGER;…function CONV_INTEGER(ARG: SIGNED)

return INTEGER;return INTEGER; function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER)

return UNSIGNED;…function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER)

return UNSIGNED;return UNSIGNED;function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER)

return SIGNED;

5353//5353

…