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EE 330 Design Project:

Automated Irrigation System

Spring 2013

Authors: Marshall Hilgemann, Watson Mulder

Lab Section: C

Table of Contents

Project Overview……………………………………………………………………………….3

Introduction………………………………………………………………………………3

Objective…………………………………………………………………………3

Application……………………………………………………………………….3

Control Mode Behavior…………………………………………………………………3

Internal Timer……………………………………………………………………3

Ambient Light Level Transitions……………………………………………….3

Soil Moisture Sensors…………………………………………………………..3

System Input/Output Design………………………………………………………………...4

Soil Moisture Sensor (SMS) Testing………………………………………………….4

SMS Circuit Construction and Simulation…………………………………………….5

Output Valve Drivers……………………………………………………………………9

System Digital Logic Control………………………………………………………………11

Design Overview……………………………………………………………………….11

User Interface…………………………………………………………………………..12

Verilog Code……………………………………………………………………………14

Simulation………………………………………………………………………………14

RTL Synthesis………………………………………………………………………….19

Encounter Issues………………………………………………………………………22

Response……………………………………………………………………………….23

Encounter Export to Cadence………………………………………………………..23

Conclusion………….…………………………………………………………………………25

Appendix…………….…………………………………………………………………………26

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Project Overview

IntroductionObjective

The objective of this project is to design an automated irrigation system that can manage the irrigation of multiple plants with a single unit. The unit should be capable of a running for long periods accurately without a great deal of power consumption.

Application

This system would be ideally used for small scale agriculture in the third world, urban gardening, or other cases in which a small reservoir could support a cluster of planters. As the system can operate on battery power and has low energy consumption, it could sustain vegetation for long periods with periodic calibration and filling of the reservoir.

Control Mode BehaviorInternal Timer

An internal timer will run and trigger a watering cycle whenever the counter reaches zero. This internal time is stored in 24 hr format and displayed to the user on the seven-segment display during nominal operation. Both the current time and the counter time can be set by user input. During the setting of these values, the unit's display will reflect the changes.

Ambient Light Level Transitions

To minimize water lost to evaporation, it is beneficial to water during early morning hours or early evening. With light transition triggering, a water cycle will start when the overall ambient light level transitions from high to low intensity (dusk) and low to high intensity (dawn). This sensor will be implemented with a photoresistor as part of a voltage divider which will trigger an inverter input to the digital system. As there is a great deal of variation in photoresistors’ performance, the voltage divider will have to be calibrated with an external resistor to achieve the appropriate threshold setting. However, as a drastic change in ambient light is needed to affect the photoresistor’s resistance, a passing shadow or artificial light source will not accidentally trigger a watering cycles.

Soil Moisture Sensors

The system also has a bank of inputs for reading soil moisture levels. When soil moisture is detected at too low a level, a watering cycle is triggered. There are 10 moisture sensors inputs such that each of the planters has its own independent sensor reading and that corresponding valve is triggered from that reading. Additionally, each moisture sensor has 3 channels of differing trigger attenuation so that each sensor has three possible thresholds of low moisture--tropical plants can have a higher triggering moisture than arid plants.

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Moisture sensors consist of two probes planted in the soil. A reference voltage is applied to the first probe, and the measured voltage of the second probe can determine the conductivity of the soil. As soil moisture increases, the conductivity of the soil increases and the probe’s measured voltage decreases. The measured voltage is then attenuated by internal resistive elements and the conditioned voltage is feed to a digital inverter. Using three physically separate circuits of resistive elements and identical digital inverters, each sensor input has three A/D converters with different input triggering voltages. Selection of these separate channels will be done physically, by plugging the sensor probe into the desired port. Each sensor has four connections--a common reference voltage out, and three trigger channel inputs: dry, wet, very wet.

Polling of the moisture sensors occurs every hour, with a reference voltage switched on by the internal clock. The reference voltage is held for minute to get a reasonable reading, while not draining the power supply greatly. At worst case, with a full load of tropical plants on every channel, the sensor reading will contribute a maximum power dissipation of around 50 mW per hour.

System Input/Output Design

Soil Moisture Sensor (SMS) TestingWe tested an implementation of the sensors in the lab and in the field using two galvanized screws as probes. These work well as they have a high conductivity, are cheap and easy to acquire, and will not oxidize quickly. The probes were placed 1.5 inches apart during testing.

The results of our experiments to approximate soil resistance appear in Table 1 below:

Table 1: Soil Moisture Test Results

These values of resistance were simplified for implementation as 3 kΩ, 2 kΩ, and 1 kΩ. They correspond to the three threshold resistances for the three modes of operation of the SMS system.

SMS Circuit Construction and Simulation

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Figure 1: Soil Moisture Testing

Soil Condition Resistance

Dry 2.901 kΩ

Wet 1.96 kΩ

Very Wet 911 Ω

Next we went about building circuits that could realize this operation. We constructed voltage dividers with the simplified approximate resistances. They have this property: when the soil resistance is equal to or greater than the additional resistance, the input voltage drops below VDD/2. Using a standard inverter, high output is triggered whenever the soil moisture is below the specified trigger level of that channel. Again, each sensor consists of three inverters with resistors, one unit for each setting. The unit for the dry setting can be seen in Figure 2:

Figure 2: Dry Inverter Schematic and Symbol

A voltage and resistance will be connected to V in. For this setup, if the connected soil resistance is higher than 3 kΩ, then Vout will come up to within 10% of VDD. In Figure 3, the layout shows how it is set up on-chip, and the extracted version proves the resistance value:

Figure 3: Dry Inverter Layout and Extraction

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The inverter circuits for Wet Setting and Very Wet Setting are very similar to that of Dry Setting, except that they have different resistances built in. Their models can be seen in Figures 4 and 5:

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Figures 4 & 5:

Wet and Very

Wet Inverters,

with Symbols

and Extracted

Layouts

Next, we tested the inverter circuits to verify their characteristics. We set up the following test circuit in Figure 6 to see how they would react to different values of soil resistance (this test circuit setup is the same for all three inverter circuits). The soil resistance is modeled as a variable resistor:

Figure 6: Inverter Test Circuit

Then we swept the soil resistance from 0 to 10 kΩ, and watched the output voltages (Figures 7a, 7b, and 7c). Notice the decreasing threshold resistance, from Fig. 7a to 7c:

Figure 7a: Dry Inverter Output Voltage as a Function of Resistance

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Figure 7b: Wet Inverter Output Voltage as a Function of Resistance

Figure 7c: Very Wet Inverter Output Voltage as a Function of Resistance

The lower threshold resistance in Fig. 7b and 7c means that irrigation is triggered more easily in the “wetter” settings. For instance, if you have a tropical type of plant that needs lots of water, then you would choose Very Wet Setting, so that the soil is kept very moist.

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Output Valve DriversWater flow in the system is controlled by a latching solenoid valve (Figure 8). Current passing through the solenoid induces a magnetic field that forces open a metal pin.

The solenoid valve is made by General Imsubs. Technical specifications were obtained from the supplier’s datasheet. This valve can operate with a switching voltage anywhere from 3.5V to 12V. Suggested current for operation at 6V is 670mA. The given resistance of the valve is 10Ω. To make sure it has no trouble latching, the desired target output current should be slightly higher. To achieve this high current signal, a special driving output circuit must be designed.

For the desired output, inverters must be sized larger than usual. In addition, to achieve this high current, we assumed the use of 9V supplies for this inverter. We set up an equation for the output current when the input is 0 (this would trigger a high output voltage). The equation for current through the PMOS transistor is

I=V out10

=µCoxwL (V GS−V Tp−V DS

2 )V DS

I=V out10

=33×10−6 wL

(−6+0.55−V out−6

2)(V out−6)

Simplifying the equation in terms of w/L, we get

I=0.55¿¿

If we let I = 600 mA, then w/L of this PMOS is approximately 3000. We decided that the most realistic way to implement this would be to let w/L = 100, and put 30 of these transistors in parallel. For equal rise/fall times, the w/L of the NMOS was decided to be one third of this.

Implementing this in Virtuoso, the PMOS transistors have width 60µm and length 600nm, while the NMOS transistors have width 20µm and length 600nm. In Fig. 9 at right, a layout of a single inverter is shown.

The schematic of all our output inverters can be seen below in Figure 10:

Figure 10: Output Driving Inverters

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Figure 8: Output Valve

Figure 9 (right): Output Inverter Layout

Next, we verified the operation of this circuit with simulation. The test circuit we set up for this task is shown in Figure 11. The solenoid valve is modeled as a 10Ω resistor:

Figure 11: Output Test CircuitThe results of this simulation can be seen in Figure 12. As you can see from the waveforms, when the input is a logical 0, then the output current is a healthy 634mA at 6.3V. This meets the given specifications for the solenoid valve to properly latch.

Figure 12: Output Simulation Results

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System Digital Logic Control

Design Overview

To ensure efficient operation and proper feedback to user control flow, the digital system requires a hierarchical structure. Top priority is given to the user input--this forces the quick display feedback to the user and ensures calibration is top priority. Next level priorities are clocking and sensor input. Sensor triggering has a slightly higher priority as it can run independently of timing.

All other logic events and operations are dependent on the internal real-time clock. To ensure the clock is accurate, it is driven by an external crystal timer.

The block diagram of systems and control flow appears below in Figure 13.

Figure 13: System Block Diagram

As the system is a complex and contains multiples of other systems, an approach of designing individual modules and using instantiation seems best.

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User InterfaceThe system requires a large number of user input signals. With many of the signals being similar, it makes sense for these signals to share a physical button that shifts function depending on mode of operation.

The physical user interface can be seen below in Figure 14 with two increment buttons, three mode set buttons, three mode enable switches, and four seven-segment displays.

The three toggle switches enable triggering of three modes--Mode 1: Timer triggering, Mode 2: Light sensor triggering, Mode 3: Moisture sensor triggering. The set buttons, when held, change the functionality of the increment buttons and change the visual feedback of the seven-segment displays. When no set buttons are held, the seven-segment display shows the real time clock’s current time in 24 hour format (HrHr:MinMin).

Figure 14: User Interface

To update the current time, the set clock button is held and the increment buttons add one hour or one minute to the current time registers (see Figure 15). Adding time loops back to zero minutes after 59 minutes and zero hours after 23 hours.

Figure 15: Setting Clock

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To set the watering cycle duration of each channel of the system, the set cycle button is held (see Figure 16). The seven-segment display changes to show ‘C’ followed by the selected channel (0-9) and then the current duration of that channel in minutes. Cycle duration can last from 1 to 64 minutes. The increment buttons now will add an additional minute to the duration or move to the next selected channel. The display will update to show the new current channel, and both increment controls will loop back to the first available setting after passing the last (channel 9 -> channel 0, 64 min -> 1 min).

Figure 16: Setting Cycle Duration

To set the triggering timer length, hold the set timer button (see Figure 17). This changes the first two seven-segment displays to show a “T” followed by the current timer length in hours. The first increment button now adds one hour to the current timer length and disables the second increment button. Valid timer lengths are from 1 to 64 hours; and as before, incrementing past the top valid time loops back to the lowest time (64hrs -> 1hr).

Figure 17: Setting Time Between Cycles

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Verilog CodeCoding was completed by defining the system’s archetype modules and then referencing instances of those modules in a top-level module. The code is included in the Appendix.

SimulationSimulation was performed on a test bench port of the system. The timescale is set to 1 second, as it is the smallest resolution of the system’s operations, and the external clock is tuned to input an accurate 1-second timing pulse to control the clock. Gate delay is not a major issue as the operation is not extremely time-critical; irrigation delay of a second or so will not be harmful.

Included below are various screenshots of simulation waveforms showing functionality.

Figure 18: Freeing running clock: seven-segment display updates showing incrementing minutes and hours.

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Figure 19: Updating the current time of the clock by forcing set clock and pulsing hour increment.

Figure 20: All channels turned on by timer reaching 1 hour trigger with mode 1 enabled.

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Figure 21: Setting the timer length to 26 hrs by forcing set timer and pulsing hour increment.

Figure 22: All channels turn on 26 hrs later when trigger time reached.

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Figure 23: Setting the cycle time at channel 4 to be longer than initial 5 minute setting.

Figure 24: Channel 4 (Valve4) now has longer time on.

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Figure 25: Light transitions trigger all channels.

Figure 26: Soil moisture sensors (SMS) trigger their designated channels. Light transition triggers all.

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Figure 27: All trigger modes enabled, various events triggering.

RTL SynthesisThe code was imported for optimization in the RTL compiler. The block structure with sub-modules appears below.

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Figure 28: Top level structure.

Figure 29: Zoomed view of top level.

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Figure 30: Zoomed view of top level.

Figure 31: Inside the ‘counter’ module.

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Figure 32: Inside a cycle register module.

Encounter IssuesRTL compiler successfully synthesized an optimized design and the RTL was imported into Encounter. However, on synthesis, Encounter fails to place due to an error with an intermediate placed buffer:

Figure 33: Encounter Error.

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As this buffer does not appear in the source code or the synthesized code, it is created by the Encounter process and the source of the problem is not clear.

Response To overcome this problem, the design was re-coded into a single all-encompassing module and optimized to use the fewest number of assignments possible. However, the error persisted and thus was not related to the instantiation or assignment structuring.

Rewriting the code another time at another level, it was found that there were multiple conditional assignments which were not being handled properly. Restructuring the code to have one assignment with sub-assignments fixed the bug. This code is included in the Appendix.

Encounter Export to CadenceThe layout synthesis successfully completed and was imported into Cadence. After several slight adjustments of spacing and removal of label materialization, the design passed DRC verification with zero errors and few warnings. The next few figures are screenshots of the resulting layout:

Figure 34: Design layout.

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Figure 35: Layout details.

Figure 36: Layout output pins detail.

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Figure 37: DRC report of zero errors.

ConclusionWith a simulation-verified design, verified layout, and simulation-verified design of the input and output channels, all portions of the system are complete to the extent computer modeling can provide. The design operates successfully in the computerized realm, and we anticipate that this irrigation system would be feasible to implement in the real world as well.

In creating this design, we met all necessary specifications; although the task proved to be more arduous than we first anticipated, through much perseverance, we accomplished our objectives. It is our sincere desire that this design would be useful for some practical purpose in the future.

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Appendix

Verilog Source Revision 5module toponemod (hrplus, minplus, modeenable1, modeenable2, modeenable3, setclock, setcycle, setcounter, cclk, sms0, sms1, sms2, sms3, sms4, sms5, sms6, sms7, sms8, sms9, lightin, osegoutA, osegoutB, osegoutC, osegoutD, out0, out1, out2, out3, out4, out5, out6, out7, out8, out9,Vref);//buttons input hrplus, minplus; //mode enable switch input modeenable1, modeenable2, modeenable3;

input setclock; input setcycle; input setcounter; input cclk;

input sms0, sms1, sms2, sms3, sms4, sms5, sms6, sms7, sms8, sms9;input lightin;

output [6:0] osegoutA;output [6:0] osegoutB;output [6:0] osegoutC;output [6:0] osegoutD;output Vref;

output out0, out1, out2, out3, out4, out5, out6, out7, out8, out9;

reg [6:0] segoutA;reg [6:0] segoutB;reg [6:0] segoutC;reg [6:0] segoutD;

reg vrefreg;reg [3:0] cycsel;

reg [3:0] disphr1;reg [3:0] disphr2;

reg [3:0] disp1;reg [3:0] disp2;

reg [3:0] seg7a;reg [3:0] seg7b;reg [3:0] seg7c;reg [3:0] seg7d;

reg [3:0] hour1;reg [3:0] minute1;reg [3:0] hour2;reg [3:0] minute2;

reg [5:0] seconds;reg countertrig;

reg hrover;reg minover;

reg run0;reg run1;reg run2;reg run3;reg run4;reg run5;reg run6;reg run7;

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reg run8;reg run9;

reg trigger0; reg trigger1; reg trigger2: reg trigger3; reg trigger4; reg trigger5; reg trigger6; reg trigger7; reg trigger8; reg trigger9; reg [5:0] cycledisplay;

reg [5:0] cycle0;reg [5:0] count0;

reg [5:0] cycle1;reg [5:0] count1;reg [5:0] cycle2;reg [5:0] count2;reg [5:0] cycle3;reg [5:0] count3;reg [5:0] cycle4;reg [5:0] count4;reg [5:0] cycle5;reg [5:0] count5;reg [5:0] cycle6;reg [5:0] count6;reg [5:0] cycle7;reg [5:0] count7; reg [5:0] cycle8;reg [5:0] count8;reg [5:0] cycle9;reg [5:0] count9;

reg [5:0] setcount;reg [5:0] curcount;

////clock assignmentalways @ (cclk) begin///////////timer control if (modeenable1 && countertrig) begin trigger0 = 1'b1; run0 = 1'b1; trigger1 <= 1'b1; run1 <= 1'b1; trigger2 <= 1'b1; run2 <= 1'b1; trigger3 <= 1'b1; run3 <= 1'b1; trigger4 <= 1'b1; run4 <= 1'b1; trigger5 <= 1'b1; run5 <= 1'b1; trigger6 <= 1'b1; run6 <= 1'b1; trigger7 <= 1'b1; run7 <= 1'b1; trigger8 <= 1'b1; run8 <= 1'b1; trigger9 <= 1'b1; run9 <= 1'b1; end ///sensor control if (modeenable2 && lightin) begin

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trigger0 <= 1'b1; run0 <= 1'b1; trigger1 <= 1'b1; run1 <= 1'b1; trigger2 <= 1'b1; run2 <= 1'b1; trigger3 <= 1'b1; run3 <= 1'b1; trigger4 <= 1'b1; run4 <= 1'b1; trigger5 <= 1'b1; run5 <= 1'b1; trigger6 <= 1'b1; run6 <= 1'b1; trigger7 <= 1'b1; run7 <= 1'b1; trigger8 <= 1'b1; run8 <= 1'b1; trigger9 <= 1'b1; run9 <= 1'b1; end if (modeenable3 && sms0) begin trigger0 <= 1'b1; run0 <= 1'b1; end if (modeenable3 && sms1) begin trigger1 <= 1'b1; run1 <= 1'b1; end if (modeenable3 && sms2) begin trigger2 <= 1'b1; run2 <= 1'b1; end if (modeenable3 && sms3) begin trigger3 <= 1'b1; run3 <= 1'b1; end if (modeenable3 && sms4) begin trigger4 <= 1'b1; run4 <= 1'b1; end if (modeenable3 && sms5) begin trigger5 <= 1'b1; run5 <= 1'b1; end if (modeenable3 && sms6) begin trigger6 = 1'b1; run6 = 1'b1; end if (modeenable3 && sms7) begin trigger7 <= 1'b1; run7 <= 1'b1; end if (modeenable3 && sms8) begin trigger8 <= 1'b1; run8 <= 1'b1; end if (modeenable3 && sms9) begin trigger9 <= 1'b1; run9 <= 1'b1;end

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/////cycle regs and cycle behavior trigs if ((cycsel==4'h0)&&(setcycle)&& hrplus) begin cycle0 <= (cycle0 + 6'h1); if (cycle0==6'b111100) cycle0 <=6'h0; end if(run0 && minover) count0 <= (count0 + 6'h1);if((count0==cycle0)&& minover) begin count0<= 6'h0; run0<= 1'b0; trigger0<=1'b0; end if ((cycsel==4'h0)&&(setcycle) && hrplus) count0 <= 6'h0;

if ((cycsel==4'h1)&&(setcycle)&& hrplus) begin cycle1 <= (cycle1 + 6'h1); if (cycle1==6'b111100) cycle1 <=6'h0; end if(run1 && minover) count1 <= (count1 + 6'h1);if((count1==cycle1) && minover) begin count1<= 6'h0; run1<= 1'b0; trigger1<=1'b0; end if ((cycsel==4'h1)&&(setcycle)&& hrplus) count1 <= 6'h0; if ((cycsel==4'h2)&&(setcycle) && hrplus) begin cycle2 <= (cycle2 + 6'h1); if (cycle2==6'b111100) cycle2 <=6'h0; end if(run2 && minover) count2 <= (count2 + 6'h1);if((count2==cycle2)&& minover) begin count2<= 6'h0; run2<= 1'b0; trigger2<=1'b0; end if ((cycsel==4'h2)&&(setcycle)&& hrplus) count2 <= 6'h0;

if ((cycsel==4'h3)&&(setcycle)&& hrplus) begin cycle3 <= (cycle3 + 6'h1); if (cycle3==6'b111100) cycle3 <=6'h0; end if(run3&& minover) count3 <= (count3 + 6'h1); if((count3==cycle3)&& minover) begin count3= 6'h0; run3= 1'b0; trigger3=1'b0; end if ((cycsel==4'h3)&&(setcycle)&& hrplus) count3 = 6'h0;

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if ((cycsel==4'h4)&&(setcycle)&& hrplus) begin cycle4 <= (cycle4 + 6'h1); if (cycle4==6'b111100) cycle4 <=6'h0; end if(run4&& minover) count4 <= (count4 + 6'h1);if((count4==cycle4)&& minover) begin count4<= 6'h0; run4<= 1'b0; trigger4<=1'b0; end if ((cycsel==4'h4)&&(setcycle)&& hrplus) count4 <= 6'h0;


if ((cycsel==4'h6)&&(setcycle)&& hrplus) begin cycle6 <= (cycle6 + 6'h1); if (cycle6==6'b111100) cycle6 <=6'h0; end if(run6&& minover) count6 <= (count6 + 6'h1);if((count6==cycle6)&& minover) begin count6<= 6'h0; run6<= 1'b0; trigger6<=1'b0; end if ((cycsel==4'h6)&&(setcycle)&& hrplus) count6 <= 6'h0; if ((cycsel==4'h7)&&(setcycle)&& hrplus) begin cycle7 <= (cycle7 + 6'h1); if (cycle7==6'b111100) cycle7 <=6'h0; end if(run7&& minover) count7 <= (count7 + 6'h1);if((count7==cycle7)&& minover) begin count7<= 6'h0; run7<= 1'b0; trigger7<=1'b0; end if ((cycsel==4'h7)&&(setcycle)&& hrplus) count7 <= 6'h0;

if ((cycsel==4'h8)&&(setcycle)&& hrplus)

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begin cycle8 <= (cycle8 + 6'h1); if (cycle8==6'b111100) cycle8 <=6'h0; end if(run8&& minover) count8 <= (count8 + 6'h1);if((count8==cycle8)&& minover) begin count8<= 6'h0; run8<= 1'b0; trigger8<=1'b0; end if ((cycsel==4'h8)&&(setcycle)&& hrplus) count8 <= 6'h0;


/////////////////////////////////////Counterif(setcounter && hrplus) begin setcount = (setcount + 6'h1); curcount = (setcount + 6'h1);end if ((setcounter)&&(setcount>6'b111100)&& hrplus) setcount <= 6'h0; if(hrover) curcount <= (curcount-6'h1);if ((curcount==0) && modeenable1) begin curcount <= (curcount + setcount); countertrig <= 1'b1; endelse countertrig<=1'b0;

///////////////////////////////////////Clock

if(setclock&& minplus) minute1 <= (minute1+4'h1); if(setclock&& hrplus) hour1 <= (hour1+4'h1); if(cclk) seconds <= (seconds+6'h1);

if (seconds >= 6'h3c) //if incr digit2 to 6 (60sec) begin minute1 <= (minute1+4'h1); //incr min seconds <= 6'h0; //reset digit2 min minover <= 1'b1; vrefreg <=1'b0; end if (minute1 >= 4'b1010) //if min 10 begin minute2 <= (minute2+4'h1); //next digit minute1 <= 4'h0;

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end if(minute2 >= 4'h6) ///if min 60 begin hrover <= 1'b1; vrefreg <=1'b1; hour1 <= (hour1+4'h1); ///incr hr minute2 <= 4'h0; end if (hour1 >= 4'hA) //if 10 hr begin hour2 <= (hour2+4'h1); hour1=4'h0; end if ((hour1>=4'h4)&(hour2==2)) //if 24hrs begin hour1=4'h0; hour2=4'h0; end if (cclk&&seconds!=6'h3c) begin seconds <= (seconds+6'h1); //else incr digit1 hrover <= 1'b0; minover <= 1'b0; end /////7segments casescase(seg7a) 4'b0000: segoutA = 7'b1111110; 4'b0001: segoutA = 7'b0110000; 4'b0010: segoutA = 7'b1101101; 4'b0011: segoutA = 7'b1111001; 4'b0100: segoutA = 7'b0110011; 4'b0101: segoutA = 7'b1011011; 4'b0110: segoutA = 7'b1011111; 4'b0111: segoutA = 7'b1110000; 4'b1000: segoutA = 7'b1111111; 4'b1001: segoutA = 7'b1111011; //letter C case 4'b1100: segoutA = 7'b1001110; //letter first half t case 4'b1101: segoutA = 7'b1110000; //letter second half t case 4'b1110: segoutA = 7'b1000000;endcase

case(seg7b) 4'b0000: segoutB = 7'b1111110; 4'b0001: segoutB = 7'b0110000; 4'b0010: segoutB = 7'b1101101; 4'b0011: segoutB = 7'b1111001; 4'b0100: segoutB = 7'b0110011; 4'b0101: segoutB = 7'b1011011; 4'b0110: segoutB = 7'b1011111; 4'b0111: segoutB = 7'b1110000; 4'b1000: segoutB = 7'b1111111; 4'b1001: segoutB = 7'b1111011; //letter C case 4'b1100: segoutB = 7'b1001110; //letter first half t case 4'b1101: segoutB = 7'b1110000; //letter secind half t case 4'b1110: segoutB = 7'b1000000;endcase

case(seg7c) 4'b0000: segoutC = 7'b1111110; 4'b0001: segoutC = 7'b0110000; 4'b0010: segoutC = 7'b1101101; 4'b0011: segoutC = 7'b1111001; 4'b0100: segoutC = 7'b0110011; 4'b0101: segoutC = 7'b1011011;

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4'b0110: segoutC = 7'b1011111; 4'b0111: segoutC = 7'b1110000; 4'b1000: segoutC = 7'b1111111; 4'b1001: segoutC = 7'b1111011; //letter C case 4'b1100: segoutC = 7'b1001110; //letter first half t case 4'b1101: segoutC = 7'b1110000; //letter secind half t case 4'b1110: segoutC = 7'b1000000;endcase

case(seg7d) 4'b0000: segoutD = 7'b1111110; 4'b0001: segoutD = 7'b0110000; 4'b0010: segoutD = 7'b1101101; 4'b0011: segoutD = 7'b1111001; 4'b0100: segoutD = 7'b0110011; 4'b0101: segoutD = 7'b1011011; 4'b0110: segoutD = 7'b1011111; 4'b0111: segoutD = 7'b1110000; 4'b1000: segoutD = 7'b1111111; 4'b1001: segoutD = 7'b1111011; //letter C case 4'b1100: segoutC = 7'b1001110; //letter first half t case 4'b1101: segoutD = 7'b1110000; //letter secind half t case 4'b1110: segoutD = 7'b1000000;endcase

//////display assignments

if ((!setcycle) && (!setcounter)) begin seg7d <= hour2; seg7c <= hour1; seg7b <= minute2; seg7a <= minute1; end if (setclock) begin seg7d <= hour2; seg7c <= hour1; seg7b <= minute2; seg7a <= minute1; end if (setcycle) begin seg7d <= 4'b1100; seg7c <= cycsel; seg7b <= disp2; seg7a <= disp1; end if (setcounter) begin seg7d <= 4'b1101; seg7c <= 4'b1110; seg7b <= disphr2; seg7a <= disphr1; end if (setcycle&& minplus) cycsel <= (cycsel+4'h1);

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if ((cycsel == 10)&& minplus) cycsel <= 4'h0; /////display casesif (setcounter&& hrplus)begincase (setcount)6'b000000: disphr1 = 4'h0;6'b000001: disphr1 = 4'h1;6'b000010: disphr1 = 4'h2;6'b000011: disphr1 = 4'h3;6'b000100: disphr1 = 4'h4;6'b000101: disphr1 = 4'h5;6'b000110: disphr1 = 4'h6;6'b000111: disphr1 = 4'h7;6'b001000: disphr1 = 4'h8;6'b001001: disphr1 = 4'h9;6'b001010: disphr1 = 4'h0;6'b001011: disphr1 = 4'h1;6'b001100: disphr1 = 4'h2;6'b001101: disphr1 = 4'h3;6'b001110: disphr1 = 4'h4;6'b001111: disphr1 = 4'h5;6'b010000: disphr1 = 4'h6;6'b010001: disphr1 = 4'h7;6'b010010: disphr1 = 4'h8;6'b010011: disphr1 = 4'h9;6'b010100: disphr1 = 4'h0;6'b010101: disphr1 = 4'h1;6'b010110: disphr1 = 4'h2;6'b010111: disphr1 = 4'h3;6'b011000: disphr1 = 4'h4;6'b011001: disphr1 = 4'h5;6'b011010: disphr1 = 4'h6;6'b011011: disphr1 = 4'h7;6'b011100: disphr1 = 4'h8;6'b011101: disphr1 = 4'h9;6'b011110: disphr1 = 4'h0;6'b011111: disphr1 = 4'h1;6'b100000: disphr1 = 4'h2;6'b100001: disphr1 = 4'h3;6'b100010: disphr1 = 4'h4;6'b100011: disphr1 = 4'h5;6'b100100: disphr1 = 4'h6;6'b100101: disphr1 = 4'h7;6'b100110: disphr1 = 4'h8;6'b100111: disphr1 = 4'h9;6'b101000: disphr1 = 4'h0;6'b101001: disphr1 = 4'h1;6'b101010: disphr1 = 4'h2;6'b101011: disphr1 = 4'h3;6'b101100: disphr1 = 4'h4;6'b101101: disphr1 = 4'h5;6'b101110: disphr1 = 4'h6;6'b101111: disphr1 = 4'h7;6'b110000: disphr1 = 4'h8;6'b110001: disphr1 = 4'h9;6'b110010: disphr1 = 4'h0;6'b110011: disphr1 = 4'h1;6'b110100: disphr1 = 4'h2;6'b110101: disphr1 = 4'h3;6'b110110: disphr1 = 4'h4;6'b110111: disphr1 = 4'h5;6'b111000: disphr1 = 4'h6;6'b111001: disphr1 = 4'h7;6'b111010: disphr1 = 4'h8;6'b111011: disphr1 = 4'h9;6'b111100: disphr1 = 4'h0;6'b111101: disphr1 = 4'h1;

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6'b111110: disphr1 = 4'h2;6'b111111: disphr1 = 4'h3;endcase

case (setcount)6'b000000: disphr2 = 4'h0;6'b000001: disphr2 = 4'h0;6'b000010: disphr2 = 4'h0;6'b000011: disphr2 = 4'h0;6'b000100: disphr2 = 4'h0;6'b000101: disphr2 = 4'h0;6'b000110: disphr2 = 4'h0;6'b000111: disphr2 = 4'h0;6'b001000: disphr2 = 4'h0;6'b001001: disphr2 = 4'h0;6'b001010: disphr2 = 4'h1;6'b001011: disphr2 = 4'h1;6'b001100: disphr2 = 4'h1;6'b001101: disphr2 = 4'h1;6'b001110: disphr2 = 4'h1;6'b001111: disphr2 = 4'h1;6'b010000: disphr2 = 4'h1;6'b010001: disphr2 = 4'h1;6'b010010: disphr2 = 4'h1;6'b010011: disphr2 = 4'h1;6'b010100: disphr2 = 4'h2;6'b010101: disphr2 = 4'h2;6'b010110: disphr2 = 4'h2;6'b010111: disphr2 = 4'h2;6'b011000: disphr2 = 4'h2;6'b011001: disphr2 = 4'h2;6'b011010: disphr2 = 4'h2;6'b011011: disphr2 = 4'h2;6'b011100: disphr2 = 4'h2;6'b011101: disphr2 = 4'h2;6'b011110: disphr2 = 4'h3;6'b011111: disphr2 = 4'h3;6'b100000: disphr2 = 4'h3;6'b100001: disphr2 = 4'h3;6'b100010: disphr2 = 4'h3;6'b100011: disphr2 = 4'h3;6'b100100: disphr2 = 4'h3;6'b100101: disphr2 = 4'h3;6'b100110: disphr2 = 4'h3;6'b100111: disphr2 = 4'h3;6'b101000: disphr2 = 4'h4;6'b101001: disphr2 = 4'h4;6'b101010: disphr2 = 4'h4;6'b101011: disphr2 = 4'h4;6'b101100: disphr2 = 4'h4;6'b101101: disphr2 = 4'h4;6'b101110: disphr2 = 4'h4;6'b101111: disphr2 = 4'h4;6'b110000: disphr2 = 4'h4;6'b110001: disphr2 = 4'h4;6'b110010: disphr2 = 4'h5;6'b110011: disphr2 = 4'h5;6'b110100: disphr2 = 4'h5;6'b110101: disphr2 = 4'h5;6'b110110: disphr2 = 4'h5;6'b110111: disphr2 = 4'h5;6'b111000: disphr2 = 4'h5;6'b111001: disphr2 = 4'h5;6'b111010: disphr2 = 4'h5;6'b111011: disphr2 = 4'h5;6'b111100: disphr2 = 4'h6;6'b111101: disphr2 = 4'h6;6'b111110: disphr2 = 4'h6;6'b111111: disphr2 = 4'h6;endcaseend

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/////cycle display switchingif(setcycle&& hrplus)begincase(cycsel)4'h0: cycledisplay <= cycle0;4'h1: cycledisplay <= cycle1;4'h2: cycledisplay <= cycle2;4'h3: cycledisplay <= cycle3;4'h4: cycledisplay <= cycle4;4'h5: cycledisplay <= cycle5;4'h6: cycledisplay <= cycle6;4'h7: cycledisplay <= cycle7;4'h8: cycledisplay <= cycle8;4'h9: cycledisplay <= cycle9;endcase///cycle display casescase (cycledisplay)6'b000000: disp1 = 4'h0;6'b000001: disp1 = 4'h1;6'b000010: disp1 = 4'h2;6'b000011: disp1 = 4'h3;6'b000100: disp1 = 4'h4;6'b000101: disp1 = 4'h5;6'b000110: disp1 = 4'h6;6'b000111: disp1 = 4'h7;6'b001000: disp1 = 4'h8;6'b001001: disp1 = 4'h9;6'b001010: disp1 = 4'h0;6'b001011: disp1 = 4'h1;6'b001100: disp1 = 4'h2;6'b001101: disp1 = 4'h3;6'b001110: disp1 = 4'h4;6'b001111: disp1 = 4'h5;6'b010000: disp1 = 4'h6;6'b010001: disp1 = 4'h7;6'b010010: disp1 = 4'h8;6'b010011: disp1 = 4'h9;6'b010100: disp1 = 4'h0;6'b010101: disp1 = 4'h1;6'b010110: disp1 = 4'h2;6'b010111: disp1 = 4'h3;6'b011000: disp1 = 4'h4;6'b011001: disp1 = 4'h5;6'b011010: disp1 = 4'h6;6'b011011: disp1 = 4'h7;6'b011100: disp1 = 4'h8;6'b011101: disp1 = 4'h9;6'b011110: disp1 = 4'h0;6'b011111: disp1 = 4'h1;6'b100000: disp1 = 4'h2;6'b100001: disp1 = 4'h3;6'b100010: disp1 = 4'h4;6'b100011: disp1 = 4'h5;6'b100100: disp1 = 4'h6;6'b100101: disp1 = 4'h7;6'b100110: disp1 = 4'h8;6'b100111: disp1 = 4'h9;6'b101000: disp1 = 4'h0;6'b101001: disp1 = 4'h1;6'b101010: disp1 = 4'h2;6'b101011: disp1 = 4'h3;6'b101100: disp1 = 4'h4;6'b101101: disp1 = 4'h5;6'b101110: disp1 = 4'h6;6'b101111: disp1 = 4'h7;6'b110000: disp1 = 4'h8;6'b110001: disp1 = 4'h9;6'b110010: disp1 = 4'h0;6'b110011: disp1 = 4'h1;6'b110100: disp1 = 4'h2;6'b110101: disp1 = 4'h3;

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6'b110110: disp1 = 4'h4;6'b110111: disp1 = 4'h5;6'b111000: disp1 = 4'h6;6'b111001: disp1 = 4'h7;6'b111010: disp1 = 4'h8;6'b111011: disp1 = 4'h9;6'b111100: disp1 = 4'h0;6'b111101: disp1 = 4'h1;6'b111110: disp1 = 4'h2;6'b111111: disp1 = 4'h3;endcase

case (cycledisplay)6'b000000: disp2 = 4'h0;6'b000001: disp2 = 4'h0;6'b000010: disp2 = 4'h0;6'b000011: disp2 = 4'h0;6'b000100: disp2 = 4'h0;6'b000101: disp2 = 4'h0;6'b000110: disp2 = 4'h0;6'b000111: disp2 = 4'h0;6'b001000: disp2 = 4'h0;6'b001001: disp2 = 4'h0;6'b001010: disp2 = 4'h1;6'b001011: disp2 = 4'h1;6'b001100: disp2 = 4'h1;6'b001101: disp2 = 4'h1;6'b001110: disp2 = 4'h1;6'b001111: disp2 = 4'h1;6'b010000: disp2 = 4'h1;6'b010001: disp2 = 4'h1;6'b010010: disp2 = 4'h1;6'b010011: disp2 = 4'h1;6'b010100: disp2 = 4'h2;6'b010101: disp2 = 4'h2;6'b010110: disp2 = 4'h2;6'b010111: disp2 = 4'h2;6'b011000: disp2 = 4'h2;6'b011001: disp2 = 4'h2;6'b011010: disp2 = 4'h2;6'b011011: disp2 = 4'h2;6'b011100: disp2 = 4'h2;6'b011101: disp2 = 4'h2;6'b011110: disp2 = 4'h3;6'b011111: disp2 = 4'h3;6'b100000: disp2 = 4'h3;6'b100001: disp2 = 4'h3;6'b100010: disp2 = 4'h3;6'b100011: disp2 = 4'h3;6'b100100: disp2 = 4'h3;6'b100101: disp2 = 4'h3;6'b100110: disp2 = 4'h3;6'b100111: disp2 = 4'h3;6'b101000: disp2 = 4'h4;6'b101001: disp2 = 4'h4;6'b101010: disp2 = 4'h4;6'b101011: disp2 = 4'h4;6'b101100: disp2 = 4'h4;6'b101101: disp2 = 4'h4;6'b101110: disp2 = 4'h4;6'b101111: disp2 = 4'h4;6'b110000: disp2 = 4'h4;6'b110001: disp2 = 4'h4;6'b110010: disp2 = 4'h5;6'b110011: disp2 = 4'h5;6'b110100: disp2 = 4'h5;6'b110101: disp2 = 4'h5;6'b110110: disp2 = 4'h5;6'b110111: disp2 = 4'h5;6'b111000: disp2 = 4'h5;6'b111001: disp2 = 4'h5;

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6'b111010: disp2 = 4'h5;6'b111011: disp2 = 4'h5;6'b111100: disp2 = 4'h6;6'b111101: disp2 = 4'h6;6'b111110: disp2 = 4'h6;6'b111111: disp2 = 4'h6;endcaseend////end on clock assignmentend //output assignmentsassign otrigger0 = trigger0;assign otrigger1 = trigger1;assign otrigger2 = trigger2;assign otrigger3 = trigger3;assign otrigger4 = trigger4;assign otrigger5 = trigger5;assign otrigger6 = trigger6;assign otrigger7 = trigger7;assign otrigger8 = trigger8;assign otrigger9 = trigger9;assign Vref = vrefreg;assign osegoutA = segoutA;assign osegoutB = segoutB;assign osegoutC = segoutC;assign osegoutD = segoutD;endmodule

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