vip1: a 3d integrated circuit for pixel applications in high energy physics jim hoff*, grzegorz...
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VIP1: a 3D Integrated Circuit for VIP1: a 3D Integrated Circuit for Pixel Applications in High Energy Pixel Applications in High Energy PhysicsPhysics
Jim Hoff*, Grzegorz Deptuch, Tom Zimmerman, Ray Yarema Jim Hoff*, Grzegorz Deptuch, Tom Zimmerman, Ray Yarema - Fermilab- Fermilab* [email protected]* [email protected]
Vertical Integration (a.k.a. 3D Integration)– Vertical Integration (a.k.a. 3D Integration)– What is it?What is it?
Several active semiconductor Several active semiconductor layers “independently” designedlayers “independently” designed Not necessarily the same functionNot necessarily the same function Not necessarily the same Not necessarily the same
technologytechnology ThinnedThinned Bonded togetherBonded together Interconnected to one another Interconnected to one another
with deep viaswith deep vias
8.2 µm
7.8 µm
6.0 µm
3D vias
Vertical Integration (a.k.a. 3D Integration)– Vertical Integration (a.k.a. 3D Integration)– What is it?What is it?
Vertical Integration (a.k.a. 3D Integration)– Vertical Integration (a.k.a. 3D Integration)– What is it?What is it?
Opto Electronicsand/ or Voltage Regulation
Digital Layer
Analog Layer
Sensor Layer
Physicist’s Dream
50 um
Power I n
Optical I n Optical Out
Industry’s Interest in Vertical Integration
•Moore’s Law•Reduce R, L, C for higher speed•Reduce chip I/O pads•Provide increased functionality•Reduce interconnect power and crosstalk
HEP’s Interest in Vertical Integration
•Reduced Mass in the Beamline•Selectable detector and readout technologies•Increased functionality per unit area at a given feature size
J. Joly, LETI
VIP1: What is it?VIP1: What is it?
FeaturesFeatures 20 20 m x 20 m x 20 m pixel sizem pixel size Binary (hit/no hit) information with analog hit information Binary (hit/no hit) information with analog hit information
to improve resolutionto improve resolution Double Correlated SamplingDouble Correlated Sampling Both analog and digital time stamping, each individually Both analog and digital time stamping, each individually
capable of resolving 32 time steps per bunch train. capable of resolving 32 time steps per bunch train. Readout between bunch trains Readout between bunch trains Data sparsification with pipelined token passingData sparsification with pipelined token passing A single point-to-point serial output lineA single point-to-point serial output line Design for megapixel array, but layout a 64x64 arrayDesign for megapixel array, but layout a 64x64 array Low power (assuming power pulsing is used)Low power (assuming power pulsing is used) A Test input per pixelA Test input per pixel
The VIP1 is a 64x64 demonstrator version of a 1k x 1k readout chip for ILC pixel vertex applications. It is designed to conform to ILC standards as they are understood today.
VIP1: Overall System ArchitectureVIP1: Overall System Architecture
X=1
T11 5
Y=1
X=2
T2
1 5
10 10
Y=2
Y=3
Y address bus
110
cell1:1
cell2:1
cell1:2
cell2:2
cell1:3
X=1000
Token to rowY=2
Token to row Y=3
Serial Data out(30 bits/ hit)
DigitalData MuxX,Y,Time
StartReadoutToken
X
Y
Time
T1buf T2buf
Note: All the Y address registers can be replaced by one counter thatis incremented by the last column token.
cell1000:1
cell2:3
cell1000:2
cell1000:3
Assume 1000 x 1000 arrayX and Y addresses are 10bits each
Analogoutputs
VIP1: Pixel Cell Block DiagramVIP1: Pixel Cell Block Diagram
I ntegrator
Discriminator
Analog out
Timestampcircuit
Test inject
Read all
R
SQ Pixel
skiplogic
Write data
D FF
Data clk
Readdata
To x, yaddress
T.S.out
Hit latchVth
Analog f ront end Pixel sparsif ication circuitry Time stamp
Conversion to a 3D architectureConversion to a 3D architecture
Inter-tier Inter-tier vias are vias are substantialsubstantial
Logical versus Logical versus physical physical division of division of functionfunction
Layout on one Layout on one tier impacts tier impacts layout on layout on other tiers.other tiers.
The Pixel Cell on Tier 1The Pixel Cell on Tier 1
Sample1
Sample2 Vth
Sample 1
To analog output buses
S. TrigDelay
Digital time stamp bus5
Pad to sensor
Analog T.S.b0 b1 b2 b3 b4
Analog time output bus
Analog ramp bus
Write data
Read data
Test input S.R.I njectpulse
I n
OutS
RQ
Y address
X address
D FF
Pixelskiplogic
Token I n
Token out
Readall
Read dataData clk
Tier 1
Tier 2
Tier 3
Tier 3analog
Tier 2Time Stamp
Tier 1Datasparsification
3Dvias
D FF
X, Y line control
Token passing logic
Test inputcircuit
OR, SR FF
• SR-ff for hit storage for the duration of the pulse train.
•OR to allow universal read
•Conservative, static, edge-triggered DFF in data sparsification.
•Dynamic edge-triggered DFF for test input pulses
•65 transistors
The Pixel Cell on Tier 2The Pixel Cell on Tier 2
Sample1
Sample2 Vth
Sample 1
To analog output buses
S. TrigDelay
Digital time stamp bus5
Pad to sensor
Analog T.S.b0 b1 b2 b3 b4
Analog time output bus
Analog ramp bus
Write data
Read data
Test input S.R.I njectpulse
I n
OutS
RQ
Y address
X address
D FF
Pixelskiplogic
Token I n
Token out
Readall
Read dataData clk
Tier 1
Tier 2
Tier 3
Tier 3analog
Tier 2Time Stamp
Tier 1Datasparsification
3Dvias
b0
b1
b2
b3
b4
Analog T. S.
• 5 bit digital timestamp latched in the pixel from a Gray Code counter on the periphery of Tier 2
•Analog time stamp resolution to be determined, but expecting 5 bits
•Time stamps can be used in alone or in series to create a 10 bit time stamp.
•72 transistors
The Pixel Cell on Tier 3The Pixel Cell on Tier 3
Sample1
Sample2 Vth
Sample 1
To analog output buses
S. TrigDelay
Digital time stamp bus5
Pad to sensor
Analog T.S.b0 b1 b2 b3 b4
Analog time output bus
Analog ramp bus
Write data
Read data
Test input S.R.I njectpulse
I n
OutS
RQ
Y address
X address
D FF
Pixelskiplogic
Token I n
Token out
Readall
Read dataData clk
Tier 1
Tier 2
Tier 3
Tier 3analog
Tier 2Time Stamp
Tier 1Datasparsification
3DviasIntegratorDiscriminator
DCS + Readout
Schmitt Trigger+NOR
CTI
• Integrator
•Double correlated sample plus readout
•Discriminator
•Chip scale programmable threshold input
•Capacitive test input (CTI)
•38 transistors
•2 vias
3D Stacking (of a single pixel) with Vias 3D Stacking (of a single pixel) with Vias (step 1)(step 1)
2000 ohm-cm p-type substrate
Buried oxide (BOX), 400 nm thick
Tier 1 pixel circuit
3D Stacking (of a single pixel) with Vias 3D Stacking (of a single pixel) with Vias (step 2)(step 2)
Bond tier 2 to tier 1
Tier 1
Tier 2
3D Stacking (of a single pixel) with Vias 3D Stacking (of a single pixel) with Vias (step 3)(step 3)
Form 3 vias, 1.5 x 7.3 µm,through Tier 2 to Tier 1
3D Stacking (of a single pixel) with Vias 3D Stacking (of a single pixel) with Vias (step 4)(step 4)
Bond tier 3 to tier 2
Tier 3
Tier 2
3D Stacking (of a single pixel) with Vias 3D Stacking (of a single pixel) with Vias (step 5)(step 5)
Form 2 vias, 1.5 x 7.3 µm,through tier 3 to tier 2
A 64x64 Array with Perimeter LogicA 64x64 Array with Perimeter Logic Perimeter Perimeter
circuitry for the circuitry for the ILC ILC Demonstrator Demonstrator chip occupies a chip occupies a small amount small amount of space.of space.
Area for the Area for the perimeter logic perimeter logic could be could be reduced in reduced in future designs.future designs.
64 x 64 array with perimeter logic
Blow up ofcorner ofarray
StatusStatus The design was submitted in October The design was submitted in October
of last year. It was due in August of of last year. It was due in August of this year.this year.
We expect delivery any day and We expect delivery any day and hope to present experimental results hope to present experimental results in the conference record or in a TNS in the conference record or in a TNS paper.paper.
This design was fabricated as part of This design was fabricated as part of a multi-project wafer run supported a multi-project wafer run supported as a DARPA R&D effort. This was the as a DARPA R&D effort. This was the second such run.second such run.
A third MPW run is planned for next A third MPW run is planned for next year.year.