VLSI Design Spring03 UCSCBy Prof Scott Wakefield

Final ProjectBy Shaoming Ding ding@soe.ucsc.eduJun Hu hujun@soe.ucsc.edu

CE222 VLSI Design CE222 VLSI Design Spring03 UCSCSpring03 UCSC

Prof. Scott WakefieldProf. Scott Wakefield

Final ProjectFinal Project

High speed 3High speed 3--tap FIRtap FIR

By Shaomin Ding By Shaomin Ding ding@soe.ucsc.eduding@soe.ucsc.edu

Jun Jun HuHuhujun@soe.ucsc.eduhujun@soe.ucsc.edu

Our goal

The goal of the project is to design a high speed 3-tap Finite Impulse Response (FIR) filter using explicit arithmetic units instead of high level behavioral operations to speed-up the computation. The arithmetic units include a 48-bit adder and a 24-bit multiplier.

The structure of the FIR Usual Implementation

Project Implementation

Multiplier

Standard multiplication

210 )011110(*]0:5[30*]0:5[ AA

Multiplier Booth’s algorithm (Radix-2)

Multiplier If Booth's recoded is +1 , then

set else if Booth's recoded is -1, then

else

0 11

-101

+110

000

Recoded aiai-1ai

BPP BPP

0PP

23 22 21 20 … 4 3 2 1 0 (0)

The implementation of multiplier in the project Radix-4 Booth

23 22 21 19 … 9 8 7 5 4 3 1 0 (0)

ai+1 ai ai-1 Operation

0 0 0 Add 0 x B

0 0 1 Add +1 x B

0 1 0 Add +1 x B

0 1 1 Add +2 x B

1 0 0 Add -2 x B

1 0 1 Add -1 x B

1 1 0 Add -1 x B

1 1 1 Add 0 x B

The implementation of multiplier in the projectThe Structure

Carry Save Adder (CSA)

A 10111001

B 00101010

Carry In 00111001

Sum 10101010 //Sum and Carry comes out from CSA

Carry Out 00111001

Result 100011100 //This uses propagate adder

Basic idea

The basic idea is that three numbers can be reduced to 2, in a 3:2 compressor, by doing the addition while keeping the carries and the sum separate.

Carry Save Adder (CSA) Wallace carry save adder tree

Full 3:2 compressor on k-bit-word.

48-bit Carry Look-ahead Adder

iii baP

iii baG

48-bit Carry Look-ahead Adder

ii CS

iiii CPGC 1

)( 1111 iiiiii CPGPGC

)( 212111 iiiiiiiii CPGPPGPGC

XOR XOR ia ib

Final Results

Summary The advantage of our structure Concurrent computation of each tap instead of the

sequential one. Multiplier concurrent computation of partial products

and summation using Wallace Tree via Carry-save Adder.

Carry Look-ahead Adder in the final addition.

Conclusion

Using arithmetic units (a 48-bit adder and a 24-bit multiplier.) instead of high level behavioral operations can highly speed-up the computation