vlsi lab manual anna university pdf

7/24/2019 vlsi lab manual anna university pdf

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SVS COLLEGE OF ENGINEERING

COIMBATORE-642 109

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

OBSERVATION NOTE BOOK

EC6612 VLSI DESIGN LABORATORY

VI SEM ECE B SEC

Name..

Roll No ..

Year/Sem ..

Branch ..

Subject..


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SVS COLLEGE OF ENGINEERING

COIMBATORE-642 109

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

EC6612 VLSI DESIGN LABORATORY

VI SEM ECE B SEC

Prepared by,

Mr. K. Manoharan,

Assistant Professor,

ECE Department.

SVS College of Engineering.

Academic Year: 2015-2016


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INDEX

EX.NO NAME OF THE EXPERIMENTS PAGE NO

1.DESIGN ENTRY AND SIMULATION OF

COMBINATIONAL LOGIC CIRCUITS7

2.DESIGN ENTRY AND SIMULATION OF SEQUENTIAL

CIRCUITS13

3.DESIGN ENTRY AND SIMULATION OF STATE

MACHINE USING STATECAD17

4.SYNTHESIS OF COMBINATIONAL AND SEQUENTIAL

CIRCUIT23

5.PLACE & ROOT AND POST PLACE & ROOT

SIMULATION27

6. HARDWARE FUSING AND TESTING33

7. DIFFERENTIAL AMPLIFIER41

8.CMOS INVERTER LAYOUT AND PARASITIC

EXTRACTION45

9. DIFFERENTIAL AMPLIFIER LAYOUT GENERATION53

10. STANDARD CELL BASED DESIGN 57

11.

PLACEMENT AND ROUTING, POWER AND CLOCK

ROUTING AND POST PLACEMENT AND ROUTING

SIMULATION

61

12. STATIC TIMING ANALYSIS67


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OBSERVATION NOTE BOOK

CONTENTS

S. No Date ExperimentsPage

NoMarks

Signature

of Staff


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Exp. No. : 1

Date:

DESIGN ENTRY AND SIMULATION OF COMBINATIONAL

LOGIC CIRCUITS

AIM:To write a Verilog code for the basic logic gates, 8 bit adder and 4bit multiplier and

simulate it using Xilinx project navigator.

APPARATUS REQUIRED:

S.No Name of the equipment/ software Quantity

1. PC with Windows 1

2. Xilinx Project navigator 1

PROCEDURE:

1. Start the Xilinx ISE by using StartProgram filesXilinx ISEprojectnavigator

2. Click FileNew Project

3. Enter the Project Name and select the location then click next

4. Select the Device and other category and click next twice and finish.

5. Click on the symbol of FPGA device and then right clickclick on new source.

6. Select the Verilog Module and give the file name click next and define ports

click next and finish.

7. Writing the Verilog Code in Verilog Editor.

8. Run the Check syntax Process window synthesize double click check

syntax. If any errors found then remove the errors with proper syntax & coding.

9. Click on the symbol of FPGA device and then right click click on new source.

10.Select the Test Bench Waveform and give the file nameselect entity click next

and finish.

11.Select the desired parameters for simulating your design. In this case combinational

circuit and simulation time click finish.

12.Assign all input signal using just click on graph and save file.

13.From the source process window. Click Behavioral simulation from drop-down

menu

14.Select the test bench file (.tbw) and click process buttondouble click the

Simulation Behavioral Model

15.Verify your design in wave window by seeing behavior of output signal with respectto input signal.

CODING:

BASIC LOGIC GATES:module gates(a,b,c,d,e,f,g,h,i);

input a,b;

output c,d,e,f,g,h,i;

and(c,a,b);

or(d,a,b);

nor(e,a,b);nand(f,a,b);

xor(g a b);


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4X 4 MULTIPLIER

LOGIC DIAGRAM


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not(i,a);

endmodule

8 BIT ADDERmodule adder(s,cout,a,b,cin);

output[7:0]s;output cout;

input[7:0]a,b;

input cin;

wire c1,c2,c3,c4,c5,c6,c7;

fulladd fa0(s[0],c1,a[0],b[0],cin);

fulladd fa1(s[1],c2,a[1],b[1],c1);





fulladd fa6(s[6],c7,a[6],b[6],c6);fulladd fa7(s[7],cout,a[7],b[7],c7);

endmodule

module fulladd(s,cout,a,b,cin);

output s,cout;

input a,b,cin;

xor (s,a,b,cin);

assign cout = ((a & b )|(b& cin)|( a & cin)) ;

endmodule

4 BIT MULTIPLIERmodule multi(m,a,b);

input [3:0]a;

input [3:0]b;

output [7:0]m;

wire [15:0]p;

wire [12:1]s;

wire [12:1]c;

and(p[0],a[0],b[0]);

and(p[1],a[1],b[0]);

and(p[2],a[0],b[1]);and(p[3],a[2],b[0]);

and(p[4],a[1],b[1]);

and(p[5],a[0],b[2]);

and(p[6],a[3],b[0]);

and(p[7],a[2],b[1]);

and(p[8],a[1],b[2]);

and(p[9],a[0],b[3]);

and(p[10],a[3],b[1]);

and(p[11],a[2],b[2]);

and(p[12],a[1],b[3]);

and(p[13],a[3],b[2]);and(p[14],a[2],b[3]);

and(p[15] a[3] b[3]);


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OUTPUT

LOGIC GATES

8 BIT ADDER


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half ha2(s[2],c[2],p[4],p[3]);

half ha3(s[3],c[3],p[7],p[6]);

full fa4(s[4],c[4],p[11],p[10],c[3]);

full fa5(s[5],c[5],p[14],p[13],c[4]);

full fa6(s[6],c[6],p[5],s[2],c[1]);full fa7(s[7],c[7],p[8],s[3],c[2]);

full fa8(s[8],c[8],p[12],s[4],c[7]);

full fa9(s[9],c[9],p[9],s[7],c[6]);

half ha10(s[10],c[10],s[8],c[9]);

full fa11(s[11],c[11],s[5],c[8],c[10]);

full fa12(s[12],c[12],p[15],s[5],c[11]);

buf(m[0],p[0]);

buf(m[1],s[1]);

buf(m[2],s[6]);

buf(m[3],s[9]);

buf(m[4],s[10]);buf(m[5],s[11]);

buf(m[6],s[12]);

buf(m[7],c[12]);

endmodule

module half(s,co,x,y);

input x,y;

output s,co;

xor (s,x,y);

and (co,x,y);

endmodule

module full(s,co,x,y,ci);

input x,y,ci;

output s,co;

wire s1,d1,d2;

half ha_1(s1,d1,x,y);

half ha_2(s,d2,s1,ci);

or or_gate(co,d2,d1);

endmodule

RESULT:Thus the Verilog code for the basic logic gates, 8 bit adder and 4bit multiplier are simulated

using Xilinx project navigator


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Exp. No. : 2

Date:

DESIGN ENTRY AND SIMULATION OF SEQUENTIAL

CIRCUITS

AIM:To write a Verilog code for counter and state machine and simulate it using Xilinx project

navigator.

APPARATUS REQUIRED:




PROCEDURE:

1. Start the Xilinx ISE by using StartProgram filesXilinx ISEproject

navigator

2. Click FileNew Project



5. Click on the symbol of FPGA device and then right clickclick on new source.

6. Select the Verilog Module and give the file name click next and define ports

click next and finish.

7. Writing the Verilog Code in Verilog Editor.

8. Run the Check syntax Process window synthesize double click check


9. Click on the symbol of FPGA device and then right click click on new source.

10.Select the Test Bench Waveform and give the file nameselect entity click next

and finish.

11.Select the desired parameters for simulating your design.

12.Assign all input signal using just click on graph and save file.

13.From the source process window. Click Behavioral simulation from drop-down

menu

14.Select the test bench file (.tbw) and click process buttondouble click the

Simulation Behavioral Model

15.Verify your design in wave window by seeing behavior of output signal with respectto input signal.

CODING:

COUNTERmodule counter (clk, clr, q);

input clk, clr;

output [3:0] q;

reg [3:0] tmp;

always @(posedge clk or posedge clr)

begin


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COUNTER OUTPUT WAVEFORM

TRAFFIC LIGHT CONTROLLER

Three lights only (RED, GREEN, YELLOW)

The lights glow cyclically at a fixed time.

The circuit will be driven by a clock of appropriate frequency


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if (clr)

tmp


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STATE DIAGRAM


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SVS COLLEGE OF ENGINEERING / ECE /EC 6612VLSI DESIGN LAB - K. Manoharan P a g e | 17

Exp. No. : 3

Date:

DESIGN ENTRY AND SIMULATION OF STATE MACHINE

USING STATECAD

AIM:

To design a sequence detector state machine to detect the sequence 1111 and simulate itusing stateCAD in Xilinx project navigator.

APPARATUS REQUIRED:




PROCEDURE:

1.

Start the Xilinx ISE by using Start

Program files

Xilinx ISE

Accessories

StateCAD2. Click Draw State Machine

3. Select Geometric, enter no of states and click next

4. Select synchronous and click next5. Tick loop back and next and click finish.

6. Edit each state name and input, output values.

7. Save the file click File Save

8. OptionsconfigurationsSelect Verilog click ok9. Click Generate HDL open the file in the path and take a copy.

10.Click OptimizeNext

11.Select FPGA

Next12.Select SpeedNext

13.Select Guarantee coverageNext

14.Select enable buffering and tick Optimize port IO and retain unassigned outputs.

15.Select VerilogNext16.Select Xilinx XSTNext

17.Click Generate HDL.

18.Now compare the verilog code of before and after optimization.19.Simulate the design by click state bench

20.Double click the inputs to change the logic value.

21.Click cycle to simulate the design.


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OUTPUT


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CODING

module mano(CLK,inx,RESET,y);

input CLK;

input inx,RESET;

output y;reg y,next_y;

reg S1,next_S1,S2,next_S2,S3,next_S3,S4,next_S4,SO,next_SO;

always @(posedge CLK)

begin

if ( RESET ) S1 = 0;

else S1 = next_S1;end

always @(posedge CLK)begin


else S2 = next_S2;end



else S3 = next_S3;

end


begin

if ( RESET ) S4 = 0;else S4 = next_S4;

end


begin

if ( RESET ) SO = 1;else SO = next_SO;

end


if ( RESET ) y = 0;

else y = next_y;end

always @ (inx or RESET or S1 or S2 or S3 or S4 or SO)

begin


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if ( ~RESET & inx & SO ) next_S1=1;

else next_S1=0;

if ( ~RESET & inx & S1 ) next_S2=1;

else next_S2=0;

if ( ~RESET & inx & S2 ) next_S3=1;else next_S3=0;

if ( ~RESET & inx & S3 | ~RESET & inx & S4 ) next_S4=1;else next_S4=0;

if ( ~inx & S1 | ~inx & S2 | ~inx & S3 | ~inx & S4 | ~inx & SO | RESET )

next_SO=1;else next_SO=0;

if ( ~RESET & inx & S3 | ~RESET & inx & S4 ) next_y=1;

else next_y=0;

endendmodule

RESULT:Thus the sequence detector state machine to detect the sequence 1111 is simulated using

stateCAD in Xilinx project navigator.


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ADDER RTL SCHEMATIC DIAGRAM

ADDER TECHNOLOGY SCHEMATIC DIAGRAM


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Exp. No. : 4

Date:

SYNTHESIS OF COMBINATIONAL AND SEQUENTIAL

CIRCUIT

AIM:To study and analyze about synthesis option available in Xilinx project navigator.

APPARATUS REQUIRED:




PROCEDURE:

1. Start the Xilinx ISE by using Start Program filesXilinx ISEproject navigator2. Click FileNew Project


4. Select the Device and other category and click next twice and finish.5. Click on the symbol of FPGA device and then right clickclick on new source.

6. Select the Verilog Module and give the file nameclick next and define portsclick next and finish.

7. Writing the Verilog Code in Verilog Editor.8. Run the Check syntax Process window synthesize double click check

syntax. If any errors found then remove the errors with proper syntax & coding.9. Synthesis your design, from the source window select, Synthesis from the window Now

double click the10.After the HDL synthesis phase of the synthesis process, you can display a schematic

representation of your synthesized source file. This schematic shows a representation of thepre-optimized design in terms of generic symbols, such as adders, multipliers, counters, ANDgates, and OR gatesdouble click View RTL Schematic

11.Double click the schematic to internal view12.Double click outside the schematic to move one-level back

13.This schematic shows a representation of the design in terms of logic elements optimized tothe target device. For example, in terms of LUTs(Look Up Table), carry logic, I/O buffers,and other technology-specific componentsDouble click View Technology Schematic

14.Double click the schematic to inner view15.Double click the LUT to inner view. This is Gate Level view of LUT, if you want see Truth

Table and K-Map for your design just click the respective tabs.16.Click Generate post synthesis simulation model and view its report.


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CODING:

8 BIT ADDER

module adder(s,cout,a,b,cin);output[7:0]s;

output cout;

input[7:0]a,b;

input cin;wire c1,c2,c3,c4,c5,c6,c7;

fulladd fa0(s[0],c1,a[0],b[0],cin);

fulladd fa1(s[1],c2,a[1],b[1],c1);fulladd fa2(s[2],c3,a[2],b[2],c2);




fulladd fa7(s[7],cout,a[7],b[7],c7);

endmodule


output s,cout;input a,b,cin;

xor (s,a,b,cin);

assign cout = ((a & b )|(b& cin)|( a & cin)) ;endmodule

COUNTER

module counter (clk, clr, q);input clk, clr;

output [3:0] q;

reg [3:0] tmp;

always @(posedge clk or posedge clr)begin

if (clr)

tmp


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DESIGN SUMMARY


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Exp. No. : 5

Date:

PLACE & ROOT AND POST PLACE & ROOTSIMULATION

AIM:To study about Place and Root and Post Place and Root using Implementation option

available in Xilinx project navigator.

APPARATUS REQUIRED:




THEORY:

Back annotation is the translation of a routed or fitted design to a timing simulation netlist. To define the behavior of the FPGA, a hardware description language (HDL) or a schematic

design methods are used. Common HDLs are VHDL and Verilog. Then, using an electronic

design automation (EDA) tool, a technology-mapped net list is generated. The net list can then be fitted to the actual FPGA architecture using a process called place-

and-route, usually performed by the FPGA vendors proprietary place-and-route software. The user will validate the map, place and route results via timing analysis, simulation, and

other verification methodologies. Once the design and validation process is complete, the

binary file generated is used to (re)configure the FPGA. In an attempt to reduce the complexity of designing in HDLs, which have been compared to

the equivalent of assembly In a typical design flow, an FPGA application developer will simulate the design at multiple

stages throughout the design process.

Initially the RTL description in VHDL or Verilog is simulated by creating test benches tosimulate the system and observe results.

Then, after the synthesis engine has mapped the design to a net list, the net list is translated toa gate level description where simulation is repeated to confirm the synthesis proceededwithout errors.

Finally the design is laid out in the FPGA at which point propagation delays can be added andthe simulation run again with these values back-annotated onto the net list.

Place & Route, the process of optimization of logic cells for effective utilization of FPGAarea and the speed of operation, is used to modify and infer the following:

1) Re-assignment of Pins2) Re-location of Slices3) Run time minimization


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PROCEDURE:




5.

Click on the symbol of FPGA device and then right click

click on new source.6. Select the Verilog Module and give the file nameclick next and define portsclick next and finish.

7. Writing the Verilog Code in Verilog Editor.8. Run the Check syntax Process window synthesize double click check


9. Synthesis your design, from the source window select, synthesis/implementation from

the window Now double click the Synthesis -XST10.After Synthesis you assign the Pin Value for your design so,double click the

Assign Package Pins

11.Enter the Pin value for your input and output signals. if you want see your Pinassignment in FPGA zoom in Architecture View or Package View

12.You see the Pins in FPGA. Save file as XST Default click ok and close the window

13.Design Implementation begins with the mapping or fitting of a logical design file to aspecific device and is complete when the physical design is successfully routed and a

bit stream is generated. Double Click Implementation Design.

14.After finishing the Implementation, you can view the Implementation report.15.After implementation you see Design Summary, you get the all details about your

design. If you want edit the place and route double click View/Edit placed design

16.You see where your IOs are placed in FPGA. And zoom to view how Pins are placed

in FPGA. You can see where your pins are placed17.Just double click View/Edit Routed Design to view interconnection wires and blocks

18.Click the pin to see where its placed in FPGA. And Zoom particular areato see Place

and Routing.

19.If you want to change the place of the design, click and trace to another slice. See,You changed place and route of the design

20.Double click Back annotated Pin Location. Once back annotation is completed,

constraint file is generated.

CODING:


output[7:0]s;

output cout;

input[7:0]a,b;input cin;


fulladd fa0(s[0],c1,a[0],b[0],cin);fulladd fa1(s[1],c2,a[1],b[1],c1);





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fulladd fa7(s[7],cout,a[7],b[7],c7);

endmodule


output s,cout;

input a,b,cin;xor (s,a,b,cin);

assign cout = ((a & b )|(b& cin)|( a & cin)) ;

endmodule

COUNTER

module counter (clk, clr, q);

input clk, clr;output [3:0] q;

reg [3:0] tmp;

always @(posedge clk or posedge clr)begin

if (clr)

tmp


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Exp. No. : 6

Date:

HARDWARE FUSING AND TESTING

AIM:To study about Hardware fusing and testing of given circuit using Xilinx project navigator.

APPARATUS REQUIRED:




PROCEDURE:



4. Select the Device and other category and click next twice and finish.5. Click on the symbol of FPGA device and then right clickclick on new source.

6. Select the Verilog Module and give the file nameclick next and define portsclick next and finish.

7. Writing the Verilog Code in Verilog Editor.8. Run the Check syntax Process window Synthesize double click check


9.

Synthesis your design, from the source window select, synthesis/implementation fromthe window Now double click the Synthesis -XST.

10.After Synthesis, Click on the symbol of FPGA device and Right click and selectNew

Source, Select Implementation Constraints File and type file name and click next.

11.Type the Net list and click save.12.Implement the design by double clicking Implement design in the process window.

13.Then double click Generate Programming File, Double click Configure Target

Device and click OK.14.Double click Create PROM File in the ISE iMPACT window, Select Storage Target

Device as Xilinx Flash PROM and click forward.

15.Add storage Device as xcf01s [2 M] and click forward, Type Output File Name and

Location and click OK.16.Select the corresponding .bit file and click Open, Click No to Add Another Device

and Click OK.

17.Double click Generate File.18.Double click Boundary Scan and Right click on the window and select Initialize

Chain, Now Select the corresponding .mcs file and click open.

19.Click OK in the Device Programming Properties window, Download the Program onto the kit by Right clicking on the device icon and select program.

20.Verify the output in the target device.


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CODING:


output[7:0]s;

output cout;

input[7:0]a,b;input cin;


fulladd fa0(s[0],c1,a[0],b[0],cin);fulladd fa1(s[1],c2,a[1],b[1],c1);





fulladd fa7(s[7],cout,a[7],b[7],c7);endmodule

module fulladd(s,cout,a,b,cin);output s,cout;

input a,b,cin;

xor (s,a,b,cin);assign cout = ((a & b )|(b& cin)|( a & cin)) ;

endmodule

4 BIT MULTIPLIERmodule multi(m,a,b);

input [3:0]a;

input [3:0]b;output [7:0]m;

wire [15:0]p;

wire [12:1]s;wire [12:1]c;

and(p[0],a[0],b[0]);

and(p[1],a[1],b[0]);and(p[2],a[0],b[1]);

and(p[3],a[2],b[0]);

and(p[4],a[1],b[1]);

and(p[5],a[0],b[2]);and(p[6],a[3],b[0]);

and(p[7],a[2],b[1]);

and(p[8],a[1],b[2]);and(p[9],a[0],b[3]);

and(p[10],a[3],b[1]);

and(p[11],a[2],b[2]);

and(p[12],a[1],b[3]);and(p[13],a[3],b[2]);


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and(p[14],a[2],b[3]);

and(p[15],a[3],b[3]);

half ha1(s[1],c[1],p[1],p[2]);half ha2(s[2],c[2],p[4],p[3]);

half ha3(s[3],c[3],p[7],p[6]);

full fa4(s[4],c[4],p[11],p[10],c[3]);

full fa5(s[5],c[5],p[14],p[13],c[4]);full fa6(s[6],c[6],p[5],s[2],c[1]);

full fa7(s[7],c[7],p[8],s[3],c[2]);

full fa8(s[8],c[8],p[12],s[4],c[7]);full fa9(s[9],c[9],p[9],s[7],c[6]);

half ha10(s[10],c[10],s[8],c[9]);

full fa11(s[11],c[11],s[5],c[8],c[10]);

full fa12(s[12],c[12],p[15],s[5],c[11]);buf(m[0],p[0]);

buf(m[1],s[1]);

buf(m[2],s[6]);buf(m[3],s[9]);

buf(m[4],s[10]);

buf(m[5],s[11]);buf(m[6],s[12]);

buf(m[7],c[12]);

endmodule

module half(s,co,x,y);

input x,y;

output s,co;xor (s,x,y);

and (co,x,y);

endmodule

module full(s,co,x,y,ci);

input x,y,ci;

output s,co;wire s1,d1,d2;

half ha_1(s1,d1,x,y);

half ha_2(s,d2,s1,ci);or or_gate(co,d2,d1);

endmodule

COUNTERmodule counter (clk, clr, q);

input clk, clr;output [3:0] q;

reg [3:0] tmp;

always @(posedge clk or posedge clr)

beginif (clr)


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tmp


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DIFFERENTIAL AMPLIFIER


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Exp. No. : 7

Date:

DIFFERENTIAL AMPLIFIER

AIM:To design and simulate the simple five transistor differential amplifier circuit and measure

the parameters using Tanner EDA tools.

APPARATUS REQUIRED:



2. Tanner EDA Tools 1

PROCEDURE:

1. Open a schematic editor by using StartProgram filesTanner EDATanner

EDA ToolsS-Edit.

2. Create new design by Click file NewNew Design.

3. Enter the design name and select the path to save the design.

4. Create new cell viewCellnew viewSelect the parameters and give ok.

5. Click add available in library window and select the library file.

6. Select devices in the library drag required PMOS and NMOS components from the

symbol browser and design five transistor differential amplifier circuit.

7. Common mode Inputs are applied to the circuit.

8. To open T spice window click ToolsT- Spice.

9. Insert technology file and required comments using insert comment option in T-

Spice.

10.Run the simulation by clicking simulation Run simulation.

11.Output waveform is viewed in the waveform viewer (W-edit) now verify the result.

12.Input and output voltages are measured and tabulated for common mode.


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13.Step 7 to step 12 is repeated for the differential mode.

14.Now calculate the gain, ICMR, and CMRR.

RESULT:Thus the simple five transistor differential amplifier was simulated and gain, ICMR, and

CMRR are calculated using Tanner EDA tools.


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SCHEMATIC DIAGRAM

OUTPUT WAVEFORM


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Exp. No. : 8

Date:

CMOS INVERTER LAYOUT AND PARASITIC EXTRACTION

AIM:To design a CMOS layout and extract the parasitic capacitance and resistance using Cadence

EDA tools.

APPARATUS REQUIRED:



2. CadenceEDA Tools

1

PROCEDURE:

STEP 1: Create a library and build a schematic of an Inverter

Execute Tools Library Manager in the CIW (Command Interpreter Window) to open

Library Manager.

In the Library Manager, execute File NewLibrary. The new library form appears.

In the New Library form, type MyDesignLib in the Name section.

In the field of Directory section, verify that the path to the library is set to ~/

Database/cadence_analog_labs_615 and click OK. A Technology File for New library form appears, select option Attach to an existing

technology libraryand click OK.

A Attach library to Technology Library form appears, select option gpdk180 from

the cyclic field and click OK

After creating a new library we can verify it from the Library Manager

If we right click on the MyDesignLib and select properties, we can find that gpdk180

library is attached as techLib to MyDesignLib.

STEP 2: Adding Components to schematic

In the Inverterschematic window, click the Instance fixed menu icon to display

the Add Instance form.

Click on the Browse button. This opens up a Library browser from which we can select

components and the symbol view.


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LAY OUT DIAGRAM

PARASITIC EXTRACTION


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Move the cursor to the Schematic window and left click to place a component.

Add the pins and wires to the Schematic as per the logic diagram and save the design.

STEP 3: Set up for transient analysis and run simulations on the Inverter Test design

In the Simulation window (ADE), execute Analysis

Choose Analysis or click the

o ChooseAnalysisicon.

In the Analysis section select Tran.

o Set the stop time as 200n.

o Click at the moderate and enabledbuttons at the bottom, and then click Apply.

In the Analysis section, select dc to set up for DC Analysis

o In the DC Analysis section, turn on Save DC Operating Point.

o Turn on the Component Parameter.

o Click the Select Component, Select input signal vpulse source in the test

schematic window.

o Select DC Voltage in the Select Component Parameter window and click OK .

In the analysis form, enter startandstop voltages as 0to 1.8 respectively.

Selecting Signals for Plotting

o Execute OutputsTo be plottedSelect on Schematicin the simulation

window.

o Follow the prompt at the bottom of the schematic window, Click on output net

Vout, input net Vin of the Inverter _Test. Press Esc with the cursor in the

schematic after selecting it

Run the Simulation

o When simulation finishes, the Transient, DC plots automatically will be popped

up along with log file.

o Click on the Split Current Strip icon to separate the wave plots.

STEP 4: Creating Layout View of Inverter

From the Inverter schematic window menu execute LaunchLayout XL. A Startup

Option form appears.

Select Create Newoption and click OK.

A New File form appears, check the Library (MyDesignLib), Cell name (Inverter)

and View name (layout).

Click OKfrom the New File Window. LSW (Layer Select Window) and a blank

layout window appear along with schematic window.


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EXTRACTED RESISTANCE AND CAPACITANCE


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STEP 5: Adding Components to Layout

Execute Connectivity Generate All from Source or click the icon in the Layout

Editor window, Generate Layout form appears. Click OK which imports the schematic

components in to the Layout window automatically. Re arrange the components with in PRBoundary.

Stretch the PRBoundary to our requirement by executing Editstretch. PressEsc after

stretching. We can also use this feature to stretch Wire and routing elements.

To move the components, execute EditMove or click the Move icon and then click on

the component which is to be moved. PressEsc after moving.

To know the distance between different components, or to measure the area consumed by

the design, execute ToolsCreate Ruler. PressEsc after measurements.

STEP 6: Make the interconnection and Creating Contacts/Vias. Finally save the design.

STEP 7: Physical Verification

i) Running a DRC

Select Assura Run DRC from layout window. The DRC form appears. The Library

and Cell name are taken from the current design window, but rule file may be missing.

Select the Technology as gpdk180. This automatically loads the rule file.

Click OK

to start DRC. When DRC finishes, a dialog box appears to view DRC results. Click Yes to view the

results of this run.

If there any DRC error exists in the design, View Layer Window (VLW) and ErrorLayer

Window (ELW) appears. Also the errors highlight in the design itself.

Correct all the DRC errors and Re run the DRC.

If there are no errors in the layout then a dialog box appears with No DRC errors found

written in it, click on close to terminate the DRC run.

ii) Running LVS (Compare the schematic net list and the layout net list)

Select Assura Run LVS from the layout window. The Run Assura LVS form

appears. It will automatically load both the schematic and layout view of the cell.

Click OK to run LVS.

Once the LVS is completed, click yesin the window to see the results of this run.

If the schematic and layout do not matches, LVS Debug window appears.


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In the LVS Debug window, find the details of mismatches and correct all those

mismatches and Rerun the LVS till theschematic is matched with layout.

If the schematic and layout matches completely, close the window to terminate the LVS

run.

iii) Running Assura RCX Extract the RC values from the layout and perform analog circuit simulation on the

designs extracted with RCX. Before using RCX to extract parasitic devices for

simulation, the layout should match with schematic completely to ensure that all parasites

will be backannoted to the correct schematic nets.

From the layout window execute AssuraRun RCX.

Change the following in the Assura parasitic extraction run form. Select Output type

under Setup tab as Extracted View.

In the Extraction tab of the form, choose Extraction type, Cap Coupling Mode and

specify the Reference node for extraction.

In the Filtering tab of the form, Enter Power Nets as Vdd, Vss Enter Ground Nets as Gnd

Click OK in the Assura parasitic extraction form when done. The RCX progress form

appears, in the progress form click Watch log fileto see the output log file.

When RCX completes, a dialog box appears which informs that Assura RCX run

Completed successfully. Click on close to terminate the RCX run.

Double click on av_extracted option under View field. The av_extraced view of design

will pop up.

Press shift-f to view values of the extracted resistance and capacitance in the av_extracted

view.

RESULT:Thus the CMOS layout was drawn and the parasitic capacitance and resistance are extracted

using CadenceEDA tools.


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CIRCUIT DIAGRAM

Sample: nmos nmos1(d,s,g);


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Exp. No. : 9

Date:

LAYOUT GENERATION

AIM:To design layout diagram for five transistor differential amplifier and extract the parasitic

capacitance of the circuit diagram using Microwind tools.

APPARATUS REQUIRED:



2. Microwind 1

PROCEDURE:

1. Open microwind by double clicking microwind2.

2. Create new design by Click on FileNew.

3. Select model file by Click on FileSelect Foundry and select the model file.

4. Create new text file and type the five transistor differential amplifier net list and save

as verilog file.

5. Click on CompileCompile Verilog File. Select the verilog text file and click on

Generate.6. To Run Simulation Click SimulateStart Simulation.

7. View the output waveforms.

8. To extract the parasitic capacitance of the circuit diagram click simulate

Simulation parameters select Mos model and click extract.

CODING

module example( Vbias,Vin1,Vin2,Out);

input Vbias,Vin1,Vin2;

output Out;

pmos pmos1(n1,vdd,n1);

pmos pmos2(Out,vdd,n1);

nmos nmos1(n1,n2,Vin1);

nmos nmos2(Out,n2,Vin2);


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LAYOUT DIAGRAM


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nmos nmos3(n2,vss,Vbias);

endmodule

RESULT:Thus the layout diagram for five transistor differential amplifier was designed and the

parasitic capacitances of the circuit diagram were extracted using Microwind tools.


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Exp. No. : 10

Date:

STANDARD CELL BASED DESIGN

AIM:To design and simulate the traffic light controller using Standard cells using Tanner EDA

tools.

APPARATUS REQUIRED:




PROCEDURE:

S- Edit


EDA ToolsS-Edit.






symbol browser and design the D flip flop, NAND gate and NOR gate.

7. Create the symbol for D flip flop, NAND gate and NOR gate.

8. Using D flip flop, NAND gate and NOR gate design the traffic light controller.

9. Create traffic light controller core and Pad the required input and outputs.

10.Simulate the design by opening T spice window click ToolsT- Spice.

11.Insert technology file and required comments using insert comment option in T-

Spice.


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14.Export the schematic as in TPR format.

L Edit1. Launch L-Edit. Use FileNew to create your design file (layout file).

2. Choose ToolsSPRSetup. In the SPR Setup dialog specify the names of the standard

cell library file and the net list file.

3. Choose ToolsSPRPlace and Route. Select the appropriate option singly or in any

combination. Depending on your standard cell design, uncheck or check the Global input

signal routing option.

4. Click the Run button. Depending on your selected options, SPR will generate up to three

new cells: a core cell, a pad frame cell, and/or a chip cell

5. Verify the design using L-Edit DRC.

6. Extract the net list and simulate the design using T-spice and identify the critical paths,

average power consumption.

7. Save the design in GDSII format and send it to your vendor for fabrication.

RESULT:

Thus the traffic light controller using Standard cells is designed and simulated, using TannerEDA tools.


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Exp. No. : 11

Date:

PLACEMENT AND ROUTING, POWER AND CLOCK

ROUTING, AND POST PLACEMENT AND ROUTING

SIMULATION

AIM:To change the placement and routing, power and clock routing, and post placement and

routing parameters and simulate the design using Tanner EDA tools.

APPARATUS REQUIRED:




PROCEDURE:

S- EDIT


EDA ToolsS-Edit.








8. Using D flip flop, NAND gate and NOR gate design the given circuit.

9. Create core and Pad the required input and outputs.



Spice.


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L EDIT

1. Launch L-Edit. Use FileNew to create your design file (layout file).










PLACEMENT AND ROUTING




3. Choose ToolsSPRSetup, click core setup change the layers parameter and design

rule parameters.

4. Choose ToolsSPRSetup, click pad route setup change the layers parameter and

design rule parameters.


combination.




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POWER AND CLOCK ROUTING




3. Choose ToolsSPRSetup, click core setup change the power parameter.


combination.





POST PLACEMENT AND ROUTING

1. After simulation change the following parameters and re simulate the design.

2. Choose ToolsSPRSetup, click core setup change the layers parameter and design

rule parameters.

3. Choose ToolsSPRSetup, click pad route setup change the layers parameter and

design rule parameters.


RESULT:

Thus the placement and routing, power and clock routing, and post placement and routing

parameters are changed and simulate using Tanner EDA tools.


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Exp. No. : 12

Date:

STATIC TIMING ANALYSIS

AIM:To design the given circuit and perform static timing analysis using Tanner EDA tools.

APPARATUS REQUIRED:




PROCEDURE:

S- Edit


EDA ToolsS-Edit.



4.

Create new cell view

Cell

new view

Select the parameters and give ok.





8. Using D flip flop, NAND gate and NOR gate design the traffic light controller.

9. Create traffic light controller core and Pad the required input and outputs.



Spice.


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L Edit1. Launch L-Edit. Use FileNew to create your design file (layout file).









6. Extract the net list and simulate the design using T-spice and measure the static time

delay between input and output signals.


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