vlsi lab manual - digital cirucit design using vhdl

VIDYAA VIKAS COLLEGE OF ENGINEERING AND TECHNOLOGY, TIRUCHENGODE

070290076 - VLSI DESIGN LAB DEPARTMENT OF ECE 1

NAME :

ROLL NO :

SEM / YEAR : VI / III

SUBJECT CODE :

SUBJECT NAME : VLSI LABORATORY

LABORATORY MANUAL



VIDYAA VIKAS COLLEGE OF ENGINEERING AND

TECHNOLOGY

TIRUCHENGODE - 637214

Register No

Certified that this is the bonafide record of work done by

Selvan / Selvi ………………………………………………..……………….. of the ………….………

Semester ……………………………………………………………… branch during the

Year…………………… in the …………………….................Laboratory.

Staff in Charge Head of the Department

Submitted for the University Practical Examination on…………………………...

Internal Examiner External Examiner



EXTRACT OF ANNA UNIVERSITY – COIMBATORE SYLLABUS

I- Design and simulation of Combinational Logic Circuit using VHDL

1. Adder

2. Multiplexer and Demultiplexer

3. Encoder and Decoder

4. Multiplier

II- Design and simulation of Sequential logic circuit using VHDL

5. Flip Flops

6. Counter

7. Shift registers

8. Frequency Divider

III- CMOS Circuit design using SPICE (DC and Transient Analysis)

9. CMOS Inverter

10. CMOS NAND and NOR Gates

11. CMOS D Latch

IV- FPGA Implementation

12. 4 bit Adder



Introduction to VHDL

A digital system can be described at different levels of abstractions and from different points of view. As the design process progresses, the level and view are changed, either by human designers or by software tools, It is desirable to have a common framework to exchange information among the designers and various software tools, Hardware description languages (HDLs) serve this purpose. In this chapter we provide an overview of the design, use and capability of HDLs. Limitations of traditional programming languages:

A programming language is characterized by its syntax and semantics. The syntax comprises the grammatical rules used to write a program, and the semantics is the “meaning” associated with language constructs. When a new computer language is developed, the designers first study the characteristics of the underlying processes and then develop syntactic constructs and their associated semantics to model and express these characteristics.

Most traditional general-purpose programming languages, such as C, are modeled after a

sequential process. In this process, operations are performed in sequential order, one operation at a time. Since an operation frequently depends on the result of an earlier operation, the order of execution cannot be altered at will. The sequential process model has two major benefits.

• At the abstract level, it helps the human thinking process to develop an algorithm step by step.

• At the implementation level, the sequential process resembles the operation of a basic computer model and thus allows efficient translation from an algorithm to machine

instructions. The characteristics of digital hardware, on the other hand, are very different from those of

the sequential model. A typical digital system is normally built by smaller parts, with customized wiring that connects the input and output ports of these parts. When signal changes, the parts

connected to the signal are activated and a set of new operations is initiated accordingly. These operations are performed concurrently, and each operation will take a specific amount of time, which represents the propagation delay of a particular part, to complete. After completion, each

part updates the value of the corresponding output port. If the value is changed, the output signal will in turn activate all the connected parts and initiate another round of operations. This description shows several unique characteristics of digital systems, including the connections of

parts, concurrent operations, and the concept of propagation delay and timing. The sequential model used in traditional programming languages cannot capture the characteristics of digital hardware, and there is a need for special languages (i.e., HDLs) that are designed to model digital

hardware. VHDL:

VHDL and Verilog are the two most widely used HDLs. Although the syntax and

“appearance” of the two languages are very different, their capabilities and scopes are quite similar. Both are industrial standards and are supported by most software tools.

VHDL stands for VHSIC (Very High Speed Integrated Circuit) HDL. The development of

VHDL was sponsored initially by the US Department of Defense as a hardware documentation standard in the early 1980s and then was transferred to the IEEE (Institute of Electrical and Electronics Engineers). IEEE ratified it as IEEE standard 1076 in 1987, which is referred to as

VHDL-87. Each IEEE standard is reviewed every few years and is revised as needed, IEEE revised the VHDL standard in 1993, which is referred to as VHDL-93, and made minor modifications and bug fixes in 2001, which is referred to as VHDL-2001. Since no new language construct is

added in the new version, there is no significant difference between VHDL-93 and VHDL-2001. A suffix is sometimes added to the IEEE standard to indicate the year the standard was released. For example, VHDL-87 and VHDL-2001 are known as IEEE standards 1076-1987 and IEEE

1076-2001 respectively.



After the initial release, various extensions were developed to facilitate various design and modeling requirements. These extensions are documented in several IEEE standards:

• IEEE standard 1076.1-1999, VHDL Analog and Mixed Signal Extensions

(VHDLAMS): defines the extension for analog and mixed-signal modeling.

• IEEE standard 1076.2-1996, VHDL Mathematical Packages: defines extra

mathematical functions for real and complex numbers.

• IEEE standard 1076.3- 1997, Synthesis Packages: defines arithmetic operations over

a collection of bits. • IEEE standard 1076.4-1995, VHDL Initiative Towards ASK Libraries (VITAL):

defines a mechanism to add detailed timing information to ASIC cells.

• IEEE standard 1076.6-1999, VHDL Register Transfer Level (RTL) Synthesis: defines

a subset that is suitable for synthesis. • IEEE standard 1164- 1993 Multivalue Logic System for VHDL Model

Interoperability (std-logicJl64): defines new data types to model multivalue logic.

• IEEE standard 1029.1-1998, VHDL Waveform and Vector Exchange to Support Design and Test Verification (WAVES): defines how to use VHDL to exchange information in a

simulation environment Advantages of VHDL:

VHDL offers the following advantages for the digital design

• Standard • Technology / Vendor independent

• Portability • Modeling Capability • Reusability • Case Insensitive

Basic VHDL Statement – Syntax:

• Library • Entity • Architecture

• Component • Signal

• Variable • Constant • Simple When

• Selected When • Process • If statement • Case Statement

• While loop • For loop

• Wait statement



Library Syntax:

Library <Library_Name>; Use <Library_Name>.<Package_Name>.<Package_Parts>; Entity Syntax:

Entity <Entity_Name> is Port (<Port_name> : <Signal_Mode> <Signal_Type>); End <Entity_Name (optional)>; Architecture Syntax:

Architecture <Architecture_Name> of <Entity_Name> is <Declarations>; Begin <Concurrent Statements>; End <Architecture_Name (optional)>;

Component Declaration Syntax:

Component <Component_Name> Port (<Port_name> : <Signal_Mode> <Signal_Type>); End Component;

Component Instantiation Syntax:

Label: <Component_Name> Portmap (Signal mapping); Signal Declaration Syntax:

Signal <Signal_Name>: Signal_Type (Range):= ‘Initial Value’; Variable Declaration Syntax:

Variable <Variable_Name>: Variable_ Type (Range):= ‘Initial Value’; Constant Declaration Syntax:

Constant <Constant_Name>: Constant_ Type (Range):= ‘Initial Value’; Simple When/Else Syntax:

Assignment When Condition Else Assignment When Condition Else; With/Select/When:

With <identifier> Select Assignment When Value, Assignment When Value; (Whenever With/Select/When is used, all permutations must be tested.)

Process Syntax:

Label: Process (Sensitivity List) <Variable Declaration>; Begin <Sequential Statements>; End Process label;



If Statement Syntax:

If <Condition> Then <Assignments>; Elsif <Condition> Then <Assignments>; ……. Else <Assignments>; End If; Case Statement Syntax:

Case <identifier> is When value => assignments; When value => assignments; End Case; While Loop Statement;

Label: While <Condition> Loop

<Sequential Statements>; End Loop; For Loop Statement:

Label: For <identifier> In < range>Loop <Sequential Statements>; End Loop; Wait Statement Syntax:

Wait Until <Signal_Condition>; Wait On Signal<Signal1, Signal2...>; Wait For <time>; Wait statement when used inside process statement does not need sensitivity list in process statement.



Creating a New Project in ISE

In this section, you will create a new ISE project. A project is a collection of all files necessary to create and to download a design to a selected FPGA or CPLD device.

XILINX ISE Quick Start Tutorial

To create a new project for this tutorial:

1. Select File > New Project. The New Project Wizard appears.

2. First, enter a location (directory path) for the new project.

3. Type tutorial in the Project Name field. When you type tutorial in the Project Name field, a tutorial subdirectory is created automatically in the directory path you selected.

4. Select HDL from the Top-Level Module Type list, indicating that the top-level file in your project will be HDL, rather than Schematic or EDIF.

5. Click Next to move to the project properties page.

6. Fill in the properties in the table as shown below

Device Family : CoolRunner XPLA3 CPLDs Device : xcr3128xl Package : TQ144

Speed Grade : 7 Top-Level Module Type : HDL

Synthesis Tool : XST (VHDL/Verilog) Simulator : ModelSim Generated Simulation Language: VHDL or Verilog, depending on the language you want to use when running behavioral simulation.

When the table is complete, your project properties should look like the following:

7. Click Next to proceed to the Create New Source window in the New Project Wizard. At the end of the next section, your new project will be created. Creating an HDL Source

In this section, you will create a top-level HDL file for your design. Determine the language that you wish to use for the tutorial. Then, continue either to the “Creating a VHDL Source” section below.



This simple AND Gate design has two inputs: A and B. This design has one output called C

1. Click New Source in the New Project Wizard to add one new source to your project.

2. Select VHDL Module as the source type in the New Source dialog box.

3. Type in the file name andgate.

4. Verify that the Add to project checkbox is selected.

5. Click Next.

6. Define the ports for your VHDL source.

In the Port Name column, type the port names on three separate rows: A, B and C. In the

Direction column, indicate whether each port is an input, output, or inout. For A and B, select in from the list. For C, select out from the list.

7. Click Next in the Define VHDL Source dialog box.

8. Click Finish in the New Source Information dialog box to complete the new source file template.

9. Click Next in the New Project Wizard.

10. Click Next again.

11. Click Finish in the New Project Information dialog box.ISE creates and displays the new project

in the Sources in Project window and adds the andgate.vhd file to the project.



12. Double-click on the andgate.vhd file in the Sources in Project window to open the VHDL file in the ISE Text Editor. The andgate.vhd file contains:

• Header information.

• Library declaration and use statements.

• Entity declaration for the counter and an empty architecture statement.

13. In the header section, fill in the following fields:

Design Name : andgate.vhd

Project Name : andgate Target Device : xcr3128xl- TQ144 Description : This is the top level HDL file for an up/down counter.

Dependencies : None Note: It is good design practice to fill in the header section in all source files.

14. Below the end process statement, enter the following line:

C <= A and B;

15. Save the file by selecting File -> Save.

Check the Syntax of New Counter Module.

When the source files are complete, the next step is to check the syntax of the design. Syntax

errors and typos can be found using this step.

1. Select the counter design source in the ISE Sources window to display the related processes in

the Processes for Source window.

2. Click the “+” next to the Synthesize-XST process to expand the hierarchy.

3. Double-click the Check Syntax process.

When an ISE process completes, you will see a status indicator next to the process name.

• If the process completed successfully, a green check mark appears.

• If there were errors and the process failed, a red X appears.

• A yellow exclamation point means that the process completed successfully, but some warnings

occurred.

• An orange question mark means the process is out of date and should be run again.

4. Look in the Console tab of the Transcript window and read the output and status messages produced by any process that you run.

Caution! You must correct any errors found in your source files. If you continue without valid syntax, you will not be able to simulate or synthesize your design.



Simulation

1. Double click Launch ModelSim Simulator in the Process View window.

2. Right Click ‘a’ to open a context menu.

3. Select Force or Clock to add the signal.



4. Define the Clock or Force signal to load appropriate signal.

5. Run the simulation by clicking the Run icon in the Main or Wave window toolbar

6. Waveform can be observed in the wave window

7. Click the Run -All icon on the Main or Wave window toolbar. The simulation continues running until you execute a break command. 8. Click the Break icon. The simulation stops running.



9. To restart the simulation, click the Restart icon to reload the design elements and reset the simulation time to zero. The Restart dialog that appears gives you options on what to retain during the restart. Click the Restart button in the Restart dialog.

Assigning Pin Location:

1. Double-click the Assign Package Pins process found in the User Constraints process group. ISE

runs the Synthesis and Translate steps and automatically creates a User Constraints File (UCF). You will be prompted with the following message:



2. Click ‘yes’ to add the UCF file to your project. The counter.ucf file is added to your project and is visible in the Sources in Project window. The Xilinx Constraints Editor opens automatically. 3. Now the Xilinx Pinout and Area Constraints Editor (PACE) opens.

4. You can see your I/O Pins listed in the Design Object List window. Enter a pin location for each pin in the Loc column as specified below:

A: p90

B: p91

C: p53

5. Click on the Package View tab at the bottom of the window to see the pins you just added. Put your mouse over grid number to verify the pin assignment.

5. Select File _ Save. You are prompted to select the bus delimiter type based on the synthesis tool you are using. Select XST Default <> and click OK. 6. Close PACE.

Creating Configuration Data

The final phase in the software flow is to generate a program file and configure the device.

Generating a Program File

The Program File is a encoded file that is the equivalent of the design in a form that can be

downloaded into the CPLD device.

1. Double Click the Generate Programming File process located near the bottom of the Processes for Source window. The Program File is created. It is written into a file called andgate.jed. This is the actual configuration data.



Configuring the Device

iMPACT is used to configure your FPGA or CPLD device. This is the last step in the design process. This section provides simple instructions for configuring a Spartan-3 xc3s200 device

connected to your PC. Note: Your board must be connected to your PC before proceeding. If the device on your board

does not match the device assigned to the project, you will get errors. Please refer to the iMPACT Help for more information. To access the help, select Help > Help Topics. To configure the device:

1. Click the “+” sign to expand the Generate Programming File processes.

2. Double-click the Configure Device (iMPACT) process. iMPACT opens and the Configure devices dialog box is displayed.

3. In the Configure Devices dialog box, verify that Boundary-Scan Mode is selected and click Next.



4. Verify that Automatically connect to cable and identify Boundary-Scan chain is selected and click Finish.

5. If you get a message saying that there was one device found, click OK to continue.

6. The iMPACT will now show the detected device, right click the device and select New Configuration File.

7. The Assign New Configuration File dialog box appears. Assign a configuration file to each device

in the JTAG chain. Select the andgate.jed file and click Open. 8. Right-click on the counter device image, and select Program... to open the Program Options

dialog box.

9. Click OK to program the device. ISE programs the device and displays Programming Succeeded if the operation was successful. 10. Close iMPACT without saving.



Ex. No. : 01 ADDER

Date :

AIM:

To write a VHDL code for Half adder and Full adder circuit and simulate the results using

EDA (HDL Simulation) tool.

REQUIREMENT:

1. A PC with good configuration

2. ModelSim55eSE (EDA tool from Mentor Graphics) for simulation.

PROCEDURE:

1. Click the ModelSim SE 5.5e icon to start the simulation of VHDL code.

2. Select create a project options given on the welcome screen in order to create a new

project otherwise choose open a project to open the existing project.

3. Proper project name should be given along with the location to save the project in the

create project window.

4. In the main window go to file � New � Source � VHDL to get in to the source editor

window.

5. Enter the VHDL source code on that source editor window and save with the extension

.vhd in the project (project created) folder and location specified previously.

6. Select file � compile in the source editor window for compiling the written code. If there is

an error debug the error, save and compile again.

7. Load the design by selecting Design � load design in the main window after successful

compilation of the VHDL codes.

8. Select signals from the view menu of the main window for selecting the signals.

9. In signal window, choose edit � force / clock for applying the appropriate input levels for

the signals selected.

10. Select view � wave � signals in design to view the response of the design (Wave form)

with the help of run option from the signal window.

11. Continue the simulation for different input levels with the procedure stated above.



DIAGRAM:

BOOLEAN EXPRESSION:

S = A XOR B C = A and B TRUTH TABLE:

INPUT OUTPUT

A B SUM CARRY

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1



PROGRAM: Design Name: Half Adder _ Dataflow model library ieee; use ieee.std_logic_1164.all; -------------------------------------- entity HA is port (a,b:in std_logic ; s,c:out std_logic); end HA; --------------------------------------- architecture arc_HA of HA is begin

s<=a xor b; c<=a and b; end arc_HA;



DIAGRAM:

EXPRESSION: S = (A xor B) xor Ci

COUT = (A and B) or (Ci and (A xor B))

TRUTH TABLE:

INPUT OUTPUT

X Y Z S COUT

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1



PROGRAM: Design Name: Full adder _ structural model Library ieee; use ieee.std_logic_1164.all; ---------------------------------------------- entity FA is port(x,y,z:in std_logic; s,cout:out std_logic); end FA; ----------------------------------------------

architecture arc_FA of FA is component HA port(a,b:in std_logic; s,c:out std_logic); end component; component vor port(a,b:in std_logic; c:out std_logic); end component; signal s0,s1,s2:std_logic; begin P1: HA port map (x,y,s0,s1); p2: HA port map (s0,z,s,s2); p3: vor port map (s1,s2,cout); end arc_FA;



RESULT:

Thus the VHDL code for the half adder and full adder circuit was simulated and verified

with the truth table.



Ex. No. : 02 MULTIPLEXER

Date :

AIM:

To write a VHDL code for 4:1 Multiplexer and 1:4 Demultiplexer circuit and simulate the

results using EDA tool.

REQUIREMENT:



PROCEDURE:







window.



6. Select file � compile in the source editor window for compiling the written code. If there

is an error debug the error, save and compile again.




9. In signal window, choose edit � force / clock for applying the appropriate input levels

for the signals selected.






DIAGRAM:

TRUTH TABLE:

INPUT OUTPUT

S0 S1 Y

0 0 D0

0 1 D1

1 0 D2

1 1 D3



PROGRAM: Design name: Multiplexer(4:1)_Behavioural model library ieee; use ieee.std_logic_1164.all; --------------------------------------------------------------------- entity mux is

port (d0,d1,d2,d3: in std_logic; sel:in std_logic_vector(1 downto 0); y: out std_logic); end mux; -------------------------------------------------------------------- architecture arc_mux of mux is begin process(d0,d1,d2,d3,sel)

begin case sel is when "00"=>y<=d0; when "01"=>y<=d1; when "10"=>y<=d2; when "11"=>y<=d3; when others=>y<='Z'; end case; end process; end arc_mux;



DIAGRAM:

TRUTH TABLE:

ENABLE INPUT OUTPUT

E S0 S1 D0 D1 D2 D3

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1



PROGRAM: Design name: Demultiplexer(1:4)_Behavioural model library ieee; use ieee.std_logic_1164.all; ------------------------------------------------------------------------- entity dmux is

port (din: in std_logic; sel:in std_logic_vector(0 to 1); y: out std_logic_vector(0 to 3));

end dmux; ------------------------------------------------------------------------ architecture arc_dmux of dmux is begin process(din,sel) begin if(din='0')then

y<="0000"; else case sel is when "00"=>y<="1000"; when "01"=>y<="0100"; when "10"=>y<="0010"; when "11"=>y<="0001"; when others=>y<="ZZZZ"; end case; end if; end process; end arc_dmux;



RESULT:

Thus the VHDL code for the 4:1 Multiplexer and 1:4 Demultiplexer circuits was

simulated and verified with the truth table.



Ex. No. : 03 ENCODER AND DECODER

Date :

AIM:

To write a VHDL code for 8:3 Encoder and 3:8 Decoder circuit and simulate the results using

EDA tool.

REQUIREMENT:



PROCEDURE:







window.















DIAGRAM:

TABLE TRUTH:

ENABLE INPUT OUTPUT

E D0 D1 D2 D3 D4 D5 D6 D7 A B C

0 0 0 0 0 0 0 0 0 X X X

1 1 0 0 0 0 0 0 0 0 0 0

1 0 1 0 0 0 0 0 0 0 0 1

1 0 0 1 0 0 0 0 0 0 1 0

1 0 0 0 1 0 0 0 0 0 1 1

1 0 0 0 0 1 0 0 0 1 0 0

1 0 0 0 0 0 1 0 0 1 0 1

1 0 0 0 0 0 0 1 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1 1



PROGRAM: Design name: Encoder(8:3)_behavioural model library ieee; use ieee.std_logic_1164.all; ------------------------------------------------------------------------------------- entity enc_behav is port(enc:in std_logic_vector(0 to 7); e:in std_logic; y:out std_logic_vector(0 to 2)); end enc_behav; ------------------------------------------------------------------------------------- architecture arc_enc_behav of enc_behav is

begin process(enc,e) begin if(e='0')then y<="ZZZ"; else case enc is when "00000001"=>y<="000"; when "00000010"=>y<="001"; when "00000100"=>y<="010"; when "00001000"=>y<="011"; when "00010000"=>y<="100"; when "00100000"=>y<="101"; when "01000000"=>y<="110"; when "10000000"=>y<="111"; when others =>y<="ZZZ"; end case; end if; end process; end arc_enc_behav;



DIAGRAM:

TRUTH TABLE:

ENABLE INPUT OUTPUT

E A B C D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 0 X X X X X X X X

1 0 0 0 1 0 0 0 0 0 0 0

1 0 0 1 0 1 0 0 0 0 0 0

1 0 1 0 0 0 1 0 0 0 0 0

1 0 1 1 0 0 0 1 0 0 0 0

1 1 0 0 0 0 0 0 1 0 0 0

1 1 0 1 0 0 0 0 0 1 0 0

1 1 1 0 0 0 0 0 0 0 1 0

1 1 1 1 0 0 0 0 0 0 0 1



PROGRAM: Design name: Decoder(3:8)_Behavorial model library ieee; use ieee.std_logic_1164.all; ----------------------------------------------------------------------------------- entity DEC_behav is port(dec:in std_logic_vector(0 to 2); e:in std_logic; y:out std_logic_vector(0 to 7)); end dec_behav; -----------------------------------------------------------------------------------

architecture arc_dec_behav of dec_behav is begin process(dec,e) begin if(e='0') then y<="ZZZZZZZZ"; else case dec is when "000"=>y<="00000001"; when "001"=>y<="00000010"; when "010"=>y<="00000100"; when "011"=>y<="00001000"; when "100"=>y<="00010000"; when "101"=>y<="00100000"; when "110"=>y<="01000000"; when "111"=>y<="10000000"; when others =>y<="ZZZZZZZZ"; end case; end if; end process; end arc_dec_behav;



RESULT:

Thus the VHDL code for the 8:3 Encoder and 3:8 Decoder circuits was simulated and

verified with the truth table.



Ex. No. : 04 MULTIPLIER

Date :

AIM:

To write a VHDL code for 3 X 3 Array Multiplier circuit and simulate the result using EDA tool.

REQUIREMENT:



PROCEDURE:







window.















DIAGRAM:



PROGRAM: Design name: 3X3 Array Multiplier_Structural model library ieee; use ieee.std_logic_1164.all; ------------------------------------------------------------------------------- entity mul_struct is port(A:in std_logic_vector(0 to 2) ; b:in std_logic_vector(0 to 2) ; p:out std_logic_vector(4 downto 0); cout:out std_logic); end mul_struct; -------------------------------------------------------------------------------- architecture arc_mul_struct of mul_struct is

component vand port(A,B:in std_logic ; c:out std_logic); end component ; component HA port(a,b:in std_logic; s,c:out std_logic); end component; component FA port(x,y,z:in std_logic; s,cout:out std_logic); end component; signal x :std_logic_vector(0 to 14); begin c1: vand port map (a(0),b(0),p(0)); c2: vand port map (a(0),b(1),x(0)); c3: vand port map (a(1),b(0),x(1)); c4: HA port map (x(0),x(1),p(1),x(2)); c5: vand port map (a(2),b(0),x(7)); c6: vand port map (a(1),b(1),x(8)); c7: FA port map (x(2),x(7),x(8),x(6),x(3)); c8: vand port map (a(0),b(2),x(4)); c9: HA port map (x(6),x(4),p(2),x(5)); c10:HA port map (x(3),x(5),x(11),x(12)); c11: vand port map (a(2),b(1),x(9)); c12: vand port map (a(1),b(2),x(10)); c13: FA port map (x(9),x(10),x(11),p(3),x(13)); c14: vand port map (a(2),b(2),x(14)); c15: FA port map (x(12),x(13),x(14),p(4),cout); end arc_mul_struct;



RESULT:

Thus the VHDL code for the 3x3 Array Multiplier circuit was simulated and verified.



Ex. No. : 05 FLIP FLOP

Date :

AIM:

To write a VHDL code for RS, J K, D, T Flip-flops and simulate the results using EDA tool.

REQUIREMENT:



PROCEDURE:







window.















DIAGRAM:

TRUTH TABLE:

INPUT OUTPUT

CLOCK R S Q0 Q1

0 0 0 X X

1 0 0 Q0 Q1

1 0 1 1 0

1 1 0 0 1

1 1 1 INVALID INVALID



PROGRAM: Design name: RS-flip flop_Behavioural model library ieee; use ieee.std_logic_1164.all; ---------------------------------------------------- entity RS_FF is

port (clk,rst,R,S:in std_logic; Q, Qbar:inout std_logic);

end RS_FF; ---------------------------------------------------- architecture arch_RS_FF of RS_FF is begin

process(R,S,clk,rst) begin if(rst='1')then Q<='Z'; Qbar<='Z'; elsif(clk'event and clk='1')then if(S='0' and R='0')then Q<=Q; Qbar<=not Q; elsif(S='0' and R='1')then Q<='0'; Qbar<='1'; elsif(S='1' and R='0')then Q<='1'; Qbar<='0'; elsif(S='1' and R='1')then Q<='Z'; Qbar<='Z'; end if; end if; end process; end arch_RS_FF;



DIAGRAM:

TRUTH TABLE:

INPUT OUTPUT

CLOCK J K Q0 Q1

0 0 0 X X

1 0 0 Q0 Q1

1 0 1 0 1

1 1 0 1 0

1 1 1 Q1 Q0



PROGRAM: Design name: JK-flip flop_Behavioural model library ieee; use ieee.std_logic_1164.all; ---------------------------------------------------- entity JK_FF is

port (clk,rst,J,K:in std_logic; Q, Qbar:inout std_logic);

end JK_FF; ---------------------------------------------------- architecture arch_JK_FF of JK_FF is begin

process(J,K,clk,rst) begin if(re='1')then Q<='Z'; Qbar<='Z'; elsif(clk'event and clk='1')then if(J='0' and K='0')then Q<=Q; Qbar<=not Q; elsif(J='0' and K='1')then Q<='0'; Qbar<='1'; elsif(J='1' and K='0')then Q<='1'; Qbar<='0'; elsif(J='1' and K='1')then Q<=not Q; Qbar<=Q; end if; end if; end process; end arch_JK_FF;



DIAGRAM:

TRUTH TABLE:

INPUT OUTPUT

CLOCK D Q0 Q1

0 0 0 0

1 0 0 1

1 1 1 0



PROGRAM: Design name: D-FF behavioral model library ieee; use ieee.std_logic_1164.all; ----------------------------------------------- entity dff is

port (clk,reset,d:in std_logic; q:out std_logic);

end dff; ----------------------------------------------- architecture arch_dff of dff is begin

process (d,clk,reset) begin if(reset='1') then q<='0'; elsif(clk'event and clk='1') then q<=d; end if; end process; end arch_dff;



DIAGRAM:

TRUTH TABLE:

INPUT OUTPUT

CLOCK T Q0 Q1

0 0 0 0

1 0 1 0

1 1 0 1



PROGRAM: Design name: T-FF_behavioural model library ieee; use ieee.std_logic_1164.all; ---------------------------------------------- entity tff is

port (clk,reset,t:in std_logic; q:out std_logic);

end tff; ---------------------------------------------- architecture arch_tff of tff is begin

process (t,clk,reset) begin if (reset='1’) then q<='0'; elsif (clk'event and clk='1' and t =’1’) then q<=not t; end if; end process; end arch_tff;



RESULT:

Thus the VHDL code for the RS, JK, D, and T Flip-flops was simulated and verified with

the truth table.



Ex. No. : 06 COUNTER

Date :

AIM:

To write a VHDL code for Counter circuits and simulates the results using EDA tool

REQUIREMENT:



PROCEDURE:







window.













DIAGRAM:



TRUTH TABLE:

CLOCK INPUT OUTPUT

CLK A B C D D0 D1 D2 D3

0 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 1

2 0 0 0 1 0 0 1 0

3 0 0 1 0 0 0 1 1

4 0 0 1 1 0 1 0 0

5 0 1 0 0 0 1 0 1

6 0 1 0 1 0 1 1 0

7 0 1 1 0 0 1 1 1

8 0 1 1 1 1 0 0 0

9 1 0 0 0 1 0 0 1

10 1 0 0 1 0 0 0 0



PROGRAM: Design name: BCD Counter_Behavioural model library ieee; use ieee.std_logic_1164.all; entity bcd IS

port ( clk, rst: in std_logic; count: out std_logic_vector(3 downto 0));

end bcd; ---------------------------------------------------------------------- architecture arch_bcd OF bcd IS type state is (zero, one, two, three, four, five, six, seven, eight, nine); signal pr_state, nx_state: state; begin

---------------------------------------------------------------------- process(rst, clk) begin if (rst='1') then pr_state <= zero; elsif(clk’event and clk='1') then pr_state <= nx_state; end if; end process; -------------------------------------------------------------------- process(pr_state) begin

case pr_state is WHEN zero =>count <= "0000"; nx_state <= one; WHEN one =>count <= "0001"; nx_state <= two; WHEN two =>count <= "0010"; nx_state <= three; WHEN three =>count <= "0011"; nx_state <= four; WHEN four =>count <= "0100"; nx_state <= five; WHEN five =>count <= "0101"; nx_state <= six; WHEN six =>count <= "0110"; nx_state <= seven; WHEN seven =>count <= "0111"; nx_state <= eight; WHEN eight =>count <= "1000"; nx_state <= nine; WHEN nine =>count <= "1001"; nx_state <= zero; end case; end process; end arch_bcd;



TRUTH TABLE: 3 BIT - UP COUNTER

CLOCK INPUT OUTPUT

CLK A B C D1 D2 D3

0 0 0 0 0 0 0

1 0 0 0 0 0 1

2 0 0 1 0 1 0

3 0 1 0 0 1 1

4 0 1 1 1 0 0

5 1 0 0 1 0 1

6 1 0 1 1 1 0

7 1 1 0 1 1 1

8 1 1 1 0 0 0



PROGRAM: Design name: 3-bit up Counter_Behavioural model library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ------------------------------------------------------ entity up_counter is

port(Clk, Set : in std_logic; Q : out std_logic_vector(2 downto 0));

end up_counter; -------------------------------------------------------

architecture archi_up_counter of up_counter is signal tmp: std_logic_vector(2 downto 0); begin process (Clk) begin if (Clk'event and Clk='1') then if (Set='1') then tmp <= "000"; else tmp <= tmp + 1; end if; end if; end process; Q <= tmp; end archi_up_counter;



TRUTH TABLE: 3 – BIT DOWN COUNTER

CLOCK INPUT OUTPUT

CLK A B C D1 D2 D3

0 0 0 0 0 0 0

1 0 0 0 1 1 1

2 0 0 1 1 1 0

3 0 1 0 1 0 1

4 0 1 1 1 0 0

5 1 0 0 0 1 1

6 1 0 1 0 1 0

7 1 1 0 0 0 1

8 1 1 1 0 0 0



PROGRAM: Design name: 3-bit down Counter_Behavioural model library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; --------------------------------------------------------- entity down_counter is port(Clk, Set : in std_logic; Q : out std_logic_vector(2 downto 0)); end down_counter; --------------------------------------------------------- architecture archi_down_counter of down_counter is

signal tmp: std_logic_vector(2 downto 0); begin process (Clk) begin if (Clk'event and Clk='1') then if (Set='1') then tmp <= "111"; else tmp <= tmp -1; end if; end if; end process; Q <= tmp; end archi_down_counter;



RESULT:

Thus the VHDL code for the counter (BCD, 3-Bit UP & DOWN) was simulated and

verified with the truth table.



Ex. No. : 07 SHIFT REGISTER

Date :

AIM:

To write a VHDL code for Shift Registers (SISO, SIPO, PIPO, PISO) and simulate the

results using EDA tool.

REQUIREMENT:


2. ModelSim5.5eSE (EDA tool from Mentor Graphics) for simulation.

PROCEDURE:


2. Select create a project options given on the welcome screen in order to create a

new project otherwise choose open a project to open the existing project.

3. Proper project name should be given along with the location to save the project in

the create project window.

4. In the main window go to file � New � Source � VHDL to get in to the source

editor window.

5. Enter the VHDL source code on that source editor window and save with the

extension .vhd in the project (project created) folder and location specified

previously.

6. Select file � compile in the source editor window for compiling the written code. If

there is an error debug the error, save and compile again.

7. Load the design by selecting Design � load design in the main window after

successful compilation of the VHDL codes.


9. In signal window, choose edit � force / clock for applying the appropriate input

levels for the signals selected.

10. Select view � wave � signals in design to view the response of the design (Wave

form) with the help of run option from the signal window.




SERIAL IN SERIAL OUT

DIAGRAM:

TRUTH TABLE: Data Input: 1

CLOCK Dout

1 0

2 0

3 0

4 1



PROGRAM: Design name: Serial In Serial Out library ieee; use ieee.std_logic_1164.all; ---------------------------------------------- entity siso is

port (din,clk:in bit; dout :out bit);

end siso; ---------------------------------------------- architecture arch_siso of siso is signal a,b,c:bit; begin process(clk)

begin if (clk’event and clk=’1’) then dout<=c; c<=b; b<=a; a<=din; end if; end process; end arch_siso;



PARALLEL IN PARALLEL OUT DIAGRAM:

TRUTH TABLE:

CLOCK INPUT OUTPUT

D0 D1 D2 D3 Q0 Q1 Q2 Q3

1 1 0 1 0 1 0 1 0

2 1 1 1 1 1 1 1 1



PROGRAM: Design name: Parallel In Parallel Out Shift Register_Structural Model library ieee; use ieee.std_logic_1164.all; ------------------------------------------ entity pipo is

port(din,clk,re:in std_logic; dout:out std_logic);

end pipo; ------------------------------------------ architecture arch_pipo of pipo is component dff

port (clk,reset,d:in std_logic; q:inout std_logic); end component; signal q0,q1:std_logic; begin

c1:dff port map(din,clk,re,q0); c2:dff port map(q0,clk,re,q1); c3:dff port map(q1,clk,re,dout);

end arch_pipo;



PARALLEL IN SERIAL OUT

DIAGRAM:

TRUTH TABLE: Data input: 1011



PROGRAM: Design name: Parallel In Serial Out Shift Register_behavioural Model library ieee; use ieee.std_logic_1164.all; ---------------------------------------------------------------------------- entity piso is port(clk,load:in std_logic; d:in std_logic_vector(3 downto 0); dout:out std_logic); end piso; ---------------------------------------------------------------------------- architecture arc_piso of piso is signal reg:std_logic_vector(3 downto 0); begin

process(clk) begin if(clk'event and clk='1')then if(load='1')then reg<=d; else reg<=reg(2 downto 0)&'0'; end if; end if; end process; dout<=reg(3); end arc_piso;



SERIAL IN PARALLEL OUT

DIAGRAM:

TRUTH TABLE:

Data input: 1111



PROGRAM: Design name: Serial In Parallel Out Shift Register_Structural Model library ieee; use ieee.std_logic_1164.all; -------------------------------------------------------------------------- entity sipo is port(d,rst,clk:in std_logic; dout:inout std_logic_vector(3 downto 0)); end sipo; ------------------------------------------------------------------------- architecture arc_sipo of sipo is component dff port(clk,reset,d:in std_logic; q:out std_logic);

end component; begin c1:dff port map(clk,rst,d,dout(0)); c2:dff port map(clk,rst,dout(0),dout(1)); c3:dff port map(clk,rst,dout(1),dout(2)); c4: dff port map(clk,rst,dout(2),dout(3)); end arc_sipo;



RESULT:

Thus the VHDL code for the Shift Registers (SISO, SIPO, PIPO and PISO) circuits was

simulated and verified.



Ex. No. : 08 FREQUENCY DIVIDER (DIVIDE BY EIGHT)

Date :

AIM:

To write a VHDL code for Frequency divider (Divide by Eight) and simulate the result using

EDA tool.

REQUIREMENT:



PROCEDURE:


2. Select create a project options given on the welcome screen in order to create a

new project otherwise choose open a project to open the existing project.

3. Proper project name should be given along with the location to save the project in

the create project window.

4. In the main window go to file � New � Source � VHDL to get in to the source

editor window.

5. Enter the VHDL source code on that source editor window and save with the

extension .vhd in the project (project created) folder and location specified

previously.

6. Select file � compile in the source editor window for compiling the written code.

If there is an error debug the error, save and compile again.

7. Load the design by selecting Design � load design in the main window after

successful compilation of the VHDL codes.


9. In signal window, choose edit � force / clock for applying the appropriate input

levels for the signals selected.

10. Select view � wave � signals in design to view the response of the design (Wave

form) with the help of run option from the signal window.




PROGRAM: Design name: Frequency divider_ Behavioural model library ieee; use ieee.std_logic_1164.all; ------------------------------------------------------------------- entity fdiv is

port(clk:in std_logic; out1:buffer std_logic:='1');

end fdiv; --------------------------------------------------- architecture arch_fdiv of fdiv is signal count: integer:=0;

begin process(clk) begin if(clk'event and clk='1')then count<=count+1; if(count=4)then out1<=not out1; count<=0; end if; end if; end process; end arch_fdiv;



RESULT:

Thus the VHDL code for frequency divider was simulated and verified.



Ex. No. : 09 4 – BIT RIPPLE CARRY ADDER (FPGA IMPLEMENTATION)

Date :

AIM:

To write a VHDL code for 4-bit ripple carry adder circuit and simulate the results using EDA

tool.

REQUIREMENT:



3. Xilinx 8.1 for synthesis

PROCEDURE:







window.















DIAGRAM:



PROGRAM: Design name: 4 Bit ripple carry adder library ieee; use ieee.std_logic_1164.all; ----------------------------------------------------------- entity padder is generic (n: integer := 4);

port(a, b : in std_logic_vector (n-1 downto 0); cin : in std_logic;

y : out std_logic_vector (n-1 downto 0); cout : out std_logic);

end padder; -----------------------------------------------------------

Architecture arc_padder of padder is signal c : std_logic_vector (n downto 0); begin c(0) <= cin; G1: for i in 0 to n-1 generate y(i) <= a(i) xor b(i) xor c(i); c(i+1) <= (a(i) and b(i)) or (b(i) and c(i)) or (c(i) and a(i)); end generate; cout <= c(n); end arc_padder;



RESULT:

Thus the VHDL code for the 4 bit adder circuit was simulated and implemented using

Xilinx ISE 8.1 tool.



Ex. No. : 10 CMOS CIRCUIT DESIGN USING SPICE - INVERTER

Date :

AIM:

To design a CMOS inverter circuit using SPICE and to perform the following analysis

(i). DC Analysis

(ii). Transient Analysis

REQUIREMENTS:


2. Orcad PSPICE 9.1 release

PROCEDURE:

1. Choose ORCAD capture icon from the program window.

2. In file, select new and then project.

3. Enter the name of the project, create the new project using A/D or mixed modeling

and specify the location.

4. Create PSPICE project as a blank project.

5. In the schematic window click on the right most corners to select the tools.

6. Select the place part tool to select the components that are specified circuit diagram.

7. Place the components on the schematic page as given in the circuit diagram.

8. Select place wire tool to connect the components as per the circuit diagram.

9. Place the junctions where ever it is necessary.

10. Select the place ground tool to place ground as needed in the circuit diagram.

11. Select the voltage / level marker from the tool bar and place as per the requirement

and save the project.

12. Choose new simulation profile and name the simulation profile.

13. Select edit simulation settings from the tool bar and make the necessary simulation

settings.

FOR DC ANALYSIS:

(i). In the Simulation settings window choose DC sweep from the Analysis type drop Down menu.

(ii). Select Voltage source in sweep variable option and also select the Name of the Source with reference to the circuit design.

(iii) Select the sweep type as linear and mention the start, end and increment Values as per the design and analysis needs.



FOR TRANSIENT ANALYSIS:

(i). In the Simulation settings window choose Time Domain (Transient) from the Analysis type drops down menu.

(ii). Enter run to time value and maximum step size in Transient options.

14. Select Run PSPICE option and obtain the results.

15. Adjust the run to time by selecting edit simulation settings for proper results.

CIRCUIT DIAGRAM:

4.699V

0V

0

V2

TD = 0

TF = 10ns

PW = 5n

PER = 10n

V1 = 0v

TR = 10ns

V2 = 5v

M4

MbreakPD

0

M3

MbreakND

0

0V

5.000V V1

5Vdc

V

V



RESULT:

Thus the CMOS inverter circuit using PSPICE was designed and the DC and Transient

analysis were performed.



Ex. No. : 11 CMOS CIRCUIT DESIGN USING SPICE – NAND & NOR GATE

Date :

AIM:

To design a CMOS NAND and NOR circuit using SPICE and to perform the following

analysis

(i). DC Analysis


REQUIREMENTS:



PROCEDURE:



3. Enter the name of the project, create the new project using A/D or mixed modeling

and specify the location.








11. Select the voltage / level marker from the tool bar and place as per the requirement

and save the project.



settings.

FOR DC ANALYSIS:







(i). In the Simulation settings window choose Time Domain (Transient) from the Analysis type drop down menu.




CIRCUIT DIAGRAM (NAND GATE):

0V

V3

TD = 0

TF = 5n

PW = .5m

PER = 1m

V1 = 5

TR = 5n

V2 = 5

0

M3

MbreakP

50.10nV

V1

5Vdc

V0V

5.000V

0

M2

MbreakN

V

V

V2

TD = 0

TF = 5ns

PW = .5m

PER = 1m

V1 = 0

TR = 5ns

V2 = 5

M1

MbreakN

0

5.000V

5.000V

M4

MbreakP

0

CIRCUIT DIAGRAM (NAND GATE):

V

0V

M3

MbreakP

5.000V

M4

MbreakP0

V

V

V1

5Vdc

0

5.000V

V2

TD = 0

TF = 5n

PW = .5m

PER = 1m

V1 = 0V

TR = 5n

V2 = 5

0V

5.000V

0

0

M1

MbreakN

0V

M2

MbreakN

V4

TD = 0

TF = 5n

PW = .5m

PER = 1m

V1 = 0

TR = 5n

V2 = 5



RESULT:

Thus the CMOS NAND and NOR circuit using PSPICE was designed and the DC and

Transient analysis were performed.



Ex. No. : 11 CMOS CIRCUIT DESIGN USING SPICE – D LATCH

Date :

AIM:

To design a CMOS D – LATCH circuit using SPICE and to perform the following analysis

(i). DC Analysis


REQUIREMENTS:



PROCEDURE:



3. Enter the name of the project, create the new project using A/D or mixed modeling and

specify the location.








11. Select the voltage / level marker from the tool bar and place as per the requirement and

save the project.



settings.

FOR DC ANALYSIS:







(i). In the Simulation settings window choose Time Domain (Transient) from the Analysis type drop down menu.




CIRCUIT DIAGRAM (CMOS D - LATCH):

M6

MbreakP

V

5.000V

M1

MbreakN

V2

5Vdc

12.55nV

0

5.000V

0V

0

M5

MbreakN

M10

MbreakP

0

0

V3

5Vdc

V

0V

0V

M3

MbreakN

0

M9

MbreakP

M4

MbreakN

M7

MbreakP

5.000V

V

5.000V

M2

MbreakN

V4

TD = 0

TF = 5n

PW = .5m

PER = 1m

V1 = 0

TR = 5n

V2 = 5v

0

V

M8

MbreakP



RESULT:

Thus the CMOS D – Latch circuit using PSPICE was designed and the DC and Transient

analysis were performed.

vlsi lab manual - digital cirucit design using vhdl

Documents

vidyaa vikas

process completed

vlsi design

traditional

wave window

source editor

digital hardware

sequential