vlsi presentation part 2
TRANSCRIPT
![Page 1: VLSI Presentation Part 2](https://reader030.vdocuments.net/reader030/viewer/2022032504/55c443a0bb61eb28518b46d9/html5/thumbnails/1.jpg)
Tic Tac ToeVLSI Project Presentation
(Part 2)Aaron Williams and Shayda Shahbazi
December 1, 2014
![Page 2: VLSI Presentation Part 2](https://reader030.vdocuments.net/reader030/viewer/2022032504/55c443a0bb61eb28518b46d9/html5/thumbnails/2.jpg)
● vdd/gnd● clk
9 inputs (1 for each block)● 18 outputs (9 for each player)● 9 outputs (3 bits for counting win/loss/draw)● 1 hidden input(1/2/3 for reset)
Layout Aspects
Overall Implementation
● Pitch = 35.4u○ Due to High number of inputs per component
![Page 3: VLSI Presentation Part 2](https://reader030.vdocuments.net/reader030/viewer/2022032504/55c443a0bb61eb28518b46d9/html5/thumbnails/3.jpg)
![Page 4: VLSI Presentation Part 2](https://reader030.vdocuments.net/reader030/viewer/2022032504/55c443a0bb61eb28518b46d9/html5/thumbnails/4.jpg)
![Page 5: VLSI Presentation Part 2](https://reader030.vdocuments.net/reader030/viewer/2022032504/55c443a0bb61eb28518b46d9/html5/thumbnails/5.jpg)
Transistor CountDFF: 6+4+8+8=26 transistorsMemory: 26*18 + 8*18 + 6*9 + 12 = 678Checker: 9*18 + 9*8 = 262Comb: 9*6 = 54Total Win:158*3 + 28 + 64*2 = 630Turn: 164+10+16 = 190Out of AI: 1814Conditions: 6*9 +96+48=198Filter: 10*9 + 18 = 108Extra: 8*6 +4 +4+6+8+10+12+14+16 =122Think: 4*10+4*8+6+18=96Memory: 9*26 + 4 = 238Memroy_Add:3*26 + 12+12+6+14+36=158Win: 6*8 + 16 = 64Counter:4*26 + 12 +14+ 34=164Total AI: 198*2 +108*2+122+96+238+164=12323046 transistors total
![Page 6: VLSI Presentation Part 2](https://reader030.vdocuments.net/reader030/viewer/2022032504/55c443a0bb61eb28518b46d9/html5/thumbnails/6.jpg)
![Page 7: VLSI Presentation Part 2](https://reader030.vdocuments.net/reader030/viewer/2022032504/55c443a0bb61eb28518b46d9/html5/thumbnails/7.jpg)
Component Conditions
![Page 8: VLSI Presentation Part 2](https://reader030.vdocuments.net/reader030/viewer/2022032504/55c443a0bb61eb28518b46d9/html5/thumbnails/8.jpg)
Component Checker
![Page 9: VLSI Presentation Part 2](https://reader030.vdocuments.net/reader030/viewer/2022032504/55c443a0bb61eb28518b46d9/html5/thumbnails/9.jpg)
Component Turn
![Page 10: VLSI Presentation Part 2](https://reader030.vdocuments.net/reader030/viewer/2022032504/55c443a0bb61eb28518b46d9/html5/thumbnails/10.jpg)
Combination Win
![Page 11: VLSI Presentation Part 2](https://reader030.vdocuments.net/reader030/viewer/2022032504/55c443a0bb61eb28518b46d9/html5/thumbnails/11.jpg)
Memory Main
![Page 12: VLSI Presentation Part 2](https://reader030.vdocuments.net/reader030/viewer/2022032504/55c443a0bb61eb28518b46d9/html5/thumbnails/12.jpg)
Filter Component
![Page 13: VLSI Presentation Part 2](https://reader030.vdocuments.net/reader030/viewer/2022032504/55c443a0bb61eb28518b46d9/html5/thumbnails/13.jpg)
Component Extra
![Page 14: VLSI Presentation Part 2](https://reader030.vdocuments.net/reader030/viewer/2022032504/55c443a0bb61eb28518b46d9/html5/thumbnails/14.jpg)
Memory Add
![Page 15: VLSI Presentation Part 2](https://reader030.vdocuments.net/reader030/viewer/2022032504/55c443a0bb61eb28518b46d9/html5/thumbnails/15.jpg)
![Page 16: VLSI Presentation Part 2](https://reader030.vdocuments.net/reader030/viewer/2022032504/55c443a0bb61eb28518b46d9/html5/thumbnails/16.jpg)
Verilog Test Code-Tests applying a set of inputs to the circuit
Future Tests:-Find a set of conditions that guarantee a Computer victory-Find a set of conditions that guarantee a Human victory-Find a set of conditions that guarantee a draw
![Page 17: VLSI Presentation Part 2](https://reader030.vdocuments.net/reader030/viewer/2022032504/55c443a0bb61eb28518b46d9/html5/thumbnails/17.jpg)
Next Steps
● Complete testing● Complete layout
![Page 18: VLSI Presentation Part 2](https://reader030.vdocuments.net/reader030/viewer/2022032504/55c443a0bb61eb28518b46d9/html5/thumbnails/18.jpg)
Thank You!