vlsi problem set

7/26/2019 Vlsi problem set

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ECE 438: Digital Integrated Circuits

Assignment #4 Solution The Inverter

Text: Chapter 5, Digital Integrated Circuits 2ndEd, Rabaey

1) Consider the CMOS inverter circuit in Figure P1 with the following parameters. Assume longchannel transistors and no velocity saturation.

Find VOL, VOH, VIL, and VIHon the VTC. Also find the noise margins of this inverter.

Figure P1

Vin Vout


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2) Consider a CMOS inverter circuit with power supply voltage VDD= 3.3V. The I-V characteristicof the NMOS transistor is specified below. When VGS=3.3V, the drain current reaches itssaturation level Isat= 2mA, for VDS> 2.5V. Assume that the input signal applied to the gate is astep pulse that switches instantaneously, from 0V to 3.3V.


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3) Consider a CMOS inverter with supply voltage of VDD= 5V. Assume long channel transistorsand no velocity saturation. Determine the fall time tfall, defined as the time elapsed between 90%to 10% transition of the output voltage. Assume kn = 20A/V

2, others are given below.


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4) An inverter is simulated in SPICE in the following conditions and characteristics


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5) For the resistive-load inverter in Figure P5, and assume an output load of 3 pFGiven: VT0= 0.43V, VDSAT=0.63, kn=115A/V

2, = 0.06 V-1, VOH= 2.5V, VOL= 0.0463V

Figure P5

a) Calculate tplh, tphl, and tp

SolutiontpLH=0.69RLCL= 155 nsec.

For tpHL: First calculate Ronfor Voutat 2.5V and 1.27315V(VOH VOL)/2.At Vout=2.5V, IDVsat=0.439mA giving Ron= 5695


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t Vout=1.27315V, IDvsat=0.4106mA giving Ron= 3100.85.Thus, the average resistance between Vout=2.5V and Vout=1.27315V is Raverage=4.398k.tpHL=0.69RaverageCL=9.104nsec.tp=av{tpLH, tpHL}=82.05nsec

ASIDE: if first-order approximation is considered, such that the 50% point is Vdd/2t Vout=1.25V, IDvsat=0.41m giving Ron= 3049.Thus, the average resistance between Vout=2.5V and Vout=1.25V is Raverage=4.372k.tpHL=0.69RaverageCL=9.05nsec.tp=av{tpLH, tpHL}=82.0nsec

b) Are the rising and falling delays equal? Why or why not?

SolutiontpLH>> tpHLbecause RL=75k is much larger than the effective linearized on-resistance of M1.

c)

Compute the static and dynamic power dissipation assuming the gate is clocked as fast aspossible.

SolutionStatic Power:

VIN=VOLgives Vout=VOH=2.5V, thus IVDD=0A so PVDD=0W.VIN=VOHgives Vout=VOL=46.3mV, which is in the linear region.Calculating the current through M1 gives IVDD=32.8APVDD=82W

Dynamic Power:NOTE: fmax= 1 / tp =1 / 82.0nsecPdyn=CLV*Vdd*fmax=3pF*(2.5V-46.3mV)*2.5V*12.2MHz=0.225mW.

6) Figure P6 shows two implementations of MOS inverters. Circuit A uses only NMOS transistors.Circuit B is a static CMOS inverter (NOTE: short-channel transistors and velocity saturated)

Figure P6

W/L = 0.75/0.25


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a) Calculate VOH, VOL, VMfor each case.


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Setting ID3+ ID4= 0, we get VM= 1.095V.So the assumption that both transistors were velocity saturated holds.

b) Find VIH, VIL,NMLandNMHfor each inverter and comment on the results. Given that VIL=0.503V and VIH = 1.35V for circuit A, and VIL= 0.861V and VIH= 1.22V for circuit B. Howcan you increase the noise margins and reduce the undefined region?

SolutionCircuit ABased on the VOLand VOHfrom part (a)VIL= 0.503V, VIH = 1.35VNMH= VOH- VIH= 1.765 - 1.35 = 0.415V, NML= VIL- VOL= 0.503- 0.263 = 0.240VCircuit BVIL= 0.861V, VIH= 1.22VNMH= VOH- VIH= 2.5V - 1.22V = 1.28V, NML= VIL- VOL= 0.861V- 0V = 0.861VWe can increase the noise margins by moving VMcloser to the middle of the outputvoltage swing.

c) Comment on the differences in the VTCs, robustness and regeneration of each inverter.

SolutionIt is clear from the two VTCs, that the CMOS inverter is more robust, since the low andhigh noise margins are higher than the first inverter. Also the regeneration in the secondinverter is greater since it provides rail to rail output and the gain of the inverter is muchgreater.

7) For this problem assume:VDD= 2.5V, WP/L = 1.25/0.25, WN/L = 0.375/0.25,L=Leff=0.25m (i.e.xd= 0m), CL=Cinvgate,kn = 115A/V

2, kp= -30A/V2, Vtn0= | Vtp0| = 0.4V, = 0V

-1, = 0.4, 2|f|=0.6V, and tox

= 58A. Use the HSPICE model parameters for parasitic capacitance given below (i.e. Cgd0,Cj,Cjsw), and assume that VSB=0V. (NOTE: short-channel transistors and velocity saturated)


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Figure P7

a) What is the VMfor this inverter?

SolutionAssume that VMis around midrail (1.25V). That means that the NMOS is velocity saturatedand the PMOS is saturated. To find VM, we set the sum of the currents at Voutequal to0 using the correct equation for each device:

b) Calculate tPHL, tPLHassuming CLeff= 6.5fF. (Assume an ideal step input, i.e. trise=tfall=0. Dothis part by computing the average current used to charge/discharge CLeff.)

Solution

We can estimate the propagation delay using the approximation t =Q/I, where Q


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= CLeffVDDandI is the average current used to charge/discharge CLeff. During the high-to-lowtransition CLeffis discharged through the NMOS transistor soI = IavgN. During the low-to-hightransition CLeffis charged through the PMOS transistor soI = IavgP. In summary:

included channel length modulation, but it is ok if your solution did not (see problemassumptions).

8) Consider the circuit in Figure P8 (which is a low-swing driver, not an inverter).Given VTn0= 0.43 and VTp0= -0.4. NOTE: short-channel transistors and velocity saturated.

a) What is the voltage swing on the output node (Vout)? Assume =0.

Figure P8

0.223

0.2080.216 37.65

IavgP= IavgN=


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SolutionThe range will be from 0.4 V to 2.07 V, since the PMOS is a weak pull down deviceand the NMOS is a weak pull up device.

b)

Compute tpLH(i.e. the time to transition from VOLto (VOH+ VOL) /2). Assume the input risetime to be 0. VOLis the output voltage with the input at 0V and VOHis the output voltagewith the input at 2.5V.

SolutionWhen the input is high and the capacitor charges, the PMOS device is in cutoff and theNMOS is velocity saturated for the duration of the charging. The total voltage range is 0.4 Vto 2.07 V, so the midpoint is 1.24 V. We can use the average current method to approximatetplh. For the velocity saturated NMOS:

Solving for the current at V=0.4 V and V=1.24 V and averaging yields an average current of404 uA. Then:

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