VLSI TESTINGVLSI TESTING

MEMORY BISTMEMORY BIST

by:by:Saeid HashemiSaeid Hashemi

Mehrdad FalakparvazMehrdad Falakparvaz

1) : WHAT IS BIST ?1) : WHAT IS BIST ?

BIST (Built-In Self-Test) : BIST (Built-In Self-Test) : is a design is a design technique in which parts of a circuit are used technique in which parts of a circuit are used to test the circuit itself .to test the circuit itself .– Hardcore : Hardcore : Parts of a circuit that must be Parts of a circuit that must be

operational to execute a self test operational to execute a self test BIST categories : BIST categories :

Memory BIST Memory BIST Logic BISTLogic BIST Logic + Embedded memory (ASICs)Logic + Embedded memory (ASICs)

Applications : Applications : Mission-critical sytems, self-Mission-critical sytems, self-diagnostic circuitry (consumer electronics).diagnostic circuitry (consumer electronics).

2) : BIST Concepts2) : BIST Concepts

BIST Techniques BIST Techniques Test Pattern Generation Techniques Test Pattern Generation Techniques

(TPG) (TPG) Test Response Compression TechniquesTest Response Compression Techniques

3 ) BIST Techniques3 ) BIST Techniques

The BIST techniques are classified The BIST techniques are classified bassed on the operational condition of bassed on the operational condition of the circuit under test (CUT):the circuit under test (CUT):

Off-Line BISTOff-Line BIST On-Line BISTOn-Line BIST

3-1) : On-Line BIST 3-1) : On-Line BIST

Testing occures during normal functional Testing occures during normal functional operating conditions (No test mode, Real-Time operating conditions (No test mode, Real-Time error detection).error detection).

Concurrent Concurrent :Occures simultaneously :Occures simultaneously with normal functional operation with normal functional operation (Realized by using coding techniques).(Realized by using coding techniques).

Nonconcurrent Nonconcurrent : Carried out while in : Carried out while in idle state (Interruptible in any state, idle state (Interruptible in any state, realized by executing diagnostic realized by executing diagnostic software/firmware routines).software/firmware routines).

3-2) : Off-Line BIST3-2) : Off-Line BIST

Deals with testing a system when it is not carrying Deals with testing a system when it is not carrying out its normal functions (Test mode, Non-Real-Time out its normal functions (Test mode, Non-Real-Time error detection).error detection).

Testing by using either on-board TPG + Output Testing by using either on-board TPG + Output Response Analyzer (ORA) or Microdiagnostic Response Analyzer (ORA) or Microdiagnostic routines.routines.

Structural : Structural : Execution based on the structure Execution based on the structure of the CUT(Explicit fault model - LFSR, ...).of the CUT(Explicit fault model - LFSR, ...).

Functional : Functional : Running based on functional Running based on functional description of CUT(Functional fault model - description of CUT(Functional fault model - Diagnostic software).Diagnostic software).

4) : Test Pattern 4) : Test Pattern Generation TechniquesGeneration Techniques

Exhaustive : Exhaustive : Applying all 2**n input Applying all 2**n input combinations, generated by binary counters or combinations, generated by binary counters or complete LFSR.complete LFSR.

Pseudoexhaustive : Pseudoexhaustive : Circuit is segmented & Circuit is segmented & each segment is tested exhaustively(Less no. each segment is tested exhaustively(Less no. of tests required):of tests required):

Logical segmentation Logical segmentation : Cone + Sensitized-path: Cone + Sensitized-path Physical segmentation Physical segmentation

4 ) : Test Pattern 4 ) : Test Pattern Generation Techniques Generation Techniques

(Cont.)(Cont.)

Pseudorandom Pseudorandom :: Not all 2**n input Not all 2**n input combinations, Random patterns generated combinations, Random patterns generated deterministically & repeatably, pattern deterministically & repeatably, pattern with/without replacement, applicable to both with/without replacement, applicable to both combinational and sequential circuits.combinational and sequential circuits.

weightedweighted : Non-uniform distribution of 0’s & 1’s, : Non-uniform distribution of 0’s & 1’s, improved fault coverage, using LFSR added with improved fault coverage, using LFSR added with combinational circuits.combinational circuits.

AdaptiveAdaptive : Using intermediate results of fault : Using intermediate results of fault simulation to modify 0’s & 1’s weights, more simulation to modify 0’s & 1’s weights, more efficient,more hard ware complexity.efficient,more hard ware complexity.

5) : Test Response 5) : Test Response compression techniquescompression techniques Response compression :Response compression : A process to form a “signature” from A process to form a “signature” from

complete output responses.complete output responses.– Signature : Signature : Compressed form of saved test results.Compressed form of saved test results.– Alias : Alias : Errorous output when faulty & fault-free sig. are the Errorous output when faulty & fault-free sig. are the

same.same. Compression procedure :Compression procedure : Composition of test vector applying, Composition of test vector applying,

results storing and comparision of the faulty & faultfree signatures.results storing and comparision of the faulty & faultfree signatures. Compression of :Compression of :

– Simple hardware implementation.Simple hardware implementation.– Small performance degradation - No effect on normal circuit Small performance degradation - No effect on normal circuit

behaviour (delay, execution time).behaviour (delay, execution time).– High degree of compression - Signature lenghts to be a High degree of compression - Signature lenghts to be a

logarithmic factor of responses lenghts.logarithmic factor of responses lenghts.– Small aliasing errors.Small aliasing errors.

5) : Test Response 5) : Test Response compression techniques compression techniques

(cont.)(cont.)

Compression problems :Compression problems :– Existing aliasing errors.Existing aliasing errors.– Calculating the good circuit signature.Calculating the good circuit signature.

Calculation of good circuit signatures :Calculation of good circuit signatures :– Golden Unit :Golden Unit : Applying the test to good part of the CUT. Applying the test to good part of the CUT.– Simulation :Simulation : Simulating the CUT and making sure of Simulating the CUT and making sure of

having good signature.having good signature.– Fault Tolerant :Fault Tolerant : Producing copies of CUT and conclude Producing copies of CUT and conclude

the correct signature by finding the subset which the correct signature by finding the subset which generates the same signature.generates the same signature.

5) : Test Response 5) : Test Response compression techniques compression techniques

(cont.)(cont.) One’s count : One’s count : The no. of times when 1 occurs in The no. of times when 1 occurs in

each output (counter).each output (counter). Transition count : Transition count : The no. of transitions(0 The no. of transitions(0

=>1,1=>0) in the output (XOR +counter).=>1,1=>0) in the output (XOR +counter). Parity checking : Parity checking : The parity of response string, 0 The parity of response string, 0

if even & 1 if odd (XOR + D-FF).if even & 1 if odd (XOR + D-FF). Syndrome checking : Syndrome checking : the normalized no. of 1’s the normalized no. of 1’s

inoutput string (k/2**n when k is no. of minterms in inoutput string (k/2**n when k is no. of minterms in an n input circuit), (All possible combination tests).an n input circuit), (All possible combination tests).

Signature analysis : Signature analysis : Based on redundancy Based on redundancy checking (LFSR).checking (LFSR).

6) : Factors affecting the 6) : Factors affecting the choice of BISTchoice of BIST

Degree of test parallelismDegree of test parallelism Fault coverageFault coverage Level of packagingLevel of packaging Test timeTest time Complexity of replaceable unitComplexity of replaceable unit Factory and field test-and-repair strategyFactory and field test-and-repair strategy Performance degradationPerformance degradation Area overheadArea overhead

6-1) : Advantages6-1) : Advantages

Lower cost of testLower cost of test Better fault coverageBetter fault coverage Possibly shorter test timesPossibly shorter test times Tests can be performed Tests can be performed

throughout the operational life of throughout the operational life of the chipthe chip

6-2) : Disadvantages6-2) : Disadvantages

Silicon area overheadSilicon area overhead Access timeAccess time Requires the use of extra pinsRequires the use of extra pins Correctness is not assured Correctness is not assured

7) : BIST key elements7) : BIST key elements

Circuit under test (CUT)Circuit under test (CUT) Test pattern generators (TPG)Test pattern generators (TPG) Output response analyzer (ORA)Output response analyzer (ORA) Distribution system for data Distribution system for data

transmission between TPG, CUT and transmission between TPG, CUT and ORAORA

BIST controllerBIST controller

8) : 8) : Specimen BIST Specimen BIST architecturearchitecture

Chip, Board or SystemChip, Board or System

DIST

CUT

CUT

DIST

ORA

BISTcontroller

TPG

9) : Memory BIST9) : Memory BIST

Memory typesMemory types– SRAM,DRAM,EEPROM,ROMSRAM,DRAM,EEPROM,ROM

Fault modelsFault models– SAF,TF,CF,NPSF,AFSAF,TF,CF,NPSF,AF

Test algorithmsTest algorithms Test categoriesTest categories

9-1) : Fault models9-1) : Fault models

Stuck-At Fault (SAF)Stuck-At Fault (SAF)– The logic value of a cell or a line is always 0 or 1The logic value of a cell or a line is always 0 or 1

Transition Fault (TF)Transition Fault (TF)– A cell or a line that fails to undergo a 0=>1 or a A cell or a line that fails to undergo a 0=>1 or a

1=>0 transition1=>0 transition

Coupling Fault (CF)Coupling Fault (CF)– A write operation to one cell changes the content of A write operation to one cell changes the content of

a second cella second cell

9-1) : Fault models 9-1) : Fault models cont.cont.

Neighborhood Pattern Sensitive Fault (NPSF)Neighborhood Pattern Sensitive Fault (NPSF)– The content of a cell , or the ability to change its content , The content of a cell , or the ability to change its content ,

is influenced by the contents of some other cells in the is influenced by the contents of some other cells in the memorymemory

Address Decoder Fault (AF)Address Decoder Fault (AF)– Any fault that affects address decoderAny fault that affects address decoder

– With a certain address , no cell will be accessedWith a certain address , no cell will be accessed– A certain cell is never accessedA certain cell is never accessed– with a certain address ,multiple cells are accessed with a certain address ,multiple cells are accessed

simultaneouslysimultaneously– A certain cell can be accessed by multiple A certain cell can be accessed by multiple

addresses.addresses.

9-2) : Memory test 9-2) : Memory test algorithmsalgorithms

Traditional testsTraditional tests zero-one,checkerboard,GALPAT,Walking zero-one,checkerboard,GALPAT,Walking

1/0,Sliding Diagonal,Butterfly1/0,Sliding Diagonal,Butterfly

March tests : Tests for stuck-March tests : Tests for stuck-at ,transition and coupling faultsat ,transition and coupling faults

MATS ,Marching1/0 ,March X , ...MATS ,Marching1/0 ,March X , ...

Tests for neighborhood pattern sensitive Tests for neighborhood pattern sensitive faults (NPSF)faults (NPSF)

9-3) : Memory test 9-3) : Memory test categoriescategories

DC : DC : Tests to verify analog parametersTests to verify analog parameters Open/short -Power consumption-leakage,threshold,...Open/short -Power consumption-leakage,threshold,...

AC : AC : Tests to verify timing parametersTests to verify timing parameters Signal rise/fall time, Setup/hold time, Delay, Access Signal rise/fall time, Setup/hold time, Delay, Access

time, . time, .

Dynamic tests : Dynamic tests : Detects dynamic faults Detects dynamic faults affecting CUT(Recovery, refresh line stuck-at, affecting CUT(Recovery, refresh line stuck-at, bit-line precharge voltage imbalance, …)bit-line precharge voltage imbalance, …)

10) : Advanced Topics10) : Advanced Topics

Built-In Self-Repair(BISR).Built-In Self-Repair(BISR). Programmable memory BISTProgrammable memory BIST Generalized Linear Feedback Shift Generalized Linear Feedback Shift

Registers(GLFSR) for pseudo Registers(GLFSR) for pseudo random memory BIST random memory BIST

Transparent BIST for RAMs.Transparent BIST for RAMs. And ....And ....