vlsi

Biyani's Think Tank

Concept based notes

VLSI

(B.Tech)

Monika Kiroriwal

Asst. Professor

Deptt. of Engineering

Biyani International Institute of Engineering and Technology

2

For free study notes log on: www.gurukpo.com

Published by :

Think Tanks

Biyani Group of Colleges

Concept & Copyright :

Biyani Shikshan Samiti

Sector-3, Vidhyadhar Nagar,

Jaipur-302 023 (Rajasthan)

Ph : 0141-2338371, 2338591-95 Fax : 0141-2338007

E-mail : [email protected]

Website :www.gurukpo.com; www.biyanicolleges.org

Edition : 2013

Price :

Leaser Type Setted by :

Biyani College Printing Department

While every effort is taken to avoid errors or omissions in this Publication, any mistake or

omission that may have crept in is not intentional. It may be taken note of that neither the

publisher nor the author will be responsible for any damage or loss of any kind arising to

anyone in any manner on account of such errors and omissions.

VLSI 3


Preface

I am glad to present this book, especially designed to serve the needs of the students. The book has been written keeping in mind the general weakness in understanding the

fundamental concepts of the topics. The book is self-explanatory and adopts the Teach

Yourself style. It is based on question-answer pattern. The language of book is quite easy and

understandable based on scientific approach.

Any further improvement in the contents of the book by making corrections, omission and

inclusion is keen to be achieved based on suggestions from the readers for which the author

shall be obliged.

I acknowledge special thanks to Mr. Rajeev Biyani, Chairman & Dr. Sanjay Biyani, Director

(Acad.) Biyani Group of Colleges, who are the backbones and main concept provider and also

have been constant source of motivation throughout this Endeavour. They played an active role

in coordinating the various stages of this Endeavour and spearheaded the publishing work.

I look forward to receiving valuable suggestions from professors of various educational

institutions, other faculty members and students for improvement of the quality of the book. The

reader may feel free to send in their comments and suggestions to the under mentioned

address.

Note: A feedback form is enclosed along with think tank. Kindly fill the feedback form

and submit it at the time of submitting to books of library, else NOC from

Library will not be given.

Author

4


UNIT 1

Introduction to Mos Technology

Q 1 Introduction to VLSI.

Ans Due to globalization with development of technology things are becoming smaller and

smaller. Every person wants the things, which are portable, light weight, low cost, small

size with good efficiency. In technical field the size of electronic devices or instruments

become small if we compare with the size of conventional devices. Earlier large size of

circuits was the main problem. To solve this problem integrated chip technology was

developed. In this technology there are many levels depend upon the quantity or number

of components which assembled on that particular chip. These levels are SSI (upto 10

gates), MSI ( upto 1000 gates), LSI (upto 10000 gates), VLSI(more than 10000) and so

on. In 1963 Gordon Moore predicted that as a result of continuous miniaturization

transistor count would double every 18 months. 53% compound annual growth rate was

record over 45 years. No other technology has grown so fast so long. Transistors size

become smaller, faster, consumes less power, and is cheaper to manufacture. VLSI stands

for "Very Large Scale Integration". The field in which packing more and more logic

devices into smaller and smaller areas within few millimeters. Many commercial software

are available like Labview, Xilinx, which work for integration technique.

Q2. Fabrication steps for n-well CMOS transistors?

Ans:- CMOS is the combination of PMOS and NMOS transistors. There are many fabrication

techniques to produce the MOS transistor. Here CMOS fabrication technique is described

with diagrams, which illustrate the fabrication procedure step by step.

Step 1:- Initially p-type substrate is taken. This substrate is covered by SIO2 layer, which

can produce using oxidation process.

VLSI 5


Step 2:- To create a n-well in the substrate a mask is made and a photo resist layer is

deposited on the SiO2 layer and mask is placed on the layer and UV light is incident on it

, after that desired n-well area is removed using organic solvent and other is same.

Step 3:-SiO2 layer on n-well is also removed using Hydrofluoric acid. And the remaining

photo resist part is etched using acids.

Step 4:- n-well is formed using n-type impurities, which are injected in the desired n-well

region.

Step 5:- Remaining oxide layer is strip off and a thin layer of oxide is deposited on it and

CVD is used to form polysilicon layer to increase the conductivity of the device.

6


Step 6:- Using photolitho graphic process the gate terminal is made while etching the

remaining part of oxide and polysilicon layer and again covered with oxide layer.

Step 7:- To define the n+ region, which are made in the CMOS transistor, deposited layer

is etched from that particular area and n+ impurities are diffused .

Step 8:- in the continue fabrication steps again strip off the oxide layer and p+ impurities

are implanted in the defined areas.

Step 9:- The constructed chip design is covered with thick oxide layer and etch the part

where the metallization has to be done and a layer of metal is deposited on it and finally

the CMOS n-well transistor is fabricated.

VLSI 7


Fig 1.1 steps of fabrication of MOSFET

So n-well CMOS transistor is made by following these steps and similarly p-well CMOS

also can be created using these steps, but the difference is that there is a diffusion of p-

type impurities in place of n-type impurities to make the well.

Q 3. Explain the working of n-channel enhancement type MOS.

Ans:- To enhance the drain current gate voltage is used. There are two types of enhancement

type MOSFET n-channel and p-channel. It is a four terminals device. The drain and

source terminal has heavily doped regions with diffused impurities. Top on the oxide layer

gate point is connected and body terminal is connected to the defined substrate. A

inversion layer is formed between the drain and source terminal and current flows in

MOSFET due to carriers, gate voltage is used to controlled the characteristics of

MOSFET . Thus it is a voltage controlled device.

Construction:- Silicon material is used to make the p-type substrate. To form the source

and drain n+ impurities are diffused into the desired area. A SiO2 layer is deposited over

substrate. To make contact of source and drain holes are cut in the oxide layer. Gate

terminal is formed on defined area and make metal connection. In enhancement type

MOSFET, no physical channel is there.

8


Fig 1.2 N-channel enhancement MOSFET

Working :- As shown in fig 1.2 drain voltage is applied and free electrons are forced to

move from source to drain but p region doesnt allow it. So there is no current and this

condition is called OFF MOS. When positive voltage is applied at gate then, it repels the

holes away from SiO2 layer and deeply enter into the p-type substrate. Free electrons

which are presented in substrate attracted towards SiO2 layer, and make a region near the

oxide layer which is rich in electrons and deficiency in holes. This process makes a

channel below the gate area and allows the movement of electrons from source to drain.

So there is enhancement of drain current and transistor is in ON condition.

Transfer characteristics:- Characteristics is plotted between gate to source voltage and

drain current .As shown in fig 1.3 the curve shows there is no drain current till VGS is

small then the threshold voltage. When VGS is more than the VT drain current increases

sharply.

VLSI 9


Fig 1.3 Transfer characteristics

Q 4 Explain the construction and working of n-channel depletion type MOSFET.

Ans Silicon material is used to make the p-type substrate. To form the source and drain n+

impurities are diffused into the desired area. A SiO2 layer is deposited over substrate. To

make contact of source and drain holes are cut in the oxide layer. Gate terminal is formed

on defined area and make metal connection. In enhancement type MOSFET, no physical

channel is there.

Fig 1.4 N-channel depletion type MOSFET

10


Working:- As shown in fig 1.4 when positive voltage is applied w.r.t. to source, electrons

which are presented in the source attracted towards drain, and there is a flow of current. If

negative voltage is given to the gate free electrons are repelled and holes of substrate are

attracted, so there is a recombination. This process is going on and electrons presented in

the channel reduce and due to this drain current decreases. Due to applied negative gate

voltage there is a reduction of free electrons, this phenomenon is called depletion and

MOSFET is called depletion type MOSFET.

Transfer characteristics:- As shown in fig1.5 when gate to source voltage is negative

then device works in depletion mode with some current. When negative voltage is

increased then drains current decrease and at defined point of voltage, current is zero.

After that when positive gate voltage is applied then device work in enhancement mode.

Fig 1.5 Transfer characteristics

Q5 Differentiate the p-channel and n-channel FET?

Ans:-

Sr.No. P-Channel N-Channel

1. Majority charge carriers are holes Majority charge carriers are electrons

2. Due to lower mobility of holes, Due to lower mobility of electrons,

VLSI 11


switching speed is slower. switching speed is faster.

3. To obtain higher conductivity, a

large number of holes are required,

it expand the size.

To obtain higher conductivity, a large

number of electrons are required, it

decreases the size.

4. Economical Expensive

5. Premature turn ON is not possible Premature turn ON may be happen

6. Simple structure so easy to

fabricate

Due to complex structure, difficulty to

fabricate.

7. It works on positive gate potential It works on negative gate potential

12


Unit 2

Basic Electrical Properties of Mos Circuits

Q 1. Explain following terms

(i) Accumulation (ii) Depletion Region (iii) Inversion layer

Ans:- Basically MOS transistor is a sandwiched structure, in which substrate layer is the placed

lower and gate layer is the top layer and oxide layer is the middle layer as shown in fig.2.1

Fig2.1 basic MOS structure

Fig 2.2 Charge distribution in Accumulation, depletion region and inversion layer

Accumulation:- Illustrated in fig 2.2, when negative gate voltage is applied then holes

which are presented in the substrate layer attracted towards the electrons and collected

VLSI 13


near the oxide layer. This area is rich in holes and void in electrons, this area is called

accumulation.

Depletion Region:- If no gate voltage is applied at the gate terminal, then there is no

drain current, this state is called flat band. Now small positive voltage is applied at the

gate terminal, which produces electric field. Due to this electric field, a force is implied on

holes and push away from the oxide layer and electrons which are present in substrate are

attracted toward oxide layer. Due to this movement both electron and holes make a layer

below oxide layer called depletion region as shown in fig 2.2.

Inversion layer:- As shown in fig 2.2 when more positive voltage is applied greater than

threshold voltage, then sufficient number of electrons are collated near the oxide layer

under the gate. This layer behaves as a channel and there is a flow of drain current through

induced n+ region. This channel is produced by inverting the substrate surface from p-

type to n-type due to electrons which are collected under the gate area. This induced

channel is also called inversion layer.

Q 2. Explain NMOS transistor produces strong 0 and weak 1, while PMOS transistor

produces strong 1and weak 0.

Ans Gate voltage is applied at gate terminal of NMOS to keep it in ON condition, this time it

behaves like a close switch. When logic 0V is applied at input, 0V is obtained in output

voltage. But when input voltage is high then the output voltage is reduced

This reduction is referred as threshold voltage loss. This reduction is caused by the

minimum value of gate source voltage, which is required to keep transistor in ON state. So

it is proved that a NMOS cannot pass a good 1.

Fig 2.3 NMOS transistor

14


PMOS is the complement of NMOS and to keep it in ON state gate terminal is connected

to the ground. When high logic level is applied at input terminal, then high voltage is

obtained at the output. But low voltage is applied at input then some voltage is obtained at

output, this voltage is there to keep the PMOS device in ON state.

Fig 2.4 PMOS transistor

Q 3. What is channel length modulation?

Ans When very high drain to source voltage is applied, then there is an increment in the

depletion layer width at the drain area. Due to this the channel length is reduced and drain

current is increased. This process is called Channel Length Modulation.

Then channel length is

Due to shorter channel length, drain current increases in saturation region and the relation

between drain current and channel length modulation is given as

Q4. What is noise margin?

Ans Presence of any unwanted signal in the desired signal is called noise which may be

generated by power supply, any component, any radiation or manmade signal also. As it is

known that noise is always is always present around us, and it is essential for all logic

gates that they do not respond to noise signals and introduce logic errors. Ability of a

device to reject the noise is the robustness of the device. Noise margin or noise immunity

is the permitted gate voltage that will not disturb the desired output. There are two

parameter which are used to specify the noise margin depending on logic 0 and logic 1,

named as low noise margin (NML) and high noise margin (NHH).

Where

VLSI 15


Fig 2.6Noise margins

The significance of the noise margins is that the amplitude of the unwanted signal which

is less than NM will not able to change the logic state. When amplitude is greater than the

NM then, in the output there will be confusion about the correct logic state.

The input range between VIL and VIH are called as intermediate region or forbidden region

and both should be close each other to switch transfer characteristics.

Fig 2.7 transfer characteristics

As shown in transfer characteristics the logic levels are at unity gain point (slope=-1).

Typical values of noise margins are

NMl=0.47 VDD

NHH= 0.34 VDD

16


Q 5 Explain body effect.

Ans:- Body effect, it is also called back gate bias. When negative potential is increased on the

substrate with respect to the source, then the depletion region is also increased, due to

large amount of positive charge in the channel. This process increase the gate to source

voltage and in result there is an increment in the threshold voltage. This is the back-gate

bias effect, which has both large and small signal implications.

Fig 2.8NMOS series connection

When n number of NMOS are connected in series. Source of first NMOS is ground and

other sources are connected to drain of previous one. But substrate of all NMOS is

connected to the ground. Lower NMOS device has zero potential difference between

source and body. This voltage is increased in upward direction due to defined connection

and width of the depletion layer is also increased. It behaves like a reverse bias PN

junction and there is a reduction in channel depth. Due to body effect threshold voltage

increases in upward direction. But the gate voltage is same for all NMOS and due to

difference in threshold voltage all NMOS transistor simultaneously cannot ON. So circuit

performance is degrading.

Due to reverse substrate bias voltage VSB, VT also increases in relation ship

Gate to body voltage for p-channel and n-channel device

VLSI 17


Final threshold equation for both channel

Here is the body bias parameter or substrate bias coefficient. Typical value of between

0.4 to 1.2 .

Q 6. What is latch up problem and also explain its prevention?

Ans:- Latch up:- In CMOS Latch up problem caused due to interaction of parasitic pnp and npn

bipolar transistors which create a low-impedance path between the power supply and the

ground. These BJTs are used with positive feedback and virtually short circuit the power

and the ground rail. Due to this excessive current flows and create potential which caused permanent damage to the devices.

Fig 2.9 internal circuit of NMOS

18


As shown in the equivalent circuit has Q1 being a vertical pnp transistor whose base is

formed by the n-well with a high base to collector current gain (1).Q2 is a npn transistor

whose base is formed by the p-type substrate. Rwell is the resistance of n-well structure

whose value ranges from 1KW to 20kW. The substrate resistance Rsub depends on the

substrate structure. Due to large value of Rwell and Rsub resistances results in open

circuit connections, which produce reverse leakage current and low current gains and for

both the npn and pnp transistors. When voltage is applied and there is a increment in the

collector current of one transistor the resulting feedback loop causes the current

perturbation to be multiplied by 1*2.

Fig 2.10 Equivalent circuit

This event turn ON the silicon-controlled rectifier and sufficient voltage drop is

responsible to turn ON the other transistor. When both transistors turn ON simultaneously

then there is a low impedance path between power and the ground rails resulting in latch-

up. For this condition if 1 *2 is greater than or equal to 1, both transistors will remain in

conduction even after the triggering perturbation is no longer available.

Prevention:- Latch up can be prevented by using following technique:

Through Gold doping substrate the minority carrier lifetime can be decreased to reduce the BJT gain. .

p+ and n+ guard band rings can be used around nMOS transistors and pMOS transistors to reduce Rw and Rsub and to capture injected minority carriers before they reach the base of the parasitic

BJT.

Place substrate and well contacts as close as possible to the source connections of the MOS transistors to reduce the values of Rw and Rsub.

Avoid forward biasing of the source/drain junctions so as not to inject high currents, this solution calls for the use of slightly doped epitaxial layer on top of the heavily doped substrate and has the

effect of shunting the lateral currents from the vertical transistor through the low resistance

substrate.

VLSI 19


Q 7 Explain circuit model of MOS transistor.

Ans Circuit model is used to describe the electrical behavior of the device at their connecting

terminals. Fig 2.11 shows the various capacitances of a MOS transistor. During

fabrication of NMOS and PMOS impurities are diffused in the substrate, but these

impurities cannot attained uniform region in the substrate and also cover the area below

gate oxide layer, so capacitance produce between gate to source and drain to gate

capacitance. Due to applied gate voltage, gate to substrate capacitance is formed. When

positive voltage is applied at drain then a reversed bias PN junction is drain to substrate

capacitance is formed. Both source and substrate are at the same potential equal to ground,

no capacitance formed between them is concealing out.

Fig 2.11 Various capacitances of MOS transistor

Fig 2.12 Equivalent small signal model of MOS transistor

When device work in a linear region, then ID increases linearly with VDS, this time channel

act as resistor that gives drain to source resistance rD. Equivalent small signal model of

MOS transistor, which include capacitances of MOS transistor .

20


Unit 3

CMOS Logic Design

Q.1 Draw the CMOS realization of logic design.

F=

Ans. In designing of CMOS logic few rules are here as mentioned:

1. Take the compliment of function 2. Firstly draw the PMOS logic design 3. Draw the NMOS logic design which is compliment of the PMOS logic design 4. Get the final output from the line which connect PMOS and NMOS logic designs

Fig 3.1 CMOS logic design of F

VLSI 21


Q.2 Draw the CMOS logic design of given function

F= (A+B). (B+C)

Ans. In this function we get the following CMOS logic design using the rules of designing.

Fig 3.2 CMOS logic design of Function

Q 3. What is propagation delay and CMOS transistor sizing?

Ans :- When there is a change in the input of any digital circuit, then the corresponding change

obtained at the output with a particular time delay, called propagation delay. This arises

due to two reasons: finite switching time of transistors and the second one is that the

capacitance present between the ground and output node to charge and discharge before

the output reaches the level of VOH or VOL as shown in fig. propagation delay is the

average of the high to- low delays which are measured between the 50 % points of the

input and output waveforms. To reduce the delay transistor sizing is done, in this we have

to decide the W/L ratio. In determining the device sizing, we should find the input

combinations that result in the lowest output current. To determine the capability of a

22


circuit, we need to find out the W/L ratio for MOS device connection like for series and

parallel connections.

When MOSFETs are connected in series then

When MOSFETs are connected in parallel, then

Q 4 What is power dissipation?

Ans: Basically in CMOS circuit power dissipation comes under two categories

1) Static power dissipation 2) Dynamic power dissipation

Factors which create static dissipation

Due to sub-threshold conduction when transistors are OFF

Due to tunneling current

Due to leakage current in reverse biased diodes

Due to contention currents

Factors which create dynamic dissipation

Due to charging and discharging of connected load capacitances

Due to current (short circuit) when NMOS and PMOS both are in ON condition

So, total power dissipation

PTotal = PStatic + PDynamic

Q 5. Draw the CMOS logic circuit for NAND gate and verify its truth table.

Ans: NAND gate is the complement of AND logic gate. It has two inputs and one output. To

realize 2 PMOS and 2 NMOS transistors are used and assemble as shown in fig3.3 and

also the truth table in fig 3.4

VLSI 23


Fig3.3 CMOS NAND logic circuit Fig 3.4Truth table of NAND gate

When both inputs are low, then M1, M2 are ON and M3, M4 are OFF, so the output is high.

When a is low and b is high then M1, M4 are ON and M2, M3 are OFF, so the output is high.

When a is high and b is low then M1, M4 are OFF and M2, M3 are OFF, so the input is high.

When a and b both are high then M1, M2 are OFF and M3, M4 are ON, so the output is low.

Q 6 Draw the CMOS logic circuit for NOR gate and verify its truth table.

Ans: NOR gate is complement of OR gate. Its CMOS logic circuit can be built as shown in

fig3.5 and also the truth table is shown in fig 3.6 using designing rules.

a b Y

(output)

0 0 1

0 1 1

1 0 1

1 1 0

24


Fig 3.5 CMOS NOR logic circuit Fig 3.6 truth table of NOR gate

When both inputs are low, then M1, M2 are ON and M3, M4 are OFF, so the output is high.

When a is low and b is high then M1, M4 are ON and M2, M3 are OFF, so the output is low.

When a is high and b is low then M1, M4 are OFF and M2, M3 are OFF, so the input is low.

When a and b both are high then M1, M2 are OFF and M3, M4 are ON, so the output is low.

Q7 Realize the CMOS SR latch using NAND gate.

Ans: Using 2 input NAND gate a S R latch cab be built as shown in below fig3.7 and fig 3.8

shows its equivalent CMOS logic circuit.

a b Y

(output)

0 0 1

0 1 0

1 0 0

1 1 0

VLSI 25


Fig 3.7 S R latch using NAND gate Fig 3.8 CMOS logic circuit of SR latch

Fig 3.9 Truth table of SR latch

CMOS logic circuit responds when S and R are active low

When S is active low (0), and R is high (1), then Q is high and Q is low and set the latch So, S = 0, then Q= 1

When R is active low (0), and S is high (1), then Q is low and Q is high and reset the latch

So, R=0, then Q = 0

When both inputs are low then both the outputs are high, this result is not permitted in SR latch. This is undetermined state.

When both inputs are high then both the outputs are hold state.

Q8 Realize CMOS SR latch using NOR gate.

Ans: Two inputs NOR gates are used to design a SR latch in fig 3.10, and to design a CMOS S

R latch, two CMOS NOR logic circuits are connected as shown in fig3.11

26


Fig 3.10 SR latch using NOR gate Fig3.11 CMOS SR latch Using NOR gate

Fig. 3.12 Truth table for SR latch

When S is high (1), M1 is turned ON, then Q is low and Q goes high

When R is high (1), M 4 is turned ON, then Q is high and Q goes low

When both S and R are low (0), then M1 and M4 are OFF, then latch hold its existing state.

When both S and R are high (1), then both Q and Q are low which is undefined state. So it is not allowed.

VLSI 27


Unit 4

Basic Physical Design and Layout Issues

Q1. Explain layout design rule.

Ans: A set of geometric constraints or rules which are used to manufactured the physical mask

layout of any circuit, these are generally called layout design rules. The main objective of

design rules is to achieve, a particular process, which maintains a high overall yield and

reliability while using the smallest possible silicon area.

Design rules can be used in two ways

(i) Micron rules, in whi

ch the layout constraints such as minimum feature sizes and minimum allowable feature

separations are stated in terms of absolute dimensions in micrometers, or,

(ii) Lambda rules, which specify the layout constraints in terms of a single parameter ( ) and

thus allow linear, proportional scaling of all geometrical constraints.

Rule number Description -Rule

Active area rules

R1 Minimum active area width 3 R2 Minimum active area spacing 3 Polysilicon rules

R3 Minimum poly width 2 R4 Minimum poly spacing 2 R5 Minimum gate extension of poly over active 2 R6 Minimum poly-active edge spacing 1 (poly outside active area)

R7 Minimum poly-active edge spacing 3 (poly inside active area)

Metal rules

R8 Minimum metal width 3 R9 Minimum metal spacing 3

Contact rules

R10 Poly contact size 2 R11 Minimum poly contact spacing 2 R12 Minimum poly contact to poly edge spacing 1 R13 Minimum poly contact to metal edge spacing 1 R14 Minimum poly contact to active edge spacing 3 R15 Active contact size

R16 Minimum active contact spacing 2 (on the same active region)

28


R17 Minimum active contact to active edge spacing 1 R18 Minimum active contact to metal edge spacing 1 R19 Minimum active contact to poly edge spacing 3 R20 Minimum active contact spacing 6 (on different active regions)

Fig 4.1 shown the layout of a particular circuit with rule number, which intimates the

dimension of each diffused material in the circuit components in lambda.

Fig 4.1 Illustration of layout design rule for circuit

Q 2 Explain the design rule for any circuit layout taking an example of CMOS invertor.

Ans As it is known that the CMOS inverter circuit consists of PMOS and NMOS transistors.

Each transistor is created according to the design rule. In designing our main goal is to

create minimum size transistor. Using minimum diffusion contact size the width of the

active area is then determined and the minimum separation from diffusion contact to both

active area edges. The width of the poly-silicon line is typically taken as the minimum

poly width as shown in fig 4.2 .

VLSI 29


Fig.4.2 Design rule constraints which determine the dimensions of a minimum-size transistor

Then, the overall length of the active area can be determined using this formula

L= minimum poly width + 2 x minimum poly-to - contact spacing + 2 x minimum

spacing from contact to active area edge.

The PMOS transistor is placed in an n-well region. The minimum separation between the

n+ active area and the n-well, distance between the NMOS and the PMOS transistor can

be determined. The poly-silicon gates of the NMOS and the PMOS transistors are usually

aligned as shown in fig .

During finalization metal connections are made for input, output, ground and VDD. Finally

the complete layout of CMOS inverter is obtained as shown in fig 4.3 (a) and 4.3 (b)

30


Fig 4.3(a) Placement of one NMOS and one PMOS transistor, and (b) Complete mask layout of

the

CMOS inverter

Q 3 Design a layout for NAND and NOR gate.

Ans Here we consider a two inputs NAND gate. While designing layout 4 transistors are

required. Firstly we design a CMOS NAND logic circuit then using lambda design rule

we create layout of NAND gate as shown in fig4.4 .

In this circuit layout colors are assigned to the layers as written below

Colors of layers

polysilicon (gates) : Red

Doped n+/p+ (active) : Green

N-Well : Yellow

Metal 1: BLUE

Metal 2 : Grey

Contacts: Black Xs

Using these colored layers layout of NAND gate is made followed by CMOS NAND

logic circuit.

VLSI 31


Fig 4.4 NAND layout

Similarly for NOR gate firstly CMOS logic circuit is designed using this circuit NOR

layout is created as shown in fig 4.5.

Fig 4.5 NOR layout

32


Q 4 What is Eular rule and design a stick layout for given function using Eular rule:

F =

Ans To determine common path in CMOS logic circuit Euler Graph Technique can be used.

Using this path easily layout can be designed with minimum connection among all the

circuit elememts. Start with either NMOS or PMOS tree and circuit components are

replaced by connecting lines like transistor segments, labeling devices, and circuit nodes.

By using the Euler path technique polysilicon lines are rearranged to get optimum layout.

Find a Euler path in both the pull-down tree graph and the pull-up tree graph with

identical ordering of the inputs.

Fig 4.6 (a) CMOS circuit (b) Euler path of NMOS and CMOS circuit

Fig 4.7 Stick layout diagram

VLSI 33


As shown in fig 4.7, a stick layout is made by using the order of NMOS and PMOS inputs

which are common for both and reduce the size and complexity of the conventional

layout.

Q 5 Draw the layout of following equation:

Ans As shown in fig 4.8 firstly CMOS circuit is designed and then euler path is created to

obtain a common path to reduce the size of the layout.

Fig 4.8 (a) CMOS logic circuit (b) Euler path for NMOS and PMOS circuit

Fig 4.9 Circuit layout of equation

Fig 4.9 shows the circuit layout of given equation , it is created by using circuit layout

lambda rules.

34


Q6 Explain the layout optimization and performance.

Ans : There are basic three components which are used to built layout: transistors, wires and

vias. Integrated chip designing the design rules determine the low level properties:

How we can design small logic gates

To reduce the delay, small joining wires connecting gates can be made.

Some fabrication errors are also introduced, which should be minimized as:

1. A wire or other feature made too wide or too narrow, can create fabrication problem and reasons may be;

(i) Error due to photolithographic (ii) Local materials

2. Planarization problem: (i) Due to deposition of metal wire in oxide area (ii) This over metal area is smoothened by chemical methods and due to this process

sometime lead breaks in layers.

3. If wider wires are used, then it may get shorted and narrow wires may burn out, so no current at all.

(i) Due to minimum width rules give a minimum size (ii) Minimum distance between layout components.

For the optimum layout design, designer should design the components in lambda, the size

of the smallest feature in a layout. By choosing value for lambda, set the dimension of

layout. Layout editor, Design rule checkers (DRC), Circuit extractors are layout design

and analysis tools, which are used to design and simulate the CMOS circuits.

VLSI 35


Unit 5

Introduction To VHDL

Q1 What is VHDL and write down its features?

Ans VHDL, stands for very high speed integrated circuit hardware language, which was

developed in 1980s. VHDL can be defined as follows

It is a programming language that is designed and optimized for digital circuit design and

modeling. This language is used to describe the physical, structural and behavioral

characteristics of digital systems at multiple level of abstraction.

The language that allows to validating the design of a device prior to fabrication.

Language which provides a range of features, that support the simulation of digital

circuits.

VHDL allows you to specify:

The components of a circuit. Their interconnection. The behavior of the components in terms of their input and output signals.

Features of VHDL Model:

Sub-components and their interconnections are described in the design as components.

It contains dataflow description of circuit and concurrent statements execute when data is

available on their inputs.

Functional and possibly timing characteristic are described in behavioral description using

VHDL concurrent statements and processes. The process execute sequentially until it gets

suspended by a wait statement.

Packages is the combination of common declaration, constants, and/or subprograms to

entities and architectures.

Generics is used to communicate information from the external environment to the

designer.

36


Ports are used for a device to communicate with its environment. A port declaration

defines the names, types directions and possible default values for the signals in a

components interface.

Configuration is an instruction used to bind the component instances to design entities

Group of signal called bus, used for communication.

Driver is a source which provides values to be applied to the signal.

Attribute is a VHDL objects additional information.

Q 2 Write a VHDL code for 4X1 MUX.

Ans Library IEEE;

Use IEEE.std_logic_1164.all;

Entity MUX is

Port (X0, X1, X2, X3: in std_logic;

S: in std_logic_vector(1 down to 0)

F: out std_logic);

End MUX;

Architecture behavior of MUX is

Begin

PROCESS (S, X0, X1, X2, X3)

Begin

Case S is

When 0=> ff f f

VLSI 37


entity piso is

port(

clk, d1, load:in std_logic;

din:in std_logic_vector(7 down to 0)

dout: out std_logic

);

end piso;

architecture piso_arch of piso is

signal reg:std_logic_vector (7 down to 0);

begin

process (clk)

begin

If clk 1 and clk event then

If load = 1then

reg

38


Q 4 Write VHDL code for up/down counter?

Ans :-

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity updown is

port(

clk, rst:in std_logic;

enable, updown:in std_logic;

count: inout std_logic_vector (4 down to 0)

);

end updown;

architecture updown_arch of updown is

begin

process (clk)

begin

If (clk 1 and clk event) then

If rst = 1then

cout

VLSI 39


end if;

end if;

end if;

end process;

end updown_arch;

Q 5. Write a VHDL program for half adder?

Ans:-

library IEEE;

use IEEE.std_logic_1164.all;

entity half is

port (

a,b:instd_logic;

sum, carry:out std_logic;

);

end half;

architecture half_arch of half is

begin

sum

40


Multiple Choice Questions

Q 1. For an n-channel JFET with a constant drain-source voltage, if the gate-source voltage is

increased (more negative) pinch-off would occur for:

(a) High values of drain current

(b) Saturation value of drain current

(c) Zero drain current

(d) Gate current equal to drain current

Q 2. For a junction FET in the pinch-off region as the drain voltage is increased the drain

current:

(a) Becomes zero

(b) Abruptly decreases

(c) Abruptly increases

(d) Remains constant

Q 3:- In modern the MOSFET, the material used for the gate is:

(a) High-purity silicon

(b) High-purity silica

(c) Heavily doped polycrystalline silicon

(d) Epitaxial grown silicon

Q 4:- The threshold voltage of an n-channel MOSFET can be increased by:

(a) Increasing the channel dopant concentration

(b) Reducing the channel dopant concentration

(c) Reducing the gate oxide thickness

(d) Reducing the channel length

Q 5:- CMOS is formed by the

(a) Twin tub

(b) CZ method

(c) LPE method

(d) None of the above

Q 6:- Input impedance of MOSSFET is

(a) less than of FET but more than BJT

(b) more than that of FET and BJT

(c) more than that of FET but less than BJT

(d) less than that of FET and BJT

VLSI 41


Q7:- MOSFET uses the electric field of

(a) gate capacitance to control the channel current

(b) barrier potential of p-n junction to control the channel current

(c) both a and b

(d) none of these

Q 8:- In MOSFET devices the N-channel type is better the P-channel type in the following

respects

(a) it has better noise immunity

(b) it is faster

(c) it is TTL compatible

(d) it has better drive capability

Q 9:- In a MOSFET, the polarity of the inversion layer is the same as that of the

(a) charge on the gate electrode

(b) minority carriers in the drain

(c) majority carries in the substrate

(d) majority carries in the source

Q 10:- A depletion MOSFET differs from a JFET in the sense that it has no

(a) channel

(b) gate

(c) P-N junction

(d) Substrate

Q 11:- A D-MOSFET can operate in the

(a) Depletion-mode only

(b) Enhancement-mode only

(c) Depletion-mode or enhancement-mode

(d) Low-impedance

Q 12:- CMOS devices use

(a) Bipolar transistors

(b) Complementary E-MOSFETs

(c) Class A operation

(d) DMOS devices

Q 13:- The main advantage of CMOS is its

(a) High power rating

42


(b) Small-signal operation

(c) Switching capability

(d) Low power consumption

Q 14 :- Which of the following effects can be caused by a rise in temperature

(a) Increase in MOSFET current (IDS)

(b) Increase in BJT current (IC)

(c) Decrease in MOSFET current (IDS)

(d) Decrease in BJT current (IC)

Q 15:- . In an E only MOSFET, drain current starts only when VGS (th) is

(a) positive

(b) negative

(c) zero

(d) greater than VGS (th)

Q 16:- When not in use, MOSFET pins are kept at the same potential through the use of

(a) shipping foil (b) nonconductive foam (c) conductive foam (d) a wrist strap

Q 17:- A "U" shaped, opposite-polarity material built near a JFET-channel center is called the

(a) gate (b) block (c) drain (d) heat sink

Q 18 :- Which JFET configuration would connect a high-resistance signal source to a low-

resistance load?

(a) Source follower (b) Common gate (c) Common source (d) Common drain

Q 19:- When applied input voltage varies the resistance of a channel, the result is called

(a) Saturization (b) Polarization (c) Cut off (d) Field effect

Q 20:- Which of the following ratings appear(s) in the specification sheet for an FET?

VLSI 43


(a) Voltages between specific terminals (b) Current level (c) Power dissipation (d) All of above

vlsi

Documents