voltage mode control of buck converter

A

PROJECT REPORT ON

“VOLTAGE MODE CONTROL OF BUCK CONVERTER”

PROJECT ASSOCIATES

Anusha A. N Arpan Chatterjee

(4NM09EE008) (4NM09EE009)

Ashutosh Kumar Manish Kumar

(4NM09EE010) (4NM09EE031)

Under the guidance of

Mr. Suryanarayana K.

Assistant Professor, Dept. of Electrical and Electronics Engineering

NMAMIT, Nitte

Project Report submitted to NMAM Institute of Technology, Nitte An Autonomous Institution affiliated to VTU Belgaum, in partial fulfilment for the award

of Bachelor of engineering in Electrical and Electronics Engineering

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

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NMAM INSTITUTE OF TECHNOLOGY

(An Autonomous Institution affiliated to VTU, Belgaum) (NBA Accredited, ISO 9001:2008 Certified)

Nitte – 574110, Karkala, Udupi District, Karnataka, India

Department of Electrical and Electronics Engineering

CERTIFICATE

Certified that the project work entitled Voltage Mode Control of Buck Converter is a bonafide

work carried out by Anusha A.N (4NM09EE008), Arpan Chatterjee (4NM09EE009),

Ashutosh Kumar (4NM09EE010) and Manish Kumar (4NM09EE031) in partial fulfillment

for the award of Degree of Bachelor of Engineering in Electrical and Electronics Engineering

of the Visvesvaraya Technological University, Belgaum during the year 2012-2013. It is

certified that all corrections / suggestions indicated for Internal Assessment have been

incorporated in the report deposited in the departmental library. The project report has been

approved as it satisfies the academic requirements in respect of project work prescribed for the

Bachelor of Engineering Degree.

Signature of Guide Signature of HOD Signature of Principal

Semester End Viva Voce Examination

Name of the Examiners Signature with Date

1. _______________________________ ________________________________

2. _______________________________ ________________________________

i

ABSTRACT

The objective of this project is to design and develop a buck converter circuit using

PID Compensator to get a stable output of 5V, 5A from an input of 12V.

The Buck-converter converts an input voltage into a lower output voltage, it is also

called step-down converter. The buck converter is designed in continuous current

conduction mode. To get the regulated output voltage, compensation mechanism

using voltage mode control is used. This project involves simulation, design and

hardware construction of voltage mode control of buck converter using PID

compensator. The simulation of the circuit is done using Orcade (PSpice). MATLab

is used to study stability analysis of the closed loop system and to get the desired

phase and gain margin. The PID compensator is designed by modifying the open

loop buck converter circuit obtained from the simulation in Orcade (PSpice). The

error signal is compared with a saw-tooth ramp voltage and desired PWM signal.

The compensator and PWM scheme is implemented using NXP LPC1768.

ii

ACKNOWLEDGEMENT

We would like to take the opportunity to appreciate the help and support rendered to

us by Mr. Suryanarayana K., Assistant Professor, Dept. of E&E in completing this

project successfully under his guidance and for helping us procure some of the

components required for this project.

We also thank Mr. Pradeep Kumar, Assistant Professor, Dept. of E&E, for his

valuable suggestions and help rendered to us.

We are grateful to our principal Dr. Niranjan N. Chiplunkar and Prof. K. Vasudev

Shettigar, HOD, Dept. of E&E for extending encouragement and providing adequate

facilities in carrying out this project.

We are grateful to all the teaching and non-teaching staff of the Dept. of E&E, and

friends who have helped us through the course of this project.

Nitte

April 2013

PROJECT ASSOCIATES:

Anusha A.N (4NM09EE008)

Arpan Chatterjee (4NM09EE009)

Ashutosh Kumar (4NM09EE010)

Manish Kumar (4NM09EE031)

iii

TABLE OF CONTENTS

CHAPTERS TITLE PAGE NO.

ABSTRACT i

ACKNOWLEDGEMENT ii

TABLE OF CONTENTS iii

LIST OF FIGURES v

LIST OF TABLES vii

1 INTRODUCTION 1

1.1 Project Background 1

1.2 Project Objective 3

1.3 Project Scope 3

2 BUCK CONVERTER DESIGN AND OPERATION 5

2.1 Operation of Buck Converter 5

2.2 Calculation of L and C 8

2.3 Converter Power Stage Calculation 9

2.3.1 Calculation of Unknown Parameters 10

2.3.2 Calculation for Inductance 10

2.3.3 Calculation for Capacitance 11

2.3.4 Buck Converter Diode Selection 11

2.3.5 Buck Converter MOSFET Selection 11

2.3.6 Buck Converter Efficiency 12

3 COMPENSATOR DESIGN AND TRANSFER FUNCTION 13

3.1 Introduction 13

3.2 Buck Converter in Voltage Mode Control 14

4 HARDWARE DESIGN AND SIMULATION 24

4.1 Pulse Width Modulation 24

4.2 Buck Converter Simulations 24

4.3 NXP LPC1768 Microcontrollers 32

iv

4.3.1 Overview 32

4.3.2 Features 33

4.3.3 Tools and Software 33

4.3.4 Technical References 34

4.3.5 Hardware Overview 35

4.3.6 Major Functional Block 36

4.3.7 Memory 36

4.3.8 Implementation 37

5 CONCLUSION AND FUTURE PROSPECTS 38

5.1 Conclusion 38

5.2 Future Prospects 38

REFERENCES 39

APPENDIX- DATA SHEETS 40

v

LIST OF FIGURES

FIGURE NO. TITLE PAGE NO.

1.1 Basic Buck Converter 1

1.2 Voltage Mode Control 2

2.1 Buck Converter 5

2.2 When switch is closed 5

2.3 When switch is open 5

2.4 Voltage and current

waveform of buck

converter

6

3.1 Voltage mode control of

buck converter

14

3.2 Block diagram of Buck

converter

14

3.3 Type III Compensator 17

3.4 open loop control to

output transfer function

19

3.5 bode diagram 20

3.6 bode diagram 20

3.7 bode diagram 21

3.8 closed loop bode

diagram

21

3.9 Output impedance bode

diagram

22

3.10 Closed loop bode

diagram

22

4.1 PWM Control 23

4.2 Simulation of open loop

buck converter in PSpice

24

4.3 Inductor Current and

Output Voltage Waveform

24

4.4 Inductor Current 25

vi

Waveform

4.5 Output Voltage Waveform 25

4.6 Inductor Current

Waveform after Zoom area

25

4.7 Output Current Waveform 25

4.8 Inductor Voltage

Waveform

26

4.9 Gate Pulse for the

MOSFET

26

4.10 Voltage across Diode 26

4.11 Current across Diode 27

4.12 Output Power Waveform 27

4.3.1 NXP LPC1768 28

4.3.2 Block Diagram of NXP

LPC1768

31

4.3.3 Pin Diagram of NXP

LPC1768

32

vii

LIST OF TABLES

TABLE NO. TITLE PAGE

1.1 DESIGN SPECIFICATION

OF BUCK CONVERTER

4

2.1 INDUCTOR AND

CAPACITOR VALUE

(CALCULATED)

11

2.2 ESTIMATED SYSTEM

LOSS

12

3.1 COMPENSATION

COMPONENTS VALUE

19

VOLTAGE MODE CONTROL OF BUCK CONVERTER

Department of Electrical & Electronics Engineering, NMAMIT, NITTE 1

CHAPTER 1: INTRODUCTION

This chapter describes the project background, objectives, and the scope. In the

project background, a brief description of the buck converter and the voltage-mode

controller as well as the objective and the scope of the project are studied.

1.1 Project Background

Direct current to direct current (DC-DC) converters in power electronics circuits are

those which convert direct current (DC) voltage input from one level to another. DC-

DC converters are also known as switching converters, switching power supplies or

switches. DC-DC converters are important in portable devices such as cellular

phones and laptops [1].

Figure 1.1: Basic Buck Converter

The Figure shows a simple buck converter which accepts a dc input and uses pulse-

width modulation (PWM) of switching frequency to control the output of a power

MOSFET. A diode together with an inductor and a capacitor produces the regulated

dc output. Buck or step down converters produce an average output voltage lower

than the input source voltage.

The buck converter is the most widely used dc-dc converter topology in power

management and microprocessor voltage-regulator (VRM) applications. These

applications require fast load and line transient responses and high efficiency over a

wide range of load current. They can convert a voltage source into a lower regulated

voltage source. For example within a computer system, voltage needs to be stepped



down and a lower voltage needs to be maintained. For this purpose the Buck

Converter can be used. Furthermore buck converters provide longer battery life for

mobile systems that spend most of their time in “stand-by”. Buck regulators are often

used as switch-mode power supplies for baseband digital core and the RF power

amplifier.

Suppose we want to use a device with low voltage level and if devices such as

laptop or charger is directly connected to the rectified supplied from the socket at

home, the device might not function properly or it might be broken due to over

current or overvoltage. Therefore to avoid unnecessary damage to the equipment’s

and devices, we would need to convert the voltage level to suitable voltage level for

the equipment’s to function properly. In this project, the configuration of DC-DC

converter chosen for study was buck configuration. Buck converter converts the DC

supply voltage to a lower DC output voltage level. The buck converter targeted is

suitable for low power application due to the low voltage and current level at the

output (25 watts).

Figure 1.2: Voltage Mode Control

The control method chosen to maintain the output voltage from the buck converter is

voltage-mode control and is shown in figure 1.2. Voltage mode has a single voltage

feedback path with pulse width modulation performed by comparing the voltage error

signal with a constant ramp waveform. The difference between both the voltages will

drive the control element to adjust the output voltage to a desired voltage level. This

is called as output voltage regulation. Voltage regulation is very important in

electronic circuit to ensure that the load or the connected device can operate

properly and to avoid damage to the equipment from overvoltage and over current.



1.2 Project Objective

The main objective of this project is to design a buck converter to convert the input

DC voltage to lower DC output voltage level for low power applications to solve the

problem of voltage regulation and high power loss of the linear regulator circuit.

Basically we design a buck converter circuit using PID Controller to get a stable

output of 5V, 5A from an input of 12V. The converter uses switching scheme which

operates the switches such as MOSFET in cut-off and saturation region to reduce

power loss across the MOSFET. The output voltage level is then regulated by the

voltage-mode control circuit to a desired output voltage level as shown in the design

specification in the table 1.1 below. The design specification is based on low power

applications such as laptop battery charger, hand phone charger etc. The circuit is

simulated by using PSpice software to obtain the desired power stage response.

1.3 Project Scope

The scope of this project is:

I. Study the operation of buck converter.

II. Study the operation of voltage-mode control circuit.

III. Simulation of buck converter frequency response using PSpice software.

IV. Designing the buck converter power stage circuit.

V. Designing the controller and compensator circuit.

VI. Testing and calibration of the completed buck converter to confirm the actual

response with the theoretical predictions.



Table 1.1: Design specification of buck converter power stage

Topology Buck Converter

Inductance (L) 100 µF

Frequency ( ) 10 kHz

Critical inductance ( ) 49.64 μH

Output voltage ( ) 5 V

Output current ( ) 5 A

Output voltage ripple (∆V) 45 mV

Output current ripple (∆I) 1.5 A

Equivalent series resistance (ESR)

DC input voltage (Vin) 12 V

Switch selection IRF520 metal-oxide-semiconductor field-

effect transistor (MOSFET)



CHAPTER 2: BUCK CONVERTER OPERATION AND

DESIGN

2.1 Operation of Buck Converter

The operation of the buck converter is simple, with an inductor and two switches

(usually a MOSFET and a diode) that control the inductor. It alternates between

connecting the inductor to source voltage to store energy in the inductor and

discharging the inductor into the load.

Figure 2.1: Buck Converter

Figure 2.1 shows the circuit diagram of a Buck-converter. The MOSFET M1 operates

as the switch, which is turned on and off by a pulse width modulated (PWM) control

voltage VPWM. The ratio of the on time (ton) when the switch is closed to the entire

switching period (Tsw) is defined as the duty cycle ⁄ .

................................................................. (2.1)

Figure 2.2: When the switch is closed Figure 2.3: When the switch is open



The equivalent circuit in Figure 2.2 is valid when the switch is closed. The diode is

reverse biased, and the input voltage supplies energy to the inductor, capacitor and

the load. When the switch is open as shown in Figure 2.3 the diode conducts and the

capacitor supplies energy to the load, and the inductor current flows through the

capacitor and the diode. The output voltage is controlled by varying the duty cycle. In

steady state, the ratio of output voltage to the input voltage is “D”, given by Vout/ Vin.

Vcont

Tsw

ton t

V1

Vout=V1

t

VL

(Vin-Vout)

-Vout t

IL

ILmax ∆IL

ILoad=IL

ILmin t

Figure 2.4: Voltages and Currents Waveform of the Buck Converter



In the figure 2.4 the analysis is assumed that the conducting voltage drop of the

MOSFET and the diode is zero. During the on-time of the MOSFET voltage V1 is

equal to Vin. When the transistor switches off (blocking phase), the inductor L

continues to drive the current through the load in parallel with C and the diode,

consequently the voltage V1 becomes zero. The voltage V1 stays at zero during the

off-time of the transistor provided that the current IL does not reduce to zero. This

mode of operation is called continuous mode. In this mode V1 is a voltage which

changes between Vin and zero, corresponding to the duty cycle of Vcont.

The low-pass filter formed by L and C, produces an average value of V1 i.e. Vout =

V1, therefore for continuous mode

............................................ (2.2)

For the continuous mode the output voltage is a function of the duty cycle and the

input voltage, and it is independent of the load. The inductor current IL has triangular

shape and its average value is determined by the load. The peak-to-peak current

ripple ∆IL is dependent on L and can be calculated as:

V = Ldi/dt → ∆i = V∆t/L → ∆IL = (Vin-Vout)ton/L = Vout(Tsw-ton)/L

For

and a switching frequency Fsw, it follows that for the continuous

mode:

The current ripple ∆IL is independent of the load.

The average of the current IL is equal to the output current Iout.

At low load current, in case that the current IL becomes zero in every

switching cycle. This mode is called discontinuous mode and for this mode, these

calculations are not valid.



2.2 Calculation of L and C:

To ensure the continuous current mode of conduction, the selected value of

inductance should be greater than the critical value of the inductor Lc which acts as a

boundary condition for continuous and discontinuous current mode of operations.

The critical value of inductance is given by,

( )

........................................ (2.3)

The inductor value must be chosen by considering the fact that the magnitude of the

ripple current in the output capacitor as well as the load current is determined by the

appropriate inductor value. Hence, normally a ripple current of 10% to 20% of the

average output current is assumed for the design to achieve good performance of

the converter [7]. The value of inductor is determined by,

( ) ( ⁄ ) ............................ (2.4)

The capacitor value is determined by assuming the output voltage ripple as 1% to

2% of the output voltage. The capacitor value is determined by,

........................................................................ (2.5)

To calculate the value of L , a realistic value of ∆IL has to be selected.

If ∆IL is selected at a very low value, the value of L has to be relatively high and this

would require a very heavy and expensive inductor. If ∆IL is selected at a very high

level, the switch-off current of the MOSFET would be very high which would result in

high losses in the MOSFET. A good and usual compromise between these effects is:

............................................................ (2.6)

For L it follows:

( ) ( ⁄ ) ( ⁄ ).............................. (2.7)

The maximum value of the inductor current is:

.................................................. (2.8)



Assuming that the inductor ripple current is small compared to its dc current the RMS

value of the current flowing through the inductor is given by:

√

........................................................ (2.9)

The capacitor C is chosen usually for a cut-off frequency of the LC-low-pass filter,

which is approximately 100 to 1000 times lower than the switching frequency. An

exact calculation of the capacitor depends on its maximum rating of the AC current

and its equivalent series resistance ESR both can be verified from the relevant data

sheet. The current ripple ∆IL causes a voltage ripple ∆Vat the output capacitor C. For

normal switching frequencies, this voltage ripple is determined by the equivalent

series resistance ESR.

The output voltage ripple is given by:

....................................................................... (2.10)

2.3 Converter Power Stage Calculation

For a Buck converter, we will calculate the required inductor and output capacitor

specifications. We will then determine the input capacitor, diode, and MOSFET

characteristics. With the selected components, we will calculate the system

efficiency.

The conventional buck converters are designed for the following specifications:

Input Voltage, V

Output Voltage,

Load Current,

Switching Frequency,



2.3.1 Calculations of Unknown Parameters

Output resistance,

=5/5= 1Ohms

Using equation (2.2), Duty Ratio, D =0.416

Peak-Peak ripple current is limited to 30% of load current,

Using equation (2.6),

Switching period, ⁄ =100μs

Switch ON time, ton=D/Fsw= 0.416/10k= 41.6μs

2.3.2 Calculation for Inductance

Critical value of inductor:

Using equation (2.3), μH

Inductor value (30% ripple current)

Using equation (2.7), L=194μH

Let us choose value of inductor= 100μH

Inductor peak current (30% ripple current):


Inductor RMS current:


The power dissipated due to copper losses is:

0.75 Watt



2.3.3 Calculation for Capacitance

Using equation (2.10), Ripple voltage ΔV= 45mV

Using equation (2.5), Capacitance C = 417μF

Let us choose value of capacitor as 470μF.

The estimated power dissipation in the capacitor is:

Table 2.1: Inductor and Capacitor Value (calculated)

2.3.4 Buck Converter Diode Selection

Estimate Diode Current:

( )

Power Dissipation: VF·ID = 1.168 Watt

We have selected schottky diode 1N5826 of 15A, 20-40 volts. Forward voltage drop

for selected diode is 0.47V at peak current of 15A. Maximum diode reverse voltage

is 20V.

2.3.5 Buck Converter MOSFET Selection

( )

( ⁄ ) ( ) (

) = 0.717 Watt

= 0.925 Watt



2.3.6 Buck Converter Efficiency

Output Power =25 Watt

Efficiency = 25/(25+2.9105) = 89.57 %

Table 2.2: Estimated System Loss

Components Value Units

Output power 25 Watt

MOSFET loss 0.925 Watt

Diode loss 1.168 Watt

Inductor loss 0.75 Watt

Capacitor loss 0.0675 Watt

Total loss 2.9105 Watt

Efficiency 89.57 %

This Buck converter design example has a calculated efficiency of 89.57%.If the

diode forward voltage drop could be lowered, the converter’s efficiency could be

raised. This buck converter design example is called an Asynchronous Buck

converter because the diode commutation (switching) is independent of the

MOSFET switching.



CHAPTER 3: COMPENSATOR DESIGN AND TRANSFER

FUNCTION

3.1 Introduction

The easiest way to obtain a digital controller is first to design an analog compensator

and transpose it in the digital domain using the bilinear transformation. The

disadvantages of such a method are the mathematical calculus needed to obtain the

values of the passive components for the compensator and the fact that if the

designer decides to change the hardware, the calculus must be reevaluated.

In this chapter, a type III analog controller with its time domain transfer function and

frequency response is given. The analog compensator was designed without any

adjustments only by placing the position of the poles and zeros by a first

approximation based on the buck converters passive components. The type III digital

controller is obtained from the transfer function of an analog type III controller

transposed into digital domain using the bilinear transformation.

After mathematical calculations, the z-coefficients for the linear difference equation

needed to implement the compensator in a microcontroller are obtained. These

coefficients are dependent only on the pole-zero placements. The pole-zero

placements are obtained from calculation similar to the analog design using only the

given values of the converter parameters.

The advantage of this digital compensator is that the user does not need to calculate

anything if he wants to close the loop for a converter, the only data needed to be

transferred to the controller are the parameters of the converter. The control mode

used in this project is voltage mode control. The models are first simulated and the

results are compared and then the experimental results are presented.



3.2 Buck Converter in Analog Voltage Mode Control

Figure 3.1: Voltage mode control of buck converter

In figure 3.1, a buck converter in voltage mode control is given. In voltage mode

control an external signal is compared with the control signal obtained for generating

the duty cycle needed to have the wanted output voltage. The output voltage Vout is

monitored and subtracted from the reference value Vref and an error signal Vcomp

results. This error signal is then used for the resulting control signal. The control

signal is then compared with the external ramp voltage Vramp and a pulse width

modulated signal is sent to the drivers of the MOSFET so that converter can react in

such a way so as to reduce the output error [2], [3], [4], [5].

Figure 3.2: Block diagram of buck converter



The transfer function of power stage can be calculated as ratio of the output voltage

to duty cycle and given as:

( ) ( )

( )…………………………………………………………..… (3.1)

( ) ( )

( ) [ ( ) ] ( )

…… (3.2)

The “(s)” indicates that the transfer function varies as a function of the frequency.

The transfer function of the PWM modulator is ⁄ , where is the peak to

peak voltage of modulator. For simplification, we can combine the transfer function of

the PWM modulator and the buck converter power stage as:

( ) ( )

…………………………………... (3.3)

Therefore, G(s) is usually referred to as the transfer function of the power stage. The

roots of the polynomial in the denominator of (3.2) are called the poles of the transfer

function of the power stage. Similarly the roots of the numerator of (3.2) are the

zeros of the transfer function of the power stage. The transfer function of the power

stage is a second order system with a double pole at the resonance frequency (of

the LC filter) and a zero produced by the ESR of the capacitor.

Line to output transfer function is given as:

( )

( )

………...……………. (3.4)

Open loop transfer function:

( ) (

)(

)(

)

(

)(

)(

)

….… (3.5)

The pole located at cancels the zero located at FESR and the pole at Fp2 is located

well above crossover frequency.

Output impedance is given as:

( ) ( )

( )............................................................... (3.6)



The parameter ⁄ is the inductor zero frequency and ( ) .

Closed loop output impedance is given as:

( ) ( )

( )....................................................................... (3.7)

The closed loop line to output TF:

( ) ( )

( )…………………….…..………………………. (3.8)

The open loop control to output voltage TF in Laplace domain is given by equation

(3.2)

( )

……………………………………...……. (3.9)

Frequency of double poles:

√ [ ( )⁄

( )⁄]

√ ………..……………… (3.10)

Frequency of zeros:

……………………………………….. (3.11)

PWM modulator gain is inversely proportional to the peak to peak ramp voltage

and given by:

( )

( )

………………………………………………………… (3.12)

The compensator transfer function from output voltage to COMP node is given as:

( ) (

)(

)

(

)(

)……………………………………. (3.13)

……………………………………………………… (3.14)



Figure 3.3: Type III compensator

The type III compensator produces two zeros and three poles. One pole is located at

the origin to realize high DC gain and the relevant components values are given as:

Loop gain crossover frequency:

………………………………………………… ….. (3.15)

The loop gain crossover frequency is usually selected between ⁄ to

⁄ of the

switching frequency. It is the zero crossover frequency defined as frequency when

loop gain is unity.

Since

………………………………….. (3.16)

So type III-B compensator is suitable for this project. The poles and zeros of the

compensator will be placed as follows:

……………………………………………….. (3.17)

The type III compensator has 3 poles and 2 zeros.

√

……………………………………..……. (3.18)

√

……………………………….………… (3.19)



is usually chosen as and this is about the maximum phase-lead obtained from

a lead compensator. The other zero of the compensator is chosen using the

following formula:

………………………………………….. (3.20)

………………………………….... (3.21)

…………………………………….…. (3.22)

……………………..……….. (3.23)

(

)

………………………………….…. (3.24)

……………………………………... (3.25)

…………………………………….. (3.26)

Considering = 2.2 nF and using equation from (3.15) to (3.26), we got the

following compensator value as shown in table below.



Table 3.1: Compensation components values

Figure 3.4: Open loop control to Output transfer function

Components Value Units

Rc1 33 kΩ

Rc2 7.5 kΩ

Cc1 32 µF

Cc2 947 pF

Cc3 2.2 nF

RFB1 475 kΩ

RFB2 475 kΩ



Figure 3.5: Bode diagram

Figure 3.6: Bode diagram



Figure 3.7: Bode Diagram

Figure 3.8: Closed Loop Bode Diagram



Figure 3.9: Output impedance Bode Diagram

Figure 3.10: Closed loop output impedance Bode Plot



// Matlab program clc; clear all; num=[1.69*10^-4 12]; den=[4.7*10^-8 2.17*10^-4 1]; t=0.0001; fs=1/t; [b,a]=bilinear(num,den,fs) x0=1; x1=0; x2=0; y1=0; y2=0; y0 = zeros(40,1); for i=1:40 y0(i) = -a(2)*y1-a(3)*y2 + b*[x0;x1;x2]; y2 = y1; y1 = y0(i); x2=x1;x1=x0;x0=1; end subplot(211); stem(y0); y = filter(b,a,[1;zeros(39,1)]); subplot(212); stem(y);

Figure 3.11: Bode plot



CHAPTER 4: HARDWARE DESIGN AND SIMULATION

4.1 Pulse Width Modulation

Figure 4.1: PWM control

Pulse Width modulation is a way to control the switch as shown in Figure 4.1 above.

The control signal is compared to a repetitive reference waveform at the desired

frequency. The switch control signal changes according to the output of the

comparison. The switch signal can be viewed as a pulse train with two states: on and

off. The Pulse Width Modulation is the method where the width of the on-part and

off-part of the switch signal are modulated to get the desired behaviour. In other

words, the method decides for how long the switch will be turned on [1].

4.2 Buck Converter Simulations

The buck converter power stage shown in Figure 4.2 is simulated using PSpice

software to obtain the output voltage and current response. The pulse-width

generator equivalent generates the pulse-width modulation to control the N-channel

MOSFET to either switch it on or off. TFis the time for the pulse to fall to zero and TR

is the time for the pulse to riseto+20 V value. PW is the time for positive pulse-width,

PER is the period for one complete cycle, Duty cycle is the positive duty cycle and

switching frequency is the desired switching frequency for the MOSFET. The

components value of the power stage is selected to be the same with the selected

values in Table 2.1. Load is selected to be 1 ohm and the input voltage is set to 12



V. The current probe and voltage probe is used to measure the voltage and current

at the inductor and the load respectively.

From the waveform shown in the figure (4.2) to (4.3), it is clear that the converter is

operating in the continuous conduction mode.

The output voltage equals 4.3399 V and output current is 4.3550 A. The output

power is 19.107 W. The related waveforms obtained from the simulation are shown

as below.

Figure 4.2: Simulation of open loop buck converter in PSpice



Figure 4.3: Inductor current and output voltage waveform

Figure 4.4: Inductor Current Waveform



Figure 4.5: Output Voltage Waveform

Figure 4.6: Inductor current waveform after zoom area



Figure 4.7: Output Current Waveform

Figure 4.8: Inductor Voltage Waveform



Figure 4.9: Gate Pulses for the MOSFET

Figure 4.10: Voltage across diode



Figure 4.11: Current across Diode

Figure 4.12: Output Power Waveform



Figure 4.13: Buck converter



4.3 NXP LPC1768 Microcontroller

4.3.1 Overview

The mbed Microcontrollers are a series of ARM microcontroller development boards

designed for rapid prototyping. The mbed NXP LPC1768 Microcontroller in particular

is designed for prototyping all sorts of devices, especially those including Ethernet,

USB, and the flexibility of lots of peripheral interfaces and FLASH memory. It is

packaged as a small DIP form-factor for prototyping with through-hole PCBs, strip

board and breadboard, and includes a built-in USB FLASH programmer.

Figure 4.3.1: NXP LPC1768

It is based on the NXP LPC1768, with a 32-bit ARM Cortex-M3 core running at

96MHz. It includes 512KB FLASH, 32KB RAM and lots of interfaces including built-in

Ethernet, USB Host and Device, CAN, SPI, I2C, ADC, DAC, PWM and other I/O

interfaces. The pin out above shows the commonly used interfaces and their

locations. Note that all the numbered pins (p5-p30) can also be used as digital in and

digital out interfaces.

The mbed Microcontrollers provide experienced embedded developers a powerful

and productive platform for building proof-of-concepts. For developers new to 32-bit

microcontrollers, mbed provides an accessible prototyping solution to get projects



built with the backing of libraries, resources and support shared in the mbed

community.

4.3.2 Features

A. NXP LPC1768 MCU

I. High performance ARM® Cortex™-M3 Core

II. 96MHz, 32KB RAM, 512KB FLASH

III. Ethernet, USB Host/Device, 2xSPI, 2xI2C, 3xUART, CAN, 6xPWM,

6xADC, GPIO

B. Prototyping form-factor

I. 40-pin 0.1" pitch DIP package, 54x26mm

II. 5V USB or 4.5-9V supply

III. Built-in USB drag 'n' drop FLASH programmer

C. mbed.org Developer Website

I. Lightweight Online Compiler

II. High level C/C++ SDK

III. Cookbook of published libraries and projects

4.3.3 Tools and Software

The mbed Microcontrollers are all supported by the mbed.org developer website,

including a lightweight Online Compiler for instant access to your working

environment on Windows, Linux or Mac OS X.

Also included is a C/C++ SDK for productive high-level programming of peripherals.

Combined with the wealth of libraries and code examples being published by the

mbed community, the platform provides a productive environment for getting things

done.



The mbed NXP LPC1768 is one of a range of mbed microcontroller packaged as a

small 40-pin DIP, 0.1-inch pitch form-factor making it convenient for prototyping with

solder less breadboard, strip board, and through-hole PCBs. It includes a built-in

USB programming interface that is as simple as using a USB Flash Drive.

4.3.4 Technical references

Power

I. Powered by USB or 4.5v - 9.0v applied to VIN

II. Less than 200mA (100mA with Ethernet disabled)

III. Real-time clock battery backup input VB

IV. 1.8v - 3.3v Keeps Real-time clock running

V. Requires 27uA, can be supplied by a coin cell

VI. 3.3v regulated output on VOUT to power peripherals

VII. 5.0v from USB available on VU (only available when USB is connected!)

VIII. Current limited to 500mA

IX. Digital IO pins are 3.3v, 4mA each, 400mA max total

Pins

I. Vin - External Power supply to the board

4.5v-9v, 100mA + external circuits powered through the Microcontroller

II. Vb - Battery backup input for Real Time Clock

1.8v-3.3v, 30uA

III. nR - Active-low reset pin with identical functionality to the reset button.

IV. Pull up resistor is on the board, so it can be driven with an open collector

V. IF+/- - Reserved for testing



The microcontroller I/O is all 3.3v logic, but 5v tolerant. A digital pin can drive 40mA,

up to a total of 400mA.

Figure 4.3.2: Block diagram of NXP LPC1768

4.3.5 Hardware Overview

The board used is Keil MCB1700. It uses the NXP LPC 1768 processor, consisting

of an ARM core (specifically, the Cortex M3), 512 KB of flash memory and 64 KB of

SRAM. The board is connected to the host computer using USB cable. It provides

power to the MCB1700. The board itself is relatively simple, and aside from the LPC

1768 itself there are only a few support circuits (mostly RS-232 level converters,

Ethernet transceivers, audio amplifiers and so on). The board provides a USB port,

two serial (COM) ports, two CAN ports, an Ethernet connector, a micro SD card slot,

a potentiometer, a speaker and a set of LEDs and buttons. It also provides a full-

colour LCD display. Pin diagram of NXP LPC1768 is shown in the figure below:



Figure 4.3.3: Pin diagram of NXP LPC1768

4.3.6 Major Functional Block

The LPC 1768 is a “system on a chip” that combines SRAM and a multichannel ADC

onto a single IC.A phase-locked loop or phase lock loop (PLL) is a control

system that generates an output signal whose phase is related to the phase of an

input "reference" signal. It is an electronic circuit consisting of a variable

frequency oscillator and a phase detector. The signal from the phase detector is

used to control the oscillator in a feedback loop. The 32-bit peripheral power control

register is referenced from C as LPC_SC->PCONP.LPC_SC is a general system-

control register block, and PCONP refers to Power CONTROL for Peripherals.

4.3.7 Memory

There are four different blocks of memory on the LPC 1768. There is a block of 512

KB of flash memory, located at the bottom of the address space, which is used for

storing your code and data. There is an 8 KB boot ROM, which is hard-coded and

unchangeable. There is a block of 32 KB of static RAM for use by the application (it’s

also possible to use this space for code, as an alternative to using the flash

memory). And finally, there are two banks of 16 KB of static RAM that are shared



with peripheral devices. All the peripherals are memory-mapped, so they are

accessible directly from C.

4.3.8 Implementation

The compensator and PWM scheme is implemented here. The error signal is

compared with a saw-tooth ramp voltage and desired PWM signal. The board can

withstand a maximum voltage of 3.3V. The pins used here are as follows:Ground,

USB(Universal Serial Bus) cable to supply the power to the board through laptop, P21

is used as the output pin which is connected to the 6th pin the driver UC3715 and P15 is

used as the ADC pin where respective pulses are generated for the PWM(Pulse

Width Modulator) which in turn is connected to the 10k Potentiometer.



CHAPTER 5: CONCLUSION AND FUTURE PROSPECTS

5.1 Conclusion

Designing a voltage-mode controlled buck converter is very challenging. The most

difficult part is determining the compensation network and manipulating the poles

and zeros to build a robust and balanced system. The PWM is a relatively simple

concept, but a real world design of this block would be troublesome. Design and

simulation of the circuit is done using Orcade (PSpice). PID controller has been

designed and the system operates in closed loop. In other words, feedback stabilizes

the system. Phase margin and gain margin has been obtained and stability analysis

of the closed loop system has been studied using MATLAB. The PID compensator

is designed by modifying the open loop buck converter circuit obtained from the

simulation in Orcade (PSpice). The error signal is compared with a saw-tooth ramp

voltage and desired PWM signal. The compensator and PWM scheme is

implemented using microcontroller NXP LPC1768 using the software Keil µVision4.

Improvement in the transient response of the converters through the use of a

feedback path with proper compensation has been achieved.

5.2 Future prospects

Technology is still improving over the years. There are many types of configuration

for buck converter control available in the market. For instance, there are

synchronous buck converter, peak-current control buck converter and etc.

Thus, this project could be expanded by implementing peak-current mode control or

synchronous buck configuration into the voltage-mode control buck converter for

improvement in the controlling of the output voltage. By improving the control method

for the buck converter, the complexity of the design will arise, thus it will need more

research to be done in the future for such improvement.

Finally, even after such improvement, there will be more research that could be done

to improve the efficiency and reliability of the converter.



REFERENCES

[1] Mohan, Ned, Undeland, T.M., and Robbins, P. W., “Power Electronics-

Converters Applications and Design”, Second Edition, John Wiley and Sons.

[2] Voltage-mode control and compensation Intricacies for buck regulators by

Timothy Hegarty, National Semiconductor - June 30, 2008.

[3] Application Note AN-1162- Compensator Design Procedure for Buck Converter

with Voltage Mode Error Amplifier By Amir M. Rahimi, Parviz Parto, and

PeymanAsadi.

[4] International Journal of Computer and Electrical Engineering Vol. 3, No. 2, April,

2011 On Modelling and Simulation of Closed loop controlled buck converter for solar

installation by A. Kalirasu and S.S.Dash.

[5] AN1452 using the MCP19035 on Synchronous buck converter design tool by

SergiuOprea, Microchip technology inc.

[6] Rashid, M.H., “Power Electronics- Circuits, Devices and Applications”, Third

Edition, Pearson.

[7] SMPS Buck Converter Design Example Web-Seminar, Microchip Technologies.

APPENDIX – DATA SHEETS

UC1714/5UC2714/5UC3714/5

FEATURES• Single Input (PWM and TTL

Compatible)

• High Current Power FET Driver, 1.0ASource/2A Sink

• Auxiliary Output FET Driver, 0.5ASource/1A Sink

• Time Delays Between Power andAuxiliary Outputs IndependentlyProgrammable from 50ns to 500ns

• Time Delay or True Zero-VoltageOperation Independently Configurablefor Each Output

• Switching Frequency to 1MHz

• Typical 50ns Propagation Delays

• ENBL Pin Activates 220µA SleepMode

• Power Output is Active Low in SleepMode

• Synchronous Rectifier Driver

DESCRIPTIONThese two families of high speed drivers are designed to provide drivewaveforms for complementary switches. Complementary switch configura-tions are commonly used in synchronous rectification circuits and activeclamp/reset circuits, which can provide zero voltage switching. In order tofacilitate the soft switching transitions, independently programmable delaysbetween the two output waveforms are provided on these drivers. The de-lay pins also have true zero voltage sensing capability which allows imme-diate activation of the corresponding switch when zero voltage is applied.These devices require a PWM-type input to operate and can be interfacedwith commonly available PWM controllers.

In the UC1714 series, the AUX output is inverted to allow driving ap-channel MOSFET. In the UC1715 series, the two outputs are configuredin a true complementary fashion.

6

5

7

8

INPUT

T1

T2

ENBL

SQ

R

TIMER

VREF

SQ

R

TIMER

VREF

50ns –500ns

50ns –500ns

5V

ENBL

VCC

3V

GND

BIAS

1.4V

ENABLE

UC1714ONLY

4 AUX

2 PWR

1 VCC

LOGICGATES

TIMERREF

3 GND

BLOCK DIAGRAM

Complementary Switch FET Drivers

SLUS170A - FEBRUARY 1999 - REVISED JANUARY 2002

UDG-99028Note: Pin numbers refer to J, N and D packages.

applicationINFOavailable

2

UC1714/5UC2714/5UC3714/5

ABSOLUTE MAXIMUM RATINGSSupply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20VPower Driver IOH

continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −200mApeak. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1A

Power Driver IOLcontinuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400mApeak. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2A

Auxiliary Driver IOHcontinuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −100mApeak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −500mA

Auxiliary Driver IOLcontinuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mApeak. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A

Input Voltage Range (INPUT, ENBL) . . . . . . . . . . −0.3V to 20VStorage Temperature Range . . . . . . . . . . . . . . −65°C to 150°COperating Junction Temperature (Note 1) . . . . . . . . . . . . 150°CLead Temperature (Soldering 10 seconds) . . . . . . . . . . . 300°C

Note 1: Unless otherwise indicated, voltages are referenced toground and currents are positive into, negative out of, the speci-fied terminals.Note 2: Consult Packaging Section of databook for thermal limi-tations and specifications of packages.

CONNECTION DIAGRAMS

DIL-8, SOIC-8 (Top View)J or N, D Packages

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, VCC = 15V, ENBL ≥ 2V, RT1 = 100kΩ from T1 to GND,RT2 = 100kΩ from T2 to GND, and −55°C < TA < 125°C for the UC1714/5, −40°C < TA < 85°C for the UC2714/5, and 0°C < TA <70°C for the UC3714/5, TA = TJ.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Overall

VCC 7 20 V

ICC, nominal ENBL = 2.0V 18 24 mA

ICC, sleep mode ENBL = 0.8V 200 300 µA

Power Driver (PWR)

Pre Turn-on PWR Output, Low VCC = 0V, IOUT = 10mA, ENBL 0.8V 0.3 1.6 V

PWR Output Low, Sat. (VPWR) INPUT = 0.8V, IOUT = 40mA 0.3 0.8 V

INPUT = 0.8V, IOUT = 400mA 2.1 2.8 V

PWR Output High, Sat. (VCC − VPWR) INPUT = 2.0V, IOUT = −20mA 2.1 3 V

INPUT = 2.0V, IOUT = −200mA 2.3 3 V

Rise Time CL = 2200pF 30 60 ns

Fall Time CL = 2200pF 25 60 ns

T1 Delay, AUX to PWR INPUT rising edge, RT1 = 10kΩ (Note 4) 20 35 80 ns

T1 Delay, AUX to PWR INPUT rising edge, RT1 = 100kΩ (Note 4) 350 500 700 ns

PWR Prop Delay INPUT falling edge, 50% (Note 3) 35 100 ns

SOIC-16 (Top View)DP Package

3

UC1714/5UC2714/5UC3714/5

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, VCC = 15V, ENBL ≥ 2V, RT1 = 100kΩ from T1 to GND,RT2 = 100kΩ from T2 to GND, and −55°C < TA < 125°C for the UC1714/5, −40°C < TA < 85°C for the UC2714/5, and 0°C < TA <70°C for the UC3714/5, TA = TJ.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Auxiliary Driver (AUX)

AUX Output Low, Sat (VAUX) VIN = 2.0V, IOUT = 20mA 0.3 0.8 V

VIN = 2.0V, IOUT = 200mA 1.8 2.6 V

AUX Output High, Sat (VCC – VAUX) VIN = 0.8V, IOUT = -10mA 2.1 3.0 V

VIN = 0.8V, IOUT = -100mA 2.3 3.0 V

Rise Time CL = 1000pF 45 60 ns

Fall Time CL = 1000pF 30 60 ns

T2 Delay, PWR to AUX INPUT falling edge, RT2 = 10kΩ (Note 4) 20 50 80 ns

T2 Delay, PWR to AUX INPUT falling edge, RT2 = 100kΩ (Note 4) 250 350 550 ns

AUX Prop Delay INPUT rising edge, 50% (Note 3) 35 80 ns

Enable (ENBL)

Input Threshold 0.8 1.2 2.0 V

Input Current, IIH ENBL = 15V 1 10 µA

Input Current, IIL ENBL = 0V −1 −10 µA

T1

Current Limit T1 = 0V −1.6 −2 mA

Nominal Voltage at T1 2.7 3 3.3 V

Minimum T1 Delay T1 = 2.5V, (Note 4) 40 70 ns

T2

Current Limit T2 = 0V −1.2 −2 mA

Nominal Voltage at T2 2.7 3 3.3 V

Minumum T2 Delay T2 = 2.5V, (Note 4) 50 100 ns

Input (INPUT)

Input Threshold 0.8 1.4 2.0 V

Input Current, IIH INPUT = 15V 1 10 µA

Input Current, IIL INPUT = 0V −5 −20 µA

Note 3: Propagation delay times are measured from the 50% point of the input signal to the 10% point of the output signal’s transi-tion with no load on outputs.

Note 4: T1 delay is defined from the 50% point of the transition edge of AUX to the 10% of the rising edge of PWR. T2 delay is de-fined from the 90% of the falling edge of PWR to the 50% point of the transition edge of AUX.

PIN DESCRIPTIONSAUX: The AUX switches immediately at INPUT’s risingedge but waits through the T2 delay after INPUT’s fallingedge before switching. AUX is capable of sourcing 0.5Aand sinking 1.0A of drive current. See the Time Relation-ships diagram below for the difference between theUC1714 and UC1715 for INPUT, MAIN, and AUX. Duringsleep mode, AUX is inactive with a high impedance.

ENBL: The ENBL input switches at TTL logic levels (ap-proximately 1.2V), and its input range is from 0V to 20V.

The ENBL input will place the device into sleep modewhen it is a logical low. The current into VCC during thesleep mode is typically 220µA.

GND: This is the reference pin for all input voltages andthe return point for all device currents. It carries the fullpeak sinking current from the outputs. Any tendency forthe outputs to ring below GND voltage must be dampedor clamped such that GND remains the most negativepotential.

4

UC1714/5UC2714/5UC3714/5

INPUT: The input switches at TTL logic levels (approxi-mately 1.4V) but the allowable range is from 0V to 20V,allowing direct connection to most common IC PWM con-troller outputs. The rising edge immediately switches theAUX output, and initiates a timing delay, T1, beforeswitching on the PWR output. Similarly, the INPUT fallingedge immediately turns off the PWR output and initiatesa timing delay, T2, before switching the AUX output.

It should be noted that if the input signal comes from acontroller with FET drive capability, this signal providesanother option. INPUT and PWR provide a delay only atthe leading edge while INPUT and AUX provide the delayat the trailing edge.

PWR: The PWR output waits for the T1 delay after theINPUT’s rising edge before switching on, but switches offimmediately at INPUT’s falling edge (neglecting propaga-tion delays). This output is capable of sourcing 1A andsinking 2A of peak gate drive current. PWR output in-cludes a passive, self-biased circuit which holds this pinactive low, when ENBL ≥ 0.8V regardless of VCC’s volt-age.

T1: A resistor to ground programs the time delay be-tween AUX switch turn-off and PWR turn-on.

T2: This pin functions in the same way as T1 but controlsthe time delay between PWR turn-off and activation ofthe AUX switch.

T1, T2: The resistor on each of these pins sets thecharging current on internal timing capacitors to provideindependent time control. The nominal voltage level ateach pin is 3V and the current is internally limited to1mA. The total delay from INPUT to each output includesa propagation delay in addition to the programmabletimer but since the propagation delays are approximatelyequal, the relative time delay between the two outputscan be assumed to be solely a function of the pro-grammed delays. The relationship of the time delay vs.RT is shown in the Typical Characteristics curves.

Either or both pins can alternatively be used for voltagesensing in lieu of delay programming. This is done bypulling the timer pins below their nominal voltage levelwhich immediately activates the timer output.

VCC: The VCC input range is from 7V to 20V. This pinshould be bypassed with a capacitor to GND consistentwith peak load current demands.

PIN DESCRIPTIONS (cont.)

PROPAGATIONDELAYS

INPUT

PWR OUTPUT

T1 DELAY T2 DELAY

UC1714 AUX OUTPUT

UC1715 AUX OUTPUT

TYPICAL CHARACTERISTICS

Time relationships. (Notes 3, 4)UDG-99027

0

100

200

300

400

500

0 10 20 30 40 50 60 70 80 90 100RT (kW)

DE

LAY

(ns)

T1 vs RT1 T2 vs RT2

T1 Delay, T2 Delay vs. RT

5

UC1714/5UC2714/5UC3714/5

15

16

17

18

0 10 20 30 40 50 60 70 80 90 100

RT (kΩ)

Icc

(mA

)

ICC vs RT with Opposite RT = 50k

0

100

200

300

400

500

600

-75 -50 -25 0 25 50 75 100 125

Temperature (°C)

De

adba

ndD

ela

y(n

s)

RT1 = 100k

RT1 = 50k

RT1 = 10kRT1 < 6k

T1 Deadband vs. Temperature AUX to PWR

Figure 1. Typical application with timed delays.

TYPICAL APPLICATIONS

UDG-94011

Figure 2. Using the timer input forzero-voltage sensing.

UDG-94012

0

100

200

300

400

500

600

-75 -50 -25 0 25 50 75 100 125

Temperature (°C)

De

adba

ndD

ela

y(n

s)

RT2 = 100k

RT2 = 50k

RT2 = 10kRT2 < 6k

T2 Deadband vs. Temperature PWR to AUX

16

17

18

19

20

21

0 100 200 300 400 500 600 700 800 9001000

Switching Frequency (kHz)

Icc

(m

A)

TYPICAL CHARACTERISTICS (cont.)

ICC vs Switching Frequency with No Load and 50%Duty Cycle RT1 = RT2 = 50k

6

UC1714/5UC2714/5UC3714/5

Figure 5. Synchronous rectifier application with a charge pump to drive the high-side n-channel buck switch.VIN is limited to 10V as VCC will rise to approximately 2VIN.

UDG-94014-1

Figure 4. Using the UC1715 as a complementary synchronous rectifier switch driver with n-channel FETs

UDG-94015-2

Figure 3. Self-actuated sleep mode with the absence of an input PWM signal. Wake up occurs with the firstpulse while turn-off is determined by the (RTO CTO) time constant.

TYPICAL APPLICATIONS (cont.)

UDG-94013

7

UC1714/5UC2714/5UC3714/5

Figure 7. Using an N-channel active reset switch with a floating drive command.

UDG-94017-1

Figure 6. Typical forward converter topology with active reset provided by the UC1714 driving an N-channelswitch (Q1) and a P-channel auxilliary switch (Q2).

TYPICAL APPLICATIONS (cont.)

UDG-94016-1

IMPORTANT NOTICE

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TI warrants performance of its hardware products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TIdeems necessary to support this warranty. Except where mandated by government requirements, testing of allparameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible fortheir products and applications using TI components. To minimize the risks associated with customer productsand applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or processin which TI products or services are used. Information published by TI regarding third–party products or servicesdoes not constitute a license from TI to use such products or services or a warranty or endorsement thereof.Use of such information may require a license from a third party under the patents or other intellectual propertyof the third party, or a license from TI under the patents or other intellectual property of TI.

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Mailing Address:

Texas InstrumentsPost Office Box 655303Dallas, Texas 75265

Copyright 2002, Texas Instruments Incorporated

This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.

©2002 Fairchild Semiconductor Corporation IRF520 Rev. B

IRF520

9.2A, 100V, 0.270 Ohm, N-Channel Power MOSFET

This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits.

Formerly developmental type TA09594.

Features

• 9.2A, 100V

• r

DS(ON)

= 0.270

Ω

• SOA is Power Dissipation Limited

• Single Pulse Avalanche Energy Rated

• Nanosecond Switching Speeds

• Linear Transfer Characteristics

• High Input Impedance

• Related Literature- TB334 “Guidelines for Soldering Surface Mount

Components to PC Boards”

Symbol

Packaging

JEDEC TO-220AB

Ordering Information

PART NUMBER PACKAGE BRAND

IRF520 TO-220AB IRF520

NOTE: When ordering, use the entire part number.G

D

S

SOURCE

DRAIN (FLANGE)

DRAINGATE

Data Sheet January 2002


Absolute Maximum Ratings

T

C

= 25

o

C, Unless Otherwise Specified

IRF520 UNITS

Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

DS

100 V

Drain to Gate Voltage (R

GS

= 20k

Ω)

(Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

DGR

100 V

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

D

T

C

= 100

o

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

D

9.26.5

AA

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

DM

37 A

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

GS

±

20 V

Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P

D

60 W

Dissipation Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 W/

o

C

Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E

AS

36 mJ

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

J,

T

STG

-55 to 175

o

C

Maximum Temperature for SolderingLeads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

L

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

pkg

300260

o

C

o

C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of thedevice at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. T

J

= 25

o

C to 150

o

C.

Electrical Specifications

T

C

= 25

o

C, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV

DSS

I

D

= 250

µ

A, V

GS

= 0V (Figure 10) 100 - - V

Gate to Threshold Voltage V

GS(TH)

V

GS

= V

DS

, I

D

= 250

µ

A 2.0 - 4.0 V

Zero Gate Voltage Drain Current I

DSS

V

DS

= 95V, V

GS

= 0V - - 250

µ

A

V

DS

= 0.8 x Rated BV

DSS

, V

GS

= 0V, T

J

= 150

o

C - - 1000

µ

A

On-State Drain Current (Note 2) I

D(ON)

V

DS

> I

D(ON)

x r

DS(ON)MAX

, V

GS

= 10V (Figure 7) 9.2 - - A

Gate to Source Leakage Current I

GSS

V

GS

=

±

20V - -

±

100 nA

Drain to Source On Resistance (Note 2) r

DS(ON)

I

D

= 5.6A, V

GS

= 10V (Figure 8, 9) - 0.25 0.27

Ω

Forward Transconductance (Note 2) gfs V

DS

≥

50V, I

D

= 5.6A (Figure 12) 2.7 4.1 - S

Turn-On Delay Time t

d(ON)

V

DD

= 50V, I

D

≈

9.2A, R

G

= 18

Ω

, R

L

= 5.5

Ω

MOSFET Switching Times are Essentially Independent of Operating Temperature

- 9 13 ns

Rise Time t

r

- 30 63 ns

Turn-Off Delay Time t

d(OFF)

- 18 70 ns

Fall Time t

f

- 20 59 ns

Total Gate Charge(Gate to Source + Gate to Drain)

Q

g(TOT)

V

GS

= 10V, I

D

= 9.2A, V

DS

= 0.8 x Rated BV

DSS

, I

g(REF)

= 1.5mA (Figure 14) Gate Charge is Essentially Independent of OperatingTemperature

- 10 30 nC

Gate to Source Charge Q

gs

- 2.5 - nC

Gate to Drain “Miller” Charge Q

gd

- 2.5 - nC

Input Capacitance C

ISS

V

DS

= 25V, V

GS

= 0V, f = 1MHz(Figure 11)

- 350 - pF

Output Capacitance C

OSS

- 130 - pF

Reverse Transfer Capacitance C

RSS

- 25 - pF

Internal Drain Inductance L

D

Measured From the Contact Screw On Tab To Center of Die

Modified MOSFET Symbol Showing the Internal Devices Inductances

- 3.5 - nH

Measured From the Drain Lead, 6mm (0.25in) From Package to Center of Die

- 4.5 - nH

Internal Source Inductance L

S

Measured From the Source Lead, 6mm (0.25in) From Header to Source Bonding Pad

- 7.5 - nH

Thermal Resistance Junction to Case R

θ

JC

- - 2.5

o

C/W

Thermal Resistance Junction to Ambient R

θ

JA

Free Air Operation - - 80

o

C/W

LD

LS

D

S

G

IRF520


Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Continuous Source to Drain Current I

SD

Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode

- - 9.2 A

Pulse Source to Drain Current (Note 3) I

SDM

- - 37 A

Source to Drain Diode Voltage (Note 2) V

SD

T

J

= 25

o

C, I

SD

= 9.2A, V

GS

= 0V (Figure 13) - - 2.5 V

Reverse Recovery Time t

rr

T

J

= 25

o

C, I

SD

= 9.2A, dI

SD

/dt = 100A/

µ

s 5.5 100 240 ns

Reverse Recovered Charge Q

RR

T

J

= 25

o

C, I

SD

= 9.2A, dI

SD

/dt = 100A/

µ

s 0.17 0.5 1.1

µ

C

NOTES:

2. Pulse test: pulse width

≤

300

µ

s, duty cycle

≤

2%.

3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).

4. V

DD

= 25V, starting T

J

= 25

o

C, L = 640mH, R

G

= 25

Ω,

peak I

AS

= 9.2A.

Typical Performance Curves

Unless Otherwise Specified

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE

FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE

G

D

S

TC, CASE TEMPERATURE (oC)25 50 75 100 125 150 1750

PO

WE

R D

ISS

IPA

TIO

N M

ULT

IPL

IER

0

0.2

0.4

0.6

0.8

1.0

1.2

TC, CASE TEMPERATURE (oC)

50 75 100 17525

10

8

6

0

4

I D, D

RA

IN C

UR

RE

NT

(A

)

2

125 150

ZθJ

C, T

RA

NS

IEN

T 1

0.1

0.0110-210-5 10-4 10-3 0.1 1 10

t1, RECTANGULAR PULSE DURATION (s)

PDM

t1t2

10

NOTES:DUTY FACTOR: D = t1/t2PEAK TJ = PDM x ZθJC + TC

SINGLE PULSE

0.5

0.020.05

0.2

0.01

0.1

TH

ER

MA

L IM

PE

DA

NC

E (

oC

/W)

IRF520


FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS

FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS

FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT

FIGURE 9. NORMALIZED DRAIN TO SOURCE ONRESISTANCE vs JUNCTION TEMPERATURE

Typical Performance Curves Unless Otherwise Specified (Continued)

100

10

1

10001 10 1000.1

I D, D

RA

IN C

UR

RE

NT

(A

)

VDS, DRAIN TO SOURCE VOLTAGE (V)

TC = 25oCTJ = MAX RATEDSINGLE PULSE

10µs

100µs

1ms

10msOPERATION IN THISAREA IS LIMITEDBY rDS(ON)

10V

VDS, DRAIN TO SOURCE VOLTAGE (V)200 50

15

12

9

0

6

I D, D

RA

IN C

UR

RE

NT

(A

)

VGS = 7V

3

30

VGS = 6V

VGS = 8V PULSE DURATION = 80µs

10 40

VGS = 5V

VGS = 4V

DUTY CYCLE = 0.5% MAX

15

12

9

0

6

1 2 3 40 5

I D, D

RA

IN C

UR

RE

NT

(A

)


3

VGS = 6V

VGS = 5V

VGS = 4V

VGS = 7V

VGS = 8V

VGS = 10VPULSE DURATION = 80µsDUTY CYCLE = 0.5% MAX

102

0.12 4 6 80

I D(O

N),

ON

-STA

TE

DR

AIN

CU

RR

EN

T (

A)

VGS, GATE TO SOURCE VOLTAGE (V)

1

10

10

175oC 25oC

VDS ≥ 50VPULSE DURATION = 80µsDUTY CYCLE = 0.5% MAX

ID, DRAIN CURRENT (A)16 320 40

2.5

2.0

1.5

0

1.0

r DS

(ON

), D

RA

IN T

O S

OU

RC

E O

N R

ES

ISTA

NC

E

PULSE DURATION = 80µs

8 24

0.5

VGS = 10V

VGS = 20V


3.0

1.8

0.6

0 60-60

TJ, JUNCTION TEMPERATURE (oC)

NO

RM

AL

IZE

D O

N R

ES

ISTA

NC

E

2.4

1.2

0-40 -20 20 40 80 100 140120 160 180

ID = 9.2A, VGS = 10VPULSE DURATION = 80µsDUTY CYCLE = 0.5% MAX

IRF520


FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE

FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

Typical Performance Curves Unless Otherwise Specified (Continued)

1.25

1.05

0.85

0 180

TJ, JUNCTION TEMPERATURE (oC)

NO

RM

AL

IZE

D D

RA

IN T

O S

OU

RC

E

1.15

0.95

0.75-60

BR

EA

KD

OW

N V

OLT

AG

E

60 120

ID = 250µA


C, C

APA

CIT

AN

CE

(p

F)

1000

800

600

400

200

0

VGS = 0V, f = 1MHzCISS = CGS + CGDCRSS = CGDCOSS ≈ CDS + CGD

1 10 102

CISS

COSS

CRSS

ID, DRAIN CURRENT (A)3 6 9 120 15

5

4

3

0

2

gfs

, TR

AN

SC

ON

DU

CTA

NC

E (

S)

1

TJ = 175oC

TJ = 25oC

PULSE DURATION = 80µsVDS ≥ 50


TJ = 175oC

I SD

, SO

UR

CE

TO

DR

AIN

CU

RR

EN

T (

A)

VSD, SOURCE TO DRAIN VOLTAGE (V)

100

10

0.10 0.4 1.2 1.6 2.00.8

TJ = 25oC1

PULSE DURATION = 80µsDUTY CYCLE = 0.5% MAX

Qg, GATE CHARGE (nC)

3 6 9 120 15

20

8

0

VG

S, G

AT

E T

O S

OU

RC

E V

OLT

AG

E (

V)

4

ID = 9.2A

16

12

VDS = 20VVDS = 50VVDS = 80V

IRF520


Test Circuits and Waveforms

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

tP

VGS

0.01Ω

L

IAS

+

-

VDS

VDDRG

DUT

VARY tP TO OBTAIN

REQUIRED PEAK IAS

0V

VDD

VDS

BVDSS

tP

IAS

tAV

0

VGS

RL

RG

DUT

+

-VDD

tON

td(ON)

tr

90%

10%

VDS90%

10%

tf

td(OFF)

tOFF

90%

50%50%

10%PULSE WIDTH

VGS

0

0

0.3µF

12VBATTERY 50kΩ

VDS

S

DUT

D

G

Ig(REF)0

(ISOLATEDVDS

0.2µF

CURRENTREGULATOR

ID CURRENTSAMPLING

IG CURRENTSAMPLING

SUPPLY)

RESISTOR RESISTOR

SAME TYPEAS DUT

Qg(TOT)

Qgd

Qgs

VDS

0

VGS

VDD

IG(REF)

0

IRF520

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHERNOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILDDOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCTOR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENTRIGHTS, NOR THE RIGHTS OF OTHERS.

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and isnot intended to be an exhaustive list of all such trademarks.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.As used herein:1. Life support devices or systems are devices orsystems which, (a) are intended for surgical implant intothe body, or (b) support or sustain life, or (c) whosefailure to perform when properly used in accordancewith instructions for use provided in the labeling, can bereasonably expected to result in significant injury to theuser.

2. A critical component is any component of a lifesupport device or system whose failure to perform canbe reasonably expected to cause the failure of the lifesupport device or system, or to affect its safety oreffectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Obsolete

This datasheet contains the design specifications forproduct development. Specifications may change inany manner without notice.

This datasheet contains preliminary data, andsupplementary data will be published at a later date.Fairchild Semiconductor reserves the right to makechanges at any time without notice in order to improvedesign.

This datasheet contains final specifications. FairchildSemiconductor reserves the right to make changes atany time without notice in order to improve design.

This datasheet contains specifications on a productthat has been discontinued by Fairchild semiconductor.The datasheet is printed for reference information only.

Formative orIn Design

First Production

Full Production

Not In Production

OPTOLOGIC™OPTOPLANAR™PACMAN™POP™Power247™PowerTrenchQFET™QS™QT Optoelectronics™Quiet Series™SILENT SWITCHER

FASTFASTr™FRFET™GlobalOptoisolator™GTO™HiSeC™ISOPLANAR™LittleFET™MicroFET™MicroPak™MICROWIRE™

Rev. H4

ACEx™Bottomless™CoolFET™CROSSVOLT™DenseTrench™DOME™EcoSPARK™E2CMOSTM

EnSignaTM

FACT™FACT Quiet Series™

SMART START™STAR*POWER™Stealth™SuperSOT™-3SuperSOT™-6SuperSOT™-8SyncFET™TinyLogic™TruTranslation™UHC™UltraFET

STAR*POWER is used under license

VCX™

This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.

Features High Surge Capability

Types up to 40V

Maximum Ratings Operating Temperature: -65 C to +150

Storage Temperature: -65 C to +175

Part NumberMaximumRecurrent

Peak ReverseVoltage

MaximumRMS Voltage

Maximum DCBlockingVoltage

Electrical Characteristics @ 25 Unless Otherwise SpecifiedAverage ForwardCurrent

IF(AV) 15A TC =100

Peak Forward SurgeCurrent

IFSM 500A 8.3ms , half sine

MaximumInstantaneousForward Voltage

VF

IRmA

TJ = 25

T = 25

V RRM

Maximum ThermalResistance,Junction To Case

R jc C/W

0.44V

IFM =15 A

DO-5DO-5

MM

NN

BB

CC

JJ

PP

FF

GG

DD

EEAA

KK

SCHOTTKY DIODES STUD TYPE 15 A

Notes:1.Standard Polarity:Stud is Cathode2.Reverse Polarity:Stud is Anode

1N5827(R)1N5826(R)

1N5828(R)

20V30V40V

14V21V28V

20V30V40V

mA 10

250

1.8

TJ = 125

0.47V 0.50V

; j

(1N5826) (1N5827) (1N5828)

15Amp Rectifier 20-40 Volts

1N5826(R) THRU1N5828(R)

DIMENSIONS

INCHES MM

DIM MIN MAX MIN MAX NOTE

A ¼ 1/4 -28 Threads Standard Polarity

B .669 .687 17.19 17.44

C ----- .794 ----- 20.16

D ----- 1.020 ----- 25.91

E .422 .453 10.72 11. 50

F .115 .200 2.93 5.08

G ----- .460 ----- 11.68

H . .

J ----- .375 ----- 9.52

K .156 ----- 3.96 -----

M ----- .667 ----- 16.94

N ----- .080 ----- 2.03

P .140 .175 3.56 4.45

--------------------

NOTE (1)

Pulse Test: Pulse Width 300 usec, Duty Cycle 2%

NOTE : (1) <

Voltage

Maximum InstantaneousReverse Current AtRated DC Blocking

NOTE (1)

Transys ElectronicsL I M I T E D

Ave

rage

For

wA

rd R

ectif

ied

Cur

rent

- A

mP

eres

Case Temperature -

Figure 2Forward Derating Curve

0 18030 60 90 1200

6

150

InS

tant

aneo

us

For

war

d C

urre

nt

- A

mpe

res

Instantaneous Forward Voltage - Volts

Figure 1Typical Forward Characteristics

Amps

Volts

1 10040

100

8

Figure Peak Forward Surge Current

Peak

Fo

rwar

d Su

rge

Curre

nt- A

mpe

res

Number Of Cycles At 60Hz - Cycles

Cycles

2 6 10 20 60 8040

Reverse Voltage - Volts

Figure 4Typical Reverse Characteristics

Volts

Amps

Am

ps

200

300

400

500

600

0 0.2 0.4 0.6 0.8 1.0 1.2

9

15

3

1N5826( R ) THRU 1N5828(R)

12

18

10

20

6.0

40

60

100

1.0

2.0

4.0

125 C

25 C

40

60

200

100

5010 20 30 40

.1

.2

.4

.6

1

2

4

6

10

20

400

600

.01

.02

.04

.06

0

Tj =125 C

TJ =25

TJ =75

Tj =150 C

1000

3

Single Phase, Half Wave60Hz Resistive or Inductive Load

Am

ps

m

I ns t

ant a

neou

s

Rev

ers e

Lea

kage

Cur

rent

- M

illm

pere

sA

voltage mode control of buck converter

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