Rev. 0.1 11/08 Copyright © 2008 by Silicon Laboratories WDS CC-UG

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WDS CHIP CONFIGURATOR USER GUIDE

1. Introduction

Welcome to the BETA release of the new Wireless Development Suite (Ver. 3.0).

WDS 3.0 BETA brings users an exciting new development environment for the EZRadio® and EZRadioPRO™wireless products from Silicon Laboratories.

Important Part Numbering Message:

In the transition from Integration Associates to Silicon Laboratories, the 'IAxxxx' markings were changed to an'Sixxxx' format (e.g. IA4421 Si4421). In addition, the transmitter part numbers starting with 42xx were renamedas the 40xx (e.g. IA4222 Si4022).

WDS 3.0 currently supports the following products:

Table 1. Supported Products

EZRadio

Transmitters Receivers Transceivers

Si4020 Si4320 Si4420

Si4021 Si4322 Si4421

Si4022

EZRadioPRO

Transmitters Receivers Transceivers

Si4030* Si4330* Si4430*

Si4031 Si4431*

Si4032* Si4432

*Note: These parts will be supported in the full WDS release.

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2. Installation

To start, run the Chip Configurator installer program from the CDROM set or from a saved location. Once started, asetup wizard will appear on your screen.

Figure 1. Initial Installation Screen

Click 'Next >' to start the installation process.

Figure 2. License Agreement

Review the license agreement and click the agreement box. Click 'Next >'.

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Figure 3. Installation Options

Next, installation options are made available and users can select where they wish the installed files to be written.Silicon Labs recommends the default settings. Once the settings have been confirmed, click 'Install'.

The installation program ensures that pre-requisite programs such as Microsoft's .NET environment are pre-installed, if they are not it will install them for you.

Note: Microsoft's .NET and Visual C++ 2005 Redistributable Package are quite large and can take several minutes to install.During this time the WDS Chip Configurator installation process may appear to stop while the .NET installation takesplace in the background - this is normal and installation will continue until its completion. Microsoft's Office and InternetExplorer tools should be closed during this installation.If your system configuration does not allow the installation of .NET from within the WDS installer it will be necessary toinstall .NET prior to the WDS installation.

Figure 4. Installation Complete

Once installation is complete the installer wizard will notify you with the splash screen in Figure 4. You may click the'start the application' box which will launch the newly installed software once you click 'Finish'.

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3. Overview

The WDS 3.0 environment is a ground up re-design with the aim of introducing a powerful new system architecturethat enables many new features including:

An improved look-and-feel of the WDS GUI

Support for future extensions including: new RF devices, demonstration programs, and test applications

Support for various I/O connections including USB and TCP/IP

Improved Graphical User Interface (GUI) responsiveness

Figure 5. Software Overview

To achieve these goals WDS has been split into 3 functional software layers:

1. Graphical User Interface (GUI) layer.

2. Data Flow Manager layer which can handle more than one parallel and bi-directional data flow channels between each GUI window and associated device pairs.

3. I/O Port Handler layer which carry out the physical data transfer (and implement communication protocols) with the devices (e.g. via USB, TCP/IP, etc.).

Window-1 Data Object-1

Device-1I/O Port Handler-1

TELEGRAM(s)

TELEGRAM(s)

Window-n Data Object-n

Device-nI/O Port Handler-n

TELEGRAM(s

TELEGRAM(s)

Graphical User Interface Layer

Data Flow Manager Layer

I/O Port Handler Layer

WDS 3.0 Software

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3.1. The New GUI InterfaceIn previous revisions of WDS Chip Configurator, the software enabled only one device and one control window tobe opened at any one time but as the demand for wireless applications grow, so has the need to work on multipleRF nodes during the development cycle.

WDS Chip Configurator's new GUI interface allows for a window to be connected to one or more devices and eachdevice could be connected to different I/O ports on a PC.

Figure 6. Connectivity Diagram

3.2. Getting StartedWDS Chip Configurator can be started from the Microsoft Windows® Start button.

Once the program has started, you will be greeted by the Silicon Labs’ splash screen which also incorporates thesoftware version and build numbers for future reference.

Programs Silicon Laboratories

Window-1 (Transmitter-1)

Device-1 (Si4020 on Port-1)

Window-2 (Transmitter-2)

Device-2 (Si4020 on Port-2)

Window-3 (Receiver-1)

Device-3 (Si4320 on Port-3)

Window-4 (EEPROM Programmer-1)

Device-4 (EEPROM on Port-4)

Window-5 (Test Application-1)

Device-5 (Si4020 on Port-5)

Device-6 (Si4020 on Port-6)

Window-7 (To display received data)

Window-6 (To send data)

Device-7 (Some input/output device)

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Figure 7. Splash Screen

By either clicking the splash screen or waiting for the timeout to occur, you will be presented by a mode selectionmenu.

Figure 8. Mode Selection Menu

The two modes operate as follows:

3.2.1. Hardware Mode

Hardware mode should be selected when you intend to connect one of the supported hardware platforms such asthe Loadboard. When using USB, the plug-and-play handler will automatically select this button for you.

3.2.2. Simulation Mode

Simulation mode should be selected when you intend to use WDS Chip Configurator without hardware, such aswhen you intend to use the tool to calculate register values for research purposes and so forth. In this mode, WDSassumes non-physical ‘ghost’ hardware is connected.

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3.3. Connections ManagerWhether you opt to select a Hardware Mode or a Simulation Mode, the flow of WDS Chip Configurator is the same.

Once you select your mode of operation you will be presented with the Connection Manager, in this window youwill select the connected RF device or the 'ghost' hardware that is assumed under simulation mode. When certainplatforms are connected, the software will reduce the options based upon the EBID report (see Hardware UserGuide).

Figure 9. Connection Manager (1 of 2)

RFIC Selection - provides the list of the available RFIC after the filters have been applied, or in hardware mode after the RFIC detection process has been completed.

Function Filter - reduces the number of available RFIC's by function (e.g. Transceiver).

RFIC Family Filter - reduces the number of available RFIC's by family membership (e.g. EZRadio).

IC Revision - this option is unavailable in hardware mode when using load boards with a properly programmed EBID. However, it is always available in simulation mode. This field allows users to select the appropriate RFIC revision.

'nickname' - this field is extremely useful if multiple hardware (ghost or physical) is connected into the WDS Chip Configurator environment as it labels all appropriately connected windows by that name reducing confusion when large system tests are being attempted.

Figure 10. Connection Manager (2 of 2)

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Once the device is connected to the WDS Chip Configurator environment, the Applications Manager screenappears.

3.4. Applications ManagerWDS is designed to support 'plug-in' software modules for given RFIC's and hardware platforms. These modulesare classified into 3 categories:

1. Control Panels - allow users to manipulate register settings of the connected RFIC's for lab based experiments. The function of these windows is very similar to that in previous versions of WDS.

2. Applications - this tab provides a list of available and extended software modules such as Network Protocol Analyzers.

3. Demos - many of the new hardware platforms that can connect to WDS are configurable by the software and as such can be 'flashed' to operate as follows:

a. Temperature monitoring demos

b. Push button demos

c. EZMac™ demos

Figure 11. Applications Manager

In the example above, the Si4520 has been filtered down to one option - The Radio Control Panel.

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3.5. Control PanelsWhen selecting the 'Radio Control Panel' for the EZRadio devices, the familiar yet enhanced control interface fromprevious WDS versions is presented.

Figure 12. Radio Control Panel

The functions of the control panel are very similar to previous versions of WDS; however, given that WDS can nowoperate with multiple hardware connections, many of the original pull down options are integrated into the activewindow.

Control Tools - allow you to load and save configurations, set hardware voltage levels and look at snapshots of current consumption for the connected hardware.

'nickname' - displays the label associating that window to the appropriate hardware.

Page Tabs - change between tasks.

Control Interface - manipulate register values.

Log Tab - double clicking the red bar extends the window to show log and scripting panels.

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3.5.1. The Logging and Scripting Extension

Figure 13. Logging and Scripting Extension

3.6. Control ToolsWith the release of the new WDS GUI, a number of functions were introduced on to the control tool bar at the top ofthe panel.

Figure 14. Control Tool Bar

So that designers can load/save project configurations for future use, the load/save function buttons are availableon every control panel. By default these configuration files are located in a 'project configuration' folder in the WDSdirectory structure, but designers can opt to save and load files from locations of their choice. As a new feature toWDS 3.0, a comments field has been added to the Save File window for future reference.

Figure 15. Save File

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The control tool bar also comes with the voltage and current consumption tools.

Figure 16. Voltage and Current Consumption Tools

3.6.1. IC Voltage Setting

To configure connected hardware such as a Loadboard to set the chip voltage to a particular level, the designermust enter the voltage level into the voltage box and then click the green arrow.

Figure 17. IC Voltage Setting

The relevant commands can be seen in the log window if it is extended.

3.6.2. Current Monitor

Figure 18. Current Monitor

The control tool bar comes with two current monitoring features. In both cases the current displayed is asnapshot rather than a continual monitor. The purpose of this tool is to act as a guide for designers wanting tounderstand how certain register settings can effect the current consumption.

Note: Loadboard 2.2 has one hardware restriction that users should be aware of—Loadboard 2.2 can only measure up to amaximum of 20 mA. Therefore, devices such as the Si4322 will ‘max out’ the scale when set to PMAX.

3.6.3. Soft Reset

In earlier versions of WDS many designers simply turned off external hardware to reset an RFIC undertest. Due to the plug 'n' play handler built in to WDS 3.0, this method is no longer recommended sinceusers will be prompted by the connections manager upon reconnection.

In WDS 3.0 a new soft reset button has been implemented in the control tool bar; depending on the RFIC, either areset is applied or registers are loaded with their default values.

3.6.4. HardwareID

With the ability to handle multiple connections from one WDS tool, it is possible that designers couldbecome confused between which windows are connected to which hardware. To help avoid these issues,a system of 'nicknames' is implemented which ties windows together, but this does not address theidentification of connected hardware. To overcome this, a 'HardwareID' button has been implemented.

If users are running hardware, such as the loadboard, and if it contains the latest firmware, then clicking on theHardwareID button will result in the flashing of two LEDs on the loadboard to aid in the identification. In oldfirmware revisions, the Loadbaord will ignore the command.

EZRadioPRO is designed to offer users the highest performance radio with maximum flexibility in design. Tosupport these added features, much more extensive control panels are available by comparison to those offered bythe EZRadio family of devices.

Table 2. Current Monitor Function Descriptions

Icon Function

Measure chip current(Warning - this is a snapshot, not a continual measurement)

Measure chip current on an update(Warning - this is a snapshot, not a continual measurement)

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The EZRadioPRO family has a 'basic' radio control panel, but also has an extended 'register settings panel', both ofwhich can be selected from the Applications Manager.

Figure 19. Selecting Radio Control Panel from the Applications Manager

In the EZRadioPRO family, multiple registers are usually modified to adjust settings. Under the EZRadioPRO radiocontrol panel these are adjusted as a background task, and as such are not highlighted, as they are in the EZRadiocontrol panels. This allows for a quick, uncluttered window to change the basic parameters.

In the EZRadioPRO radio control panel, any changes made will result in a telegram being sent to the registersettings panel, which actually performs the register update in the radio.

Figure 20. Extended Options Pull Down

Registers in the EZRadioPRO family of devices can be directly manipulated through the 'Register Settings Panel',which can be launched in the Applications Manager.

It is however possible to launch the Register settings panel from the radio control panel directly. If the small pull-down is used to expose the extended options, then 3 new icons can be seen.

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Figure 21. Extended Options Available

To launch the Register Settings Panel from the Radio Control Panel, click the following icon:

Figure 22. Switch Application

This will launch the window in Figure 23.

Figure 23. Register Settings Panel

In addition to the usual features this screen shows:

Functions Tabs - switch the screen so that the settings panel shows the appropriate information for the task being worked on.

Register Manipulation Window - where individual register bits may be modified. An orange cell represents a register bit set to '1', and a white cell represents a register bit set to '0'. Clicking on a cell toggles the setting.

When altering a setting in the Radio Control Panel, the appropriate registers will be modified in the Register SettingPanel.

Note: THIS IS CURRENTLY A ONE WAY PROCESS. Modifications in the register settings panel will not be reflected in a Radio Control Panel, as such the ability to launch theRadio Control Panel from the Register Settings Panel is disabled.

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4. Icon Glossary

Table 3. Glossary of Icons

Icon Description

Creates an instance of WDS when physical hardware is to be connected (e.g. Loadboard)

Creates an instance of WDS when 'ghost' hardware is connected

Allows users to define their workspace environment such as language and logging preferences

Starts Connection Manager

When workspaces become cluttered by multiple windows. Using this button will move all windows into a cascaded position

In the event bugs are noticed or features are requested, use this button to send the WDS team an emailNote: This button does not operate as a technical support portal.

Provides a list of currently supported RFIC's by WDS

Provides information on the WDS version

Transmitter

Receiver

Transceiver

Toggles between the 'Register Settings Panel' and ‘Radio Control Panel’

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Issues a 'Soft Reset' to the RFIC restoring default values

Requests the connected hardware associated with a given panel to high-light itself(requires firmware update in earlier Loadboard 2.x)

Load project configuration from disc

Save project configuration to disc

Instruct Loadboard to implement a voltage change

Measure chip current(Warning - this is a guideline snapshot, not a continual measurement)

Measure chip current on an update (Warning - this is a guideline snapshot, not a continual measurement)

Table 3. Glossary of Icons (Continued)

Icon Description

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5. Introduction to Advanced Testing with WDS

The following section will demonstrate how to use the WDS Chip Configurator with the Loadboard hardwareplatform.

Figure 24. Loadboard Hardware Platform

This tutorial will demonstrate how to implement the following experiments:

Section “6.2. Transmitter Testing” covers the following tasks:

Setting CW

Setting output power

Setting Center Frequency

Generating PN9 data

Setting modulation scheme

Sending direct data

Sending data with FIFO

Section “6.3. Receiver Testing” covers the following tasks:

Receiving direct data

Receiving data with FIFO

BER (Bit Error Rate) Tests

Setting receiver data for different data rates, deviations, filter bandwidths etc.

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5.1. Introducing the WDS EnvironmentPrior to attempting the experiments, it is important to understand some of the basic tools available in WDS. Tointroduce these tools it is assumed that Loadboard hardware is connected, an Si4432 EZRadioPRO transceivertest card is selected, and the 'Register Settings Panel' is open.

Figure 25. Register Settings Panel

5.2. Batch Files and the Batch WindowAs engineers learn WDS and want to make use of its features for exhaustive tests, they can create, save, and runbatch files. These batch files can be used to configure multiple registers through a single click.

The batch file is designed to be constructed as a simple text file. Some basic rules have to be followed in order toensure that the batch file is executed correctly by WDS. An example batch file is shown below:

#BATCHNAME IA4432_RevX2 CW F:917.5MHz# Set power supply to 3.3VVA1# Set SDN pin to LOWL6# Operating & Function Control 2 : Register 07H.# Write data swres= '1' (To write the data, MSB of the command should be set # to '1'. Toread the data, MSB of the command should be set to '0'S2 8780# Operating & Function Control 2 : Register 07H.# Read Status from 07H (To read the data, MSB of the command should be set # to '0'.S2 0700

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A batch file can consist of comments and hardware commands:

If a line starts with the # character, then the line is considered a comment and is used for user reference only.

If a line starts with #BATCHNAME, then the text in this line will appear as the title of the script just above the batch command textbox.

If a line starts with a valid hardware command (such as those used to change the value of an radio's register or to set the power supply), then the given command will be sent to the hardware through the USB interface.

Figure 26. Batch Editor

Table 4. Loadboard Command Descriptions

Loadboard Command Description

Vxx Set supply voltage (64: 2.0 V – C1: 5 V).

Ln Set output bit ‘n’ to low.(Note: SDN pin of the EZRadio PRO device is connected to output 6.)

Hn Set output bit ‘n’ to high.(Note: SDN pin of the EZRadio PRO device is connected to output 6.)

S2xxxx Send xxxx (hex) command to EZRadio PRO device via SPI port.

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5.3. Loading Existing Batch Files1. Select the 'Batch Editor' tab.

2. Select one of the 4 batch boxes and load the batch file from disk. The batch editor will allow for up to 4 scripts to be loaded at any one time.

3. The batch file load in to the selected batch script box.

4. Batch files are executed by clicking the 'Run' button. Additionally, batch files can be looped by selecting the 'Loop' checkbox'.

Figure 27. Loading an Existing Batch

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5.4. Creating a Batch FileThe scripts in the WDS batch files are simple ASCII text files, so a text editor can be used to create them; however,batch files may also be created from within WDS environment.

1. Select the 'Batch Editor' tab.

2. Select the register that requires manipulation (note the register's description can be found in the 'register description' tab).

3. Set the register content by clicking on the relevant bits (A bit is set to '1' when orange and '0' when white).

4. Allocate the register to a batch window by clicking 1, 2, 3, or 4.

5. Repeat steps 3 and 4 until all the required registers are set.

6. Comments or additional Loadboard commands can be typed directly into the batch textbox for future reference.

7. Save your batch files for future use.

8. Run the batch (select 'Loop' if required)Note: Ensure that all batch files end with a carriage return for proper parsing.

Figure 28. Creating a Batch File

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6. Hardware Setup

6.1. Current Consumption MeasurementsContinual current consumption measurements can be taken by connecting a standard multimeter to JP3/JP4(Loadboard 2.2).

Figure 29. Current Consumption Measurement

6.2. Transmitter Testing6.2.1. Output Spectrum Measurements

The EZRadioPRO family can generate a number of test signals such as a CW (Continuous Wave) or a PN9randomly generated signal, these signals can be used to modulate the output spectrum. Using the modulatedoutput spectrum users can test the RF transmit performance characteristics such as output power, phase noise,and spurious emissions for both un-modulated and PN9 modulated waveforms.

To perform these tests using the appropriate CW or PN9 scripts from within the WDS environment, use anappropriate EZRadioPRO test card plugged into the Loadboard. The Loadboard should then be connected to labbased test equipment as shown in Figure 30. Next, run an appropriate CW or PN9 script from within the WDSenvironment.

Figure 30. Output Spectrum Measurements

Connect the multimeter to JP3 or JP4 to measure the

current consumption

GPIO0

GPIO1

GPIO2

TX Output

Oscilloscope

Vector Signal Analyzer

RX Input

Spectrum Analyzer

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6.2.2. Generating Un-modulated CW on the Default Center Frequency

WDS Commands:# Set PWRDWN pin = LOWL6# Apply Software Reset# Write Register 07: Operating & Function Control1 # Software Reset : set 'swres' bit to 1S2 8780# Write Register 55: Reduce xTAL Start-#upS2 D540# Set VCO Bias CurrentS2 DA03# Set FBDIV HC and disable TX boostS2 D940# Set DIG Regulator to 1.5VS2 E602# Write Register 62: Crystal Oscillator / Control Test# Reduces crystal startup time. (Based on measurement results)S2 E200# Turn On the Transmitter # Write Register 07: Operation & Mode Control1 # Set txon = '1'S2 8708

Expected results:

Figure 31. TX Output in CW Mode

The spectrum plot shows TX output after running the script described above. When users turn on the transmitterwith default settings, an un-modulated carrier at 915 MHz will be created.

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6.2.3. Compensating for the Crystal Error

Because of imperfections in the external crystals, there will likely be some offset in the system. In order tocompensate for this offset, the capacitance bank of the crystal should be adjusted. This is not required if the AFC isenabled or if a wider IF filter is used.

Instructions: Connect the TX output to the spectrum analyzer and confirm that the TX output is at exactly 915 MHz(default). If not, adjust the registers to fine tune the crystal.

WDS Commands:# Fine tune the crystal to remove any offset. # Write Register 09: Crystal Oscillator Load Capacitance Register # Step through values in this register such that the TX output is at 915Mhz (±0.5 kHz)S2 897a

Crystal Frequency offset may also be compensated by offsetting the PLL frequency such that there is no error atthe RF output. The PLL step is 312.5 Hz in high band and 156.25 Hz in low band.

WDS Commands:# The PLL may also be offset to adjust frequency # Not required if AFC is enabled or wider IF Filter is used. # Write Register 73, 74, 1D: Frequency Offset Register, Frequency Channel Control, AFCLoop # Gearshift Override (Disable AFC)# Step through values in this register such that the TX output is at 915Mhz (±0.5 kHz)S2 9D00S2 F300S2 F400

Expected Results:

Figure 32. TX Output after Crystal Compensation

The spectrum plot shows TX output after running the scripts above. After fine tuning the crystal, TX output is at915 MHz.

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6.2.4. Change the TX Power

WDS Commands: # Set TX output power to desired value.# Write Register 6D: TX Power# Power Step 0S2 ED00

Expected Results:

Figure 33. Stepping TX Output Power

Blue Trace: TX Power register is set to '00'.

Yellow Trace: TX Power register is set to '11'.

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6.2.5. Change Frequency

The frequency of the EZRadioPRO devices can be modified by changing the frequency band select and nominalcarrier frequency registers (reg. 75, 76, 77H).

WDS Commands:# Change TX Frequency from default (915MHz) to 917 MHz # Write Register 75: Frequency Band Select Register:S2 F575# Write Register 76: Nominal Carrier Frequency 1 Register:S2 F6D4# Write Register 77: Nominal Carrier Frequency 2 Register: S2 F780

Expected Results:

Figure 34. Changing TX Output Frequency

The spectrum plot shows TX output showing the frequency of unmodulated carrier changed from Yellow Trace:default (915 MHz), to Blue Trace: 917 MHz.

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6.2.6. Changing Modulation Scheme

Modulation scheme can be changed by setting the modulation mode control register.

WDS Commands: # Set FSK mode with Internal PN9 data# Write Register 71: Modulation Mode Control2 Register : # modtyp[1:0] = '10' (FSK), dtmod[1:0] = '11', internally generated PN9S2 F132

OR

# Set GFSK mode with Internal PN9 data# Write Register 71: Modulation Mode Control2 Register # modtyp[1:0] = '11' (FSK), dtmod[1:0] = '11', internally generated PN9S2 F133

Expected Results:

Figure 35. TX Spectrum for FSK and GFSK Modulation

The spectrum plot shows PN9 data with FSK/GFSK Mode, default Data Rate (41 kHz), deviation 20 KHz,Averaging ON.

Yellow Trace = FSK

Blue Trace = GFSK

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6.2.7. Change Data Rate

Transmit Data Rate can be changed by modifying the TX Data Rate 1 & TX Data Rate 0 (6E, 6F) registers.

WDS Commands:# Set Data Rate = 1.2K# Use Calculator to determine the appropriate values for the registers.# Write Register 6E: TX Data Rate 1 S2 EE00# Write Register 6F: TX Data Rate 0S2 EF4F

OR

# Set Data Rate = 100K# Use Calculator to determine the appropriate values for the registers.# Write Register 6E: TX Data Rate 1 S2 EE19# Write Register 6F: TX Data Rate 0S2 EF9A

OR

# Set Data Rate = 50K# Use Calculator to determine the appropriate values for the registers.# Write Register 6E: TX Data Rate 1 S2 EE0C# Write Register 6F: TX Data Rate 0S2 EFCD

To confirm the data rate has changed, put TX_Clk on GPIO output (refer to Section “6.2.9. Transmitting Data inSynchronous Direct Mode”). Note that TX_Clk will not be available when internal PN9 mode is used.

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6.2.8. Change Deviation

Change Frequency deviation register (72h) to set the required deviation

WDS Commands:# Change Deviation to 100KHz# Use Calculator to determine the appropriate values for the register.# Write Register 72: Frequency Deviation Register.S2 F250

OR

# Change Deviation to 12.5KHz# Write Register 72: Frequency Deviation Register.S2 F214

OR

# Change Deviation to 25KHz# Write Register 72: Frequency Deviation Register.S2 F228

Expected Results:

Figure 36. Figure 1:TX Spectrum Plot for Different Data Rates

The spectrum plot shows PN9 data with GFSK Mode, 50K Data Rate.

Yellow Trace: 50K Deviation

Blue Trace: 12.5K Deviation

Magenta Trace: 25K Deviation

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6.2.9. Transmitting Data in Synchronous Direct Mode

In this mode, the data to be transmitted is supplied to the chip from the GPIO line. The chip gives a clock output forthe microcontroller. The microcontroller must send the data synchronous to this clock.

Instructions: The following script sets GPIO0 as TX CLK and GPIO 1 as TX input data to be transmitted (PN23,PN9 data or any pattern). Connect the TX output to spectrum analyzer and observe the TX spectrum.

WDS Commands: # Apply Software Reset# Write Register 07: Operating & Function Control1 # Software Reset : set 'swres' bit to 1S2 8780

# Write Register 55: Reduce xTAL Start-#upS2 D540# Set VCO Bias CurrentS2 DA03# Set FBDIV HC and disable TX boostS2 D940# Set DIG Regulator to 1.5VS2 E602

# Fine tune the crystal to remove any offset. # Write Register 09: Crystal Oscillator Load Capacitance Register # Step through values in this register such that the TX output is at 915Mhz (±0.5 kHz)S2 897a# The PLL may also be offset to adjust frequency # Not required if AFC is enabled or wider IF Filter is used# Write Register 73, 74, 1D: Frequency Offset Register, Frequency Channel Control, AFCLoop #Gearshift Override (Disable AFC)# Step through values in this register such that the TX output is at 915Mhz (±0.5 kHz)S2 9D00S2 F300S2 F400

# Set Desired Center Frequency (950MHz)# Use Calculator to determine the appropriate values for the registers.# Write Register 75: Frequency Band Select# sbsel = '1', hbsel = '1', fb= '10111'S2 F577# Write Register 76: Nominal Carrier Frequency 1# Write Register 77: Nominal Carrier Frequency 0S2 F67DS2 F700

# Set Data Rate = 50K# Use Calculator to determine the appropriate values for the registers.# Write Register 6E: TX Data Rate 1 RegisterS2 EE0C# Write Register 6F: TX Data Rate 0 Register S2 EFCD# Set Deviation to 25KHz# Write Register 72: Frequency DeviationS2 F228

# Set GPIOs to enable synchronous direct mode of data operation# Set GPIO0 as TX Data Input for Direct Modulation# Write Register 0B: GPIO0 configuration RegisterS2 8b10# Set GPIO1 as TX Data CLK output to be used in conjunction with TX Data pin (output)

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# Write Register 0C: GPIO1 configuration RegisterS2 8C0F

# Set GFSK, synchronous direct mode of operation# Write Register 70: Modulation Mode Control 1 Register# trclk[1:0] = '01' : TX Data CLK is available via the GPIO# dtmod[1:0] = '00' : Direct Mode using TX_Data function via the GPIO pin.# modtyp[2:0] = '011' : GFSK mode.S2 F143

# Turn the transmitter ON# Write Register 07: Operating & Function Control 1 register# txon = '1'S2 8708

Expected Results:

Figure 37. TX Spectrum Plot for Synchronous Direct Mode Data Transmission

The spectrum plot shows PN9 with GFSK Mode, 50K DR, h=1, Averaging ON.

Figure 38. TX Data Rate Clock Output Configured to GPIO1

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6.2.10. Transmitting Data in Asynchronous Direct Mode

In this mode, the data to be transmitted is supplied to the chip from the GPIO line. Only FSK modulation is availablefor this mode of operation.

WDS Commands: # Set PWRDWN pin = LOWL6

# Apply Software Reset# Write Register 07: Operating & Function Control1 # Software Reset : set 'swres' bit to 1S2 8780

# Write Register 55: Reduce xTAL Start-#upS2 D540# Set VCO Bias CurrentS2 DA03# Set FBDIV HC and disable TX boostS2 D940# Set DIG Regulator to 1.5VS2 E602

# Fine tune the crystal to remove any offset. # Write Register 09: Crystal Oscillator Load Capacitance Register # Step through values in this register such that the TX output is at 915Mhz (±0.5 kHz)S2 897a# The PLL may also be offset to adjust frequency # Not required if AFC is enabled or wider IF Filter is used# Write Register 73, 74, 1D: Frequency Offset Register, Frequency Channel Control, AFCLoop #Gearshift Override (Disable AFC)# Step through values in this register such that the TX output is at 915Mhz (±0.5 kHz)S2 9D00S2 F300S2 F400

# Set Desired Center Frequency (950MHz)# Use Calculator to determine the appropriate values for the registers.# Write Register 75: Frequency Band Select# sbsel = '1', hbsel = '1', fb= '10111'S2 F577# Write Register 76: Nominal Carrier Frequency 1# Write Register 77: Nominal Carrier Frequency 0S2 F67DS2 F700

# Set Data Rate = 50K# Use Calculator to determine the appropriate values for the registers.# Write Register 6E: TX Data Rate 1 RegisterS2 EE0C# Write Register 6F: TX Data Rate 0 Register S2 EFCD

# Set Deviation to 25KHz# Write Register 72: Frequency DeviationS2 F228

# Set GPIOs to enable synchronous direct mode of data operation# Set GPIO0 as TX Data Input for Direct Modulation# Write Register 0B: GPIO0 configuration Register

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32 Rev. 0.1

S2 8b10# Set GPIO1 as TX Data CLK output to be used in conjunction with TX Data pin (output) # Write Register 0C: GPIO1 configuration RegisterS2 8C0F

# Set FSK, asynchronous direct mode of operation# Write Register 70: Modulation Mode Control 1 Register# trclk[1:0] = '01' : TX Data CLK is available via the GPIO# dtmod[1:0] = '00' : Direct Mode using TX_Data function via the GPIO pin.# modtyp[2:0] = '010' : FSK mode.S2 F102

# Turn the transmitter ON# Write Register 07: Operating & Function Control 1 register# txon = '1'S2 8708

Expected Results:

Figure 39. TX Spectrum Plot for Asynchronous Direct Mode Data Transmission

The spectrum plot shows PN9 with GFSK Mode, 50K DR, h = 1, Averaging ON.

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Rev. 0.1 33

6.2.11. Transmitting Data in FIFO Mode

WDS Command:# Set PWRDWN pin = LOWL6

# Apply Software Reset# Write Register 07: Operating & Function Control1 # Software Reset : set 'swres' bit to 1S2 8780

# Write Register 55: Reduce xTAL Start-#upS2 D540# Set VCO Bias CurrentS2 DA03# Set FBDIV HC and disable TX boostS2 D940# Set DIG Regulator to 1.5VS2 E602

# Fine tune the crystal to remove any offset. # Write Register 09: Crystal Oscillator Load Capacitance Register # Step through values in this register such that the TX output is at 915Mhz (±0.5 kHz)S2 897a# The PLL may also be offset to adjust frequency # Not required if AFC is enabled or wider IF Filter is used# Write Register 73, 74, 1D: Frequency Offset Register, Frequency Channel Control, AFCLoop #Gearshift Override (Disable AFC)# Step through different values of this register such that the TX output is at 915Mhz +/-0.5 KHz. S2 9D00S2 F300S2 F400

# Set Desired Center Frequency (950MHz)# Use Calculator to determine the appropriate values for the registers.# Write Register 75: Frequency Band Select# sbsel = '1', hbsel = '1', fb= '10111'S2 F577# Write Register 76: Nominal Carrier Frequency 1# Write Register 77: Nominal Carrier Frequency 0S2 F67DS2 F700

# Set Data Rate = 50K# Use Calculator to determine the appropriate values for the registers.# Write Register 6E: TX Data Rate 1 RegisterS2 EE0C# Write Register 6F: TX Data Rate 0 Register S2 EFCD

# Set Deviation to 25KHz# Write Register 72: Frequency DeviationS2 F228

# Set GPIOs as digital data outputs to monitor TX related signals# GPIO0, GPIO1, GPIO2 as digital test outputs# Write Register 0B: GPIO Configuration 0s2 8b0b

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34 Rev. 0.1

# Write Register 0C: GPIO Configuration 1s2 8c0b# Write Register 0D: GPIO Configuration 2s2 8d0b# Select appropriate internal digital signal. (please refer data sheet)# Write Register 51 : Digital Test Bus Select# Set Digital Test Bus to output signals at address 29H =41.# GPIO0 : data_start, GPIO1 : tx_out, GPIO2 : pk_sents2 d129

# Set TX Packet Structure # Set Transmit Header 3 value (optional)# Write Register 3A : Transmit Header 3# Set Transmit Header 3 = F0s2 baf0# Set Transmit Header 2 Value (optional)# Write Register 3B : Transmit Header 2#Set Transmit Header 2 = FFs2 bbff# Write Register 33: Header Control2 Register# select Header 3 & Header 2, Fix packet Length, 2 sync words.# txhdlen[2:0] = '010', fixpklen = '1', synclen[1:0]= '01's2 b32a# Set transmit Preamble Length# Write Register 34: Preamble Length Register# Preamble Length = 0F + 1=16 nibbles.s2 b40f# Set data access control register to enable automatic TX packet handling. If CRC is # enable, CRC byte will be added to the TX.# Write Register 30: Data Access Control Register# enpactx=1 : enable automatic packet handling of TX Path.s2 b00c

# Set TX Data Clock Configuration, Modulation source (Direct Mode, FIFO Mode, PN9), # Modulation Type (FSK, GFSK)# Write Register 71: Modulation Mode Control 2 Register# Set FIFO Mode with FSK Modulation# dtmod[1:0]= '10' : FIFO Mode, modtyp[2:0] = '010' = FSK.s2 f122

# Write data to the FIFO# Write Register 7F: FIFO Access Register# Set 1st data byte = 0Fs2 ff0f

# Turn Transmitter ON .# Write Register 07: Operating Mode & Function Control 1 Register# txon = '1's2 8708

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Rev. 0.1 35

Running this script will transmit one packet. In order to see the packet signals, run the above script with "Loop"checkbox in the WDS window checked. This will transmit multiple packets after a fixed delay. User can then triggeron the pk_sent or data_start signals to see the waveform as shown below. The user can also set the spectrumanalyzer with "Max_Hold" on to see if the packet is being transmitted.

Expected Results:

Figure 40. Internal Packet Handler Signals during TX Data Transmission

GPIO2 - Top Trace: Packet_Sent

GPIO1 - Middle Trace: TX_Out

GPIO0 - Bottom Trace: Data Start

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36 Rev. 0.1

6.3. Receiver TestingThe EZRadioPRO family can make available the data bits it receives on the GPIOs. The GPIOs are made availablethrough the loadboard's SMA connectors as shown below.

GPIO0 is available on the DATA_IN SMA connector.

GPIO1 is available on the DATA_OUT SMA connector.

GPIO2 is available on the CLK_OUT SMA connector.

The GPIO, when connected to various lab equipment, make it possible to measure RX performance characteristicssuch as sensitivity and selectivity.

Figure 41. Measurement Setup for Receiver Parameters

For BER Measurements, RX_Clk & RX_Data is configured to GPIO outputs. Connections can be made based onthe test equipment available.

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6.4. Direct Synchronous Receive ModeSetting the chip in receive mode requires a sequence of events to happen and these are shown below. In the directreceive mode, the packet handler inside the chip is not used, and all received data can be made available on theGPIO lines. Data can then be processed by the external microcontroller.

Instructions: When using the following script, the RF generator should be set to 868.3 MHz with a 50 kHz data rateand a deviation of 25 kHz. Using the RF generator and an IQ modulation/Arbitrary waveform generator, a numberof different patterns can be generated.

In general, the pattern will look like:

A preamble (4 bytes min.) + sync_word (1 byte min.) + Headers (Optional) + payload (custom data, PN9 etc.) +CRC (2 bytes optional).

In the scripts provided the pattern was:

A preamble (8 bytes) + sync_word (2 bytes) + PN9 data.

WDS Commands:#BATCHNAME 4432 RevX RX 868.3 50k-h1 #RX LO = 868.3MHz

# Set PWRDWN pin = LOWL6

# Apply Software Reset# Write Register 07: Operating & Function Control1 # Software Reset : set 'swres' bit to 1S2 8780# Write Register 55: Reduce xTAL Start-#upS2 D540# Set VCO Bias CurrentS2 DA03# Set FBDIV HC and disable TX boostS2 D940# Set DIG Regulator to 1.5VS2 E602# Write Register 62: Crystal Oscillator / Control Test# Reduces crystal startup time. (Based on measurement results)S2 E200# Deltasigma ADC Tuning 2 Register# Set Delta-Sigma ADC ref. to 0.8V# This setting gives a better dynamic range for the ADC.# adcref[2:0]= '111'S2 E803# Tune the Crystal to compensate for crystal offset.# Write Register 09: Crystal Oscillator Load Capacitance# Step through different values of this register such that the PGA / IF output is at937.5KHz# Please refer section on (Crystal Fine tuning for RX)S2 897a# The PLL may also be offset to adjust frequency # Not required if AFC is enabled or wider IF Filter is used# Write Register 73, 74, 1D: Frequency Offset Register, Frequency Channel Control, AFCLoop #Gearshift Override (Disable AFC)# Step through different values of this register such that the PGA / IF output is at937.5KHz# Please refer section on (Crystal Fine tuning for RX)#S2 9D00#S2 F300#S2 F400

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38 Rev. 0.1

# Enable AFCS2 9D40#Set AFC Band LimiterS2 F228# Set Desired Receive Frequency # Use Calculator to determine the appropriate values for the registers.# Write Register 75: Frequency Band Select# sbsel = '1', hbsel = '1', fb= '10111'S2 F573# Write Register 76: Nominal Carrier Frequency 1# Write Register 77: Nominal Carrier Frequency 0S2 F667S2 F7C0

# Enable AGC# Write Register 69: AGC Override #1# agcen = '1'S2 E920

# Set Packet Hander and thresholds# Set Preamble, Sync, CRC etc.# Write Register 30: Data Access Control Register# Set Packet Timing: # enpactx = '1' :Enable TX Packet Handling,# crc[1:0] = '00' : CRC=CCITT: S2 B080# Set Transmit Packet Length (expected receive packet length)# Write Register 3E: Transmit Packet Length. # pklen[7:0] = Set the expected length of packet to be received.S2 BE18# Set Preamble Length: Preamble length is set to max. for increasing preamble timeout.This is only # for doing BER measurements. When using actual packet reception, this valueshould be set to # expected packets preamble length.# Write Register 34: Preamble Length Register S2 B47F# Configure when to confirm if preamble is detected based on pattern matching '1010'.# Write Register 35: Preamble Detection Control Register#preath[4:0] = '00111'# When preath + 1 = 8 nibbles of preamble (sequence of 1010s) is detected, preamble detectsignal # will go Hi. S2 B538# Write Register 33: Header Control2 Register# fixpklen = '1' : Receive packet of fixed bytes.# synclen[1:0] = '01' : Set the receiver for 2 bytes of sync word detection.# Set SYNC word length=2 Bytes: Sync Word 3 & 2S2 B30A# Setting the register below will cause no sync detection and preamble detection # will be restarted after the programmed timeout. Used for test purposes only.#S2 B30E# Write Register 36: SYNC Word Byte 3S2 B62D# Write Register 37,38,39: SYNC Word Byte 2,1,0S2 B7D4S2 B8D4S2 B9D4

# Select the receiver mode (FSK/GFSK etc.)

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Rev. 0.1 39

# Set FSK/GFSK mode of reception# Set TR Data Clock out, Direct Mode data via GPIO,Modulation Mode - FSK/GFSK# Write Register 71: Operating & Function Control 1 Register# trclk[1:0] = '01' : TX Data Clk is available via the GPIO# dtmod[1:0]= '00' : Direct Mode using TX_Data function via the GPIO pin.# modtyp[1:0]= '011' : GFSK mode. S2 F143

# Select desired signals on the GPIOs# Set the Test Bus# Set GPIO to monitor PGA/IF output. IF o/p should be centered at 937.5KHz. # Write Register 0B: GPIO Configuration 0# Set GPIO0= Analog Test N OutputS2 8B0C# Write Register 50: Analog Test Bus# Set Internal Analog Test Bus to PGA/IF output. IF o/p should be centered at 937.5KHz. Ifnot, then please compensate for crystal offset (refer section x). # ATBp/n = PGA-Ip/nS2 D003# Write Register 0C: GPIO Configuration 1# Set GPIO1= Digital Test OutputS2 8C8B# Write Register 0D: GPIO Configuration 2# Set GPIO1= Digital Test OutputS2 8D8B# Write Register 51: Digital Test Bus # Set Digital Test Bus Output on GPIO's: GPIO0=Bit Clock, GPIO1=Valid # Preamble, GPIO2=RX DataS2 D136

# Set Modem according to the desired data-rate, deviation, filter BW.# Please use the EXCEL CALCULATOR to calculate the values for the following registers# Set Modem Settings# 50KBPS data rate, 25kHz dev, Mod Index=1, BW=95.3kHz# Write Register 1C: IF Filter Bandwidth# Set IF Filter Decimation Rate NDEC=3'h0# Set IF Filter Coefficient Set FILSET=4'h1S2 9C01# Write Register 20: Clock Recovery Oversampling Ratio S2 A050# Write Register 21: NCO Offset (high bits) S2 A101# Write Register 22: NCO Offset (medium bits)S2 A299# Write Register 23: NCO Offset (low bits) S2 A39A# Write Register 24: Clock Recovery Timing Loop Gain (high bits) S2 A406# Write Register 25: Clock Recovery Timing Loop Gain (low bits) S2 A568

# Write Reg. Clock Recovery Gearshift OverrideS2 9F03# Turn on the receiver#### Turn the Receiver ON# Write Register 07: Operation & Function Control 1 # rxon = '1'S2 8704

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40 Rev. 0.1

Expected Results:

Figure 42. Internal Test Signals during Reception in Direct Synchronous Receive Mode

Trace 1: Preamble Detection Signal.

Trace 2: Received Data. The packet structure shows preamble + sync_word + PN9 data used for the BERmeasurements.

Results:

At the Silicon Labs factory when the settings shown above were used, a sensitivity of –106.5 dBm @ 0.1% BERwas recorded.

If your results substantially differ then measurement setup may need to be improved or the receiver is notconfigured properly.

WDS Commands:

#BATCHNAME RX_868.3MHz_50K_h1_FIFO# Set PWRDWN pin = LOWL6

# Apply Software Reset# Write Register 07: Operating & Function Control1 # Software Reset : set 'swres' bit to 1S2 8780# Write Register 55: Reduce xTAL Start-#upS2 D540# Set VCO Bias CurrentS2 DA03# Set FBDIV HC and disable TX boostS2 D940# Set DIG Regulator to 1.5VS2 E602# Write Register 62: Crystal Oscillator / Control Test# Reduces crystal startup time. (Based on measurement results)S2 E200# Deltasigma ADC Tuning 2 Register# Set Delta-Sigma ADC ref. to 0.8V# This setting gives a better dynamic range for the ADC.# adcref[2:0]= '111'S2 E803

# Tune the Crystal to compensate for crystal offset.

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Rev. 0.1 41

# Write Register 09: Crystal Oscillator Load Capacitance# Step through different values of this register such that the PGA / IF output is at#937.5KHz# Please refer section on (Crystal Fine tuning for RX)S2 897a# The PLL may also be offset to adjust frequency # Not required if AFC is enabled or wider IF Filter is used# Write Register 73, 74, 1D: Frequency Offset Register, Frequency Channel Control, AFCLoop #Gearshift Override (Disable AFC)# Step through different values of this register such that the PGA / IF output is at937.5KHz# Please refer section on (Crystal Fine tuning for RX)#S2 9D00#S2 F300#S2 F400

# Enable AFCS2 9D40#Set AFC Band LimiterS2 F228# Set Desired Receive Frequency # Use Calculator to determine the appropriate values for the registers.# Write Register 75: Frequency Band Select# sbsel = '1', hbsel = '1', fb= '10111'S2 F573# Write Register 76: Nominal Carrier Frequency 1# Write Register 77: Nominal Carrier Frequency 0S2 F667S2 F7C0

# Enable AGC# Write Register 69: AGC Override #1# agcen = '1'S2 E920

# Set Packet Hander and thresholds# Set Preamble, Sync, CRC etc.# Write Register 30: Data Access Control Register# Set Packet Timing: # enpactx = '1' :Enable TX Packet Handling,# crc[1:0] = '00' : CRC=CCITT: S2 B080# Set Transmit Packet Length (expected receive packet length)# Write Register 3E: Transmit Packet Length. # pklen[7:0] = Set the expected length of packet to be received.# Set Packet Length (data payload length) = 6 bytesS2 BE05# Set Expected receive Preamble Length: # Write Register 34: Preamble Length Register S2 B40f# Configure when to confirm if preamble is detected based on pattern matching '1010'.# Write Register 35: Preamble Detection Control Register#preath[4:0] = '00011'# When preath + 1 = 8 nibbles of preamble (sequence of 1010s) is detected, preamble detectsignal # will go Hi. S2 B518# Write Register 33: Header Control2 Register# fixpklen = '1' : Receive packet of fixed bytes.# synclen[1:0] = '01' : Set the receiver for 2 bytes of sync word detection.# Set SYNC word length=2 Bytes: Sync Word 3 & 2

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42 Rev. 0.1

S2 B30A

# Setting the register below will cause no sync detection and preamble detection # will be restarted after the programmed timeout. Only For Test Purposes#S2 B30E# Write Register 36: SYNC Word Byte 3S2 B62D# Write Register 37, 38, 39: SYNC Word Byte 2, 1, 0S2 B7D4S2 B8D4S2 B9D4

# Select the receiver mode (FSK/GFSK etc.)# Set FSK/GFSK mode of reception# Set TR Data Clock out, Direct Mode data via GPIO,Modulation Mode - FSK/GFSK# Write Register 71: Operating & Function Control 1 Register# trclk[1:0] = '01' : TX Data Clk is available via the GPIO# dtmod[1:0]= '10' : FIFO Mode.# modtyp[1:0]= '011' : GFSK mode. S2 F163

# Select desired signals on the GPIOs# Set the Test Bus# In the current script, the test bus is not used. # ATBp/n = PGA-Ip/nS2 D003# Set Digital Test Bus Output (Not Used in current)S2 D136# Write Register 0B: GPIO Configuration 0# Set GPIO0= RX DataS2 8B14# Write Register 0C: GPIO Configuration 1# Set GPIO1= Valid Preamble DetectS2 8C19# Write Register 0D: GPIO Configuration 2# Set GPIO2= Sync Word DetectedS2 8D1b

# Set Modem according to the desired data-rate, deviation, filter BW.# 50KBPS data rate, 25kHz dev, Mod Index=1, BW=95.3kHz# Write Register 1C: IF Filter Bandwidth# Set IF Filter Decimation Rate NDEC# Set IF Filter Coefficient Set FILSETS2 9C05# Write Register 20: Clock Recovery Oversampling Ratio S2 A050# Write Register 21: NCO Offset (high bits) S2 A101# Write Register 22: NCO Offset (medium bits)S2 A299# Write Register 23: NCO Offset (low bits) S2 A39A# Write Register 24: Clock Recovery Timing Loop Gain (high bits) S2 A406# Write Register 25: Clock Recovery Timing Loop Gain (low bits) S2 A568

# Write Reg. Clock Recovery Gearshift OverrideS2 9F03# Turn on the receiver# Reset Delta-Sigma ADC

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# Write Register 67: Delta Sigma ADC Tuning 1 S2 E780# Clear Delta-Sigma ADC Reset# Write Register 67: Delta Sigma ADC Tuning 1 S2 E71C# Turn the Receiver ON# Write Register 07: Operation & Function Control 1 # rxon = '1'S2 8704

Expected Results:

Figure 43. Internal Packet Handler Signals during Packet Reception in FIFO Mode

GPIO0 - Top Trace1: Received Data

GPIO2 - Middle Trace: Sync_Detect Signal

GPIO1 - Bottom Trace: Preamble Detect Signal in FIFO Receive Mode

If packets are being transmitted in the loop mode, the following display can be observed on the oscilloscope.

Figure 44. Internal Packet Handler Signals during Continuous Packet Reception

Top Trace: RX_Data

Bottom Trace: Preamble Detect Signal in continuous reception

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44 Rev. 0.1

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