web viewsome machines have automatic saving of user visible registers on subroutine call. ......

COA Question Paper Ms. Vincy Joseph

Class: SE CMPNA&B

Subject: Computer Architecture and Organization

Module III

1. Describe the register organization within CPU (10 Marks)

Register Organization

• The registers in the processor performs two roles:

1. User Visible Registers :

– Minimize main memory references by optimizing use of registers

2. Control and Status Registers:

– Used by control unit to control the operation of processor and some OS to control execution of program.

User Visible Registers

• Referenced by means of machine language

• They are categorized as :

– General Purpose

– Data

– Address

– Condition Codes

• General Purpose Registers

– Can be assigned to a variety of functions by programmer

– Can contain operand for any opcode

– Can be dedicated registers for stack and floating point.

– Can be used for addressing functions


• Data Registers: Used only to hold data and cannot be used for operand address calculation

• Address Registers

• They may be general purpose or devoted to an addressing mode

– Example:

• Segment Pointers: holds base address of segment

• Index Registers: for indexed addressing

• Stack Pointer: points to the top of stack.

• Condition Codes (Flags)

– They are bits set by the processor hardware as the result of operations

– E.g. Carry,Overflow,Sign

– They may be tested as part of conditional branch operation

– Condition code bits are collected into one or more registers and the programmer cannot alter them.

Advantages of Condition Codes

• They reduce the number of compare and test needed

• Conditional instructions are simplified

• They facilitate multi-way branches

Disadvantages of Condition Codes

• They add complexity to hardware and software

• They are irregular and requires extra hardware connections

• Condition code machines have to add non-condition code instructions for special situations


• In pipelined computers synchronization is required to avoid conflict

Design Issues with Registers

• General purpose or specialized registers:

– Specialized Register : Operand is specified implicit

• E.g. PUSH and POP in Stack

– Specialization limits programmer’s flexibility

• No. of registers to be provided

– More registers requires more operand specifier bits

– Between 8 and 32 is optimum for CISC processors

– Fewer will result in more memory references.

• Issue of Register Length

– Must be long enough to hold

• the largest address and

• most of the data types

• Saving of User Registers:

– Some machines have automatic saving of user visible registers on subroutine call

– Some machines leave the responsibility to the programmer

Control and Status Registers

• Control Registers : Four registers essential for instruction execution are

– Program Counter


– Instruction Register

– Memory Address Register

– Memory Buffer Register

• Program Counter(PC)

– It contains the address of the next instruction to be fetched

– Processor updates PC after instruction fetch

– A branch or skip instruction modifies the content of PC

• Instruction Register (IR)

– It contains the instruction most recently fetched

– In IR, the opcode and operand specifiers are analyzed.

• Memory Address Register

– It contains the address of a location in memory

– In a bus organized system, MAR is directly connected to the address bus

• Memory Buffer Register

– It contains a word of data to be written into memory or the word

recently read

– MBR connects directly to data bus in a bus organized system

– User visible registers exchange data with MBR.

– ALU have direct access to MBR and user visible registers

• Status Register– A register or set of registers that contain status information is called

Program Status Word (PSW)

– PSW contains condition codes and other status information

– PSW contains flags like :

• Sign: Sign bit of last arithmetic operation


• Zero: Set when result is 0.

• Carry: Set when a carry/borrow is generated /taken.

– PSW contains :

• Equal: set when a logical compare result is equality

• Overflow: Indicates arithmetic overflow

• Interrupt Enable/Disable: Used to enable / disable interrupts

• Supervisor: Indicates whether processor is executing in

supervisor/user mode. Certain privileged instructions and

certain areas of memory can be accessed only in supervisor

mode.

• Other Registers– Process Control Block Pointer: points to a block of memory

containing additional status information

– Interrupt vector register : holds interrupt vector

– system stack pointer : points to a stack to implement certain

functions like subroutine call

2. Explain in detail the different types of addressing modes(10

Marks)

Addressing Modes

• It defines how to specify operands.

• The most common addressing modes are:

– Immediate


– Direct

– Indirect

– Register

– Register Indirect

– Displacement (Indexed)

– Stack

Immediate Addressing

• Operand is present in the instruction

• e.g. ADD 5 // Add 5 to contents of accumulator

• It can be used to define and use constants or set initial values of variables.

• Adv:

– Faster access as no memory reference to fetch data

• Disadv:

– Size of the number is limited to the size of address field

Direct Addressing

• Address field contains effective address of operand

• e.g. ADD A

– Look in memory at address A for operand

• Adv:

– Single memory reference to access data


– No additional calculations to work out effective address

• Disadv: Limited address space

Indirect Addressing

• Memory cell pointed by address field contains the address of (pointer to) the operand

• EA = (A)

– Look in A, find address (A) and look there for operand

• e.g. ADD (A) // Add contents of cell pointed by accumulator

• Adv:

– Large address space (2n where n = word length)

– May be nested, multilevel, cascaded


• e.g. EA = (((A)))

• Disadv: Multiple memory accesses to find operand and hence slower

Register Addressing

• Address field refers to a register

• EA = R

• Adv:

– Only a small address field is needed in the instruction

– Less access time

• Disadv:

– Limited number of registers

– Limited address space

Register Indirect Addressing

• Similar to indirect addressing

• EA = (R)

• Operand is in memory cell pointed to by contents of register R

• One fewer memory access than indirect addressing


Displacement Addressing

• Combines direct and register indirect addressing

• EA = A + (R)

• Address field hold two values

– A = base value

– R = register that holds displacement

– or vice versa

Stack Addressing

• Stack is a reserved block of locations

• Stack pointer holds the address of the top of the stack.


• It is a form of implied addressing: as no memory reference is required but operate on the top of the stack

3. Explain with diagram the working of the Hardwired Control Unit (10

Marks)4. Describe Hardwired Control Unit and specify its advantages

(10 Marks)In this, the control unit is essentially a state machine circuit.The input logic signals are transformed into a set of output logic signals, which are the control signals. It uses a fixed logic circuits to generate control signals

• Instruction Register– Uses opcodes to perform different actions for different

instruction• Decoder


– There should be unique logic input for each opcode – It is done by decoder (n-bits 2n outputs ,each will activate

a single unique output)– Decoder becomes complex for variable length opcodes

• Clock– It issues repetitive pulses to execute micro-operations.

• Timing generator– At the end of each subcycle, the timing generator is

reinitialized to generate new T1

• Control Unit Logic– It defines how it produces output control signals as function

of input signals– For each control signal , a boolean expression is derived

• Modern processors result in large number of boolean expressions and implementing combinatorial circuits are extremely difficult.

• Hence simpler microprogramming approach is used

Advantages

• Works faster as combinational circuits generates control signals based on input status.

Disadvantages

• Complex in design if it requires larger number of control points

• No flexibility : difficult to make corrections or add a new feature

• Uses too many logic gates.


5. Explain Wilke’s Engine in detail (10 Marks) It was introduced in 1951 To store microprogram, it should contain rapid access storage

device and hence a diode matrix is used.

For any micro-operation, we need to configure the diodes in the matrix.

During a machine cycle, one row of matrix is activated with a pulse. This generates signals at those points where diode is present

• First part generates control signals• Second part generates the next address of the row to be pulsed


• Each row is one microinstruction• Layout of matrix is control memory• At the beginning of cycle, Register 1 contains the address of the

row to be pulsed• Register 1 is fed to decoder which when activated by clock pulse,

activates one row• The first part generate control signals & second part generate next

address which is fed into RegisterII• Register II is gated to Register I by a clock pulse• Application of pulses alternatively to decoder and gate connecting

Register I and II causes a predetermined sequence of microinstrucitons to be executed

• It is similar to Horizontal, the major differences are• CAR could be incremented by 1 in HM, but next address is

contained in Wilkes Scheme• To permit branching , a row must contain two parts

controlled by a conditional signal in Wilkes.6. Explain with diagram the functioning of microprogrammed control

unit (10 Marks) It executes a set of microinstructions are stored in control

memory Control Address Register (CAR)

o Contains address of next microinstruction to be reado Similar to MAR

Control Buffer Register (CBR)o Contains control word of the currently executing

microinstruction Sequencing Logic Unit

o It loads CAR and issues a READ command


Functioning of Micro-programmed CU

1. To execute an instruction, the sequencing logic unit issues a READ command to the control memory.

2. The content of the address specified in CAR is read into CBR

3. CBR generates control signals and next address information for the sequencing logic unit.

4. Sequencing logic unit loads a new address into CAR based on the next-address information from CBR and the ALU flags.


Calculating Next Address

• Depending on the value of ALU flags and CBR, one of three decisions is made:

– Get the next instruction:

• CAR CAR +1

– Jump to a new routine based on a jump microinstruction:

• Load the address field of CBR into CAR.

– Jump to a machine instruction routine:

• Load the CAR based on the opcode in the IR.

Two Decoders

• Upper Decoder: translates the opcode of the IR into CAR

• Lower decoder : used only for vertical microinstructions

– In a vertical microinstruction, a code is used for each action to be performed and the decoder translates this code into individual control signals

Adv. Of Micro-programmed CU

• Simpler to design

• Cheaper

• Less Prone to Error

• Less logic required for sequencing and decoding

• Easy to implement

Disadv. : Slower in performance


7. Explain microinstruction sequencing and execution(10

Marks)

Sequencing Technique

• Based on the format of address information in the microinstruction, it is classified into 3 categories:

– Two Address Fields

– Single Address Field

– Variable Format

Two Address Fields


• Address-selection signals are provided by branch logic module (It has inputs of control unit flags and control bits from microinstruction)

• Multiplexer has inputs of both address fields and instruction register.

• Based on address- selection input, multiplexer transmits either opcode or one of two addresses to CAR.

• CAR produce the next microinstruction address

• ADV: Simple

• DISADV: more bits required in microinstruction

Single Address Field


• With this approach, the options for next address are as follows:

• Address field

• Instruction Register code

• Next sequential address

• Address-selection input determine which option is selected.

• Adv: reduces the number of address fields to one.

• Disadv: Address field is not used often which cause inefficiency in the microinstruction coding

scheme.

Variable Format


• Provide for two entirely different microinstruction formats and one bit designates which format is being used.

• In one format, the remaining bits activate control signals.

• In other format, some bits drive branch logic module and remaining bits provide the address.

• With first format, the next address is either sequential address or address derived from IR.

• With second format, either a conditional or unconditional branch is specified.

• Disadvantage:

• one entire cycle is consumed with each branch microinstruction.


• With other approaches, address generation occurs as part of the same cycle.

Microinstruction Execution

• Each microinstruction cycle is made up of two events

– Fetch

• Determined by generation of microinstruction address

– Execute

• Effect of Execute is to generate control signals

– Some control points are internal

– Some go to external control bus or other interface

8. Write short note on microinstructions to execute MOV [R1], R2(06

Marks)The control sequence is :t1: MAR (R1)t2: MBR (memory)t3: R2 (MBR)The first microinstruction moves the content of R1 to MAR. This moves the address of the location in memory which is contained in R1 to MAR .The second microinstruction is to read the content of memory. Here the address in MAR is given to read from the memory. The data in the memory location identified by MAR is stored to MBR.The third microinstruction moves the data fetched from memory contained in MBR to R2.

9. What are the applications of microprogramming (03 Marks)


1. In Realization of control unit: Microprogramming is used widely now for implementing the control unit of computers

2. In Operating system: Microprograms can be used to implement some of the primitives of operating system. This simplifies operation system implementation and also improves the performance of the operating system.

3. In High-Level Language support: In High-Level language various sub functions and data types can be implemented using microprogramming. This makes compilation into an efficient machine language form possible.

4. In Microdiagnostics: Microprogramming can be used for detection isolation monitoring and repair of system errors. This is known as microdiagnostics and they significantly enhance system maintenance.

5. In User Tailoring: By using RAM for implementing control memory (CM), it is possible to tailor the machine to different applications.

6. In Emulation: Emulation refers to the use of a microprogram on one machine to execute programs originally written for another machine. This is used widely as an aid for users in migrating from one computer to another.

10. Write short note on Nanoprogramming (05 Marks)

Nano-programming

• In this method, microinstructions does not generate control signals directly but uses a second control memory called Nano Control Memory (NCM)

• There are two levels of control memory:

– higher level Micro Control Memory &

– lower level NCM that stores nano-instructions


• Suppose there are n = 2048 micro-ops each of 41 bits wide,

• The memory required for single control ROM is 2048 x 41 =83,968 bits

• Suppose there are 100 unique control words in ROM.

• These 100 words can be uniquely saved in nano control ROM saving space as shown:


• Advantage:

– Reduces total size of required control memory

– Greater design flexibility

• Disadvantage: Less speed due to two level memory

11. What are the differences between RISC and CISC processors (05

Marks)12. Compare RISC and CISC processors (05 Marks)


13. Explain features of RISC and CISC processors (10 Marks)

Complex Instruction Set Computers

• CISC processor mostly uses a unified cache for both data and instructions and shares the same path


• They mostly use microprogrammed CU and hence control memory is required and it slows down the execution

• It tries to simplify the compilation and improve the overall computer performance.

– CISC architecture attempt to provide a single machine instruction for every statement in a high-level language.

• It incorporates variable-length instruction formats.

– Packing variable instruction formats in memory requires special decoding circuits.

• Instructions manipulate operands in memory

• Uses a variety of addressing modes—from 5 to 20

• Uses a large number of instructions—from 100 to 250

• Includes specialized instructions which are used infrequently

• Examples : Motorola 68000 family, Intel x86 CPUs-Pentium

Reduced Instruction Set Computers

• It uses separate instruction and data caches and their access paths are different

• It uses hardwired control unit and hence faster execution.


• Uses a small set of instructions with register-to-register operations and simple load and store operations for memory.

• Uses only a few addressing modes

• Follows a simple instruction format

– instruction length is fixed and aligned on word boundaries.

• Instructions are easy to decode.

• Execute one instruction per clock cycle

– Includes pipelining

– Load or store may require two clock cycles.

• Uses a large number of registers

– overlapped register windows speed-up procedure call and return.

– Thus register-to-memory operations is minimized

• Examples : SPARC, Alpha,...

web viewsome machines have automatic saving of user visible registers on subroutine call. ......

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