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An example of positive feedback op amp circuit: Schmitt Trigger

In real OA imperfections cause Vd to have a small value: If Vd > 0 VO If Vd < 0 VO

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Lets assume VSUPPLY = 5V

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Op Amp Imperfections a. Voltage Supply Limits (Saturation)

For a real op amp, clipping occurs if the output voltage reaches certain limits.

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b. Output Current Limit (Short-Circuit Output Current ISC) The current that an op amp can supply to a load is limited (typically

+/-25 mA) If a small-value load draw a current outside the limit, the output

waveform becomes clipped Example:

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Ideally, This means, the op amp should provide 205 mA, which is higher than the 25mA the op amp can really issue. In practice: Thus, as soon as the output voltage reaches 2.44 V (which corresponds to an input voltage of 2.44/4 0.61 V) the output voltage gets clipped.

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Example:

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In this case the OA has no problem to provide the current required to produce an output voltage up to 20V. Unfortunately, as soon as the value of Vo gets larger than 12V (which correspond to an input voltage value of Vin =12/4 = 3V), the output is still going to be clipped. This time the reason is not the OA current limit, but the OA supply limit. Because of that, the max current that the op amp is really going to provide is only:

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c. CMRR

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d. Non Linearity

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e. DC offset voltage Offset is caused by the fact that the internal circuit of the op amp experiences fabrication mismatches.

As a result the op amp is not perfectly balanced, i.e.:

VO0 when Vin1=Vin2

Offsets arise from input stage mismatch and cause the input-output characteristic to shift in either the positive or negative direction (the plot displays positive direction). We model the offset by a single voltage source placed in series with one of the inputs. Since offsets are random can be positive or negative, Vos can appear at either input with arbitrary polarity.

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Why are DC offsets important? Can cause unacceptable accuracy errors Can cause saturation

Example: Effects of DC offset (Accuracy Error)

The op amp amplifies the input as well as the offset, creating errors. Lets assume we have a weighting station that uses an electronic pressure meter whose output is amplified by the circuit shown, and the pressure meter generates 20mV for every 100 Kg. If the op amp has an offset of Vos = 2mV, this correspond to an error of 10Kg. Example: Effects of DC offsets (Saturation)

( )osinout VVRRV +

+=

2

11

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The first op amp has an offset of 2 mV. What happens at the output? A1 = 1 + 104/102 100 A2 = 1 + 104/102 100 Av = Vout/Vin = A1 A2 104

The first stage will amplify the offset by a factor of 100 generating a DC level of 200 mV at node X. At this point, the second stage amplifies VX by another factor of 100, attempting to generate Vout=20V. Since the op amps have a supply voltage of 3V the Vout cannot exceed this value and the second op amp will saturate. Example: effects of DC offsets on the ideal integrator (saturation)

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In other words, the circuit integrates the offset, generating an output that tends to + (in reality the positive supply voltage) or (in reality the negative supply voltage) depending on the sign of Vos. It is worth to notice that if we model the offset placing a voltage source in series with the negative input instead of the positive input the specific formulae may change but the physical effect is the same.

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To avoid the saturation problem caused by the offset, we can modify the integrator circuit as follow:

The idea is to place a resistor in parallel with the capacitor to absorb the offset. Since Vos is a DC its effect at the output is given by: For example if Vos = 2mV and R2/R1=100, then Vout contains a dc error of 202 mV, but at least does not saturate.

However, the presence of R2 also affects the integration function. The closed-loop transfer function has no longer has a pole at origin. Now the circuit contains a pole at 1/(R2C1) 1

1

121

2

+=

sCRRR

VV

in

out

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In summary:

R2/R1 must be sufficiently small to minimize the effect of the offset

R2C1 must be sufficiently large so as to negligibly impact the input signal frequencies of interest

Commonly used offset voltage nulling circuits

Universal offset voltage balancing schemes: It is possible to build many reasonable balancing circuits. Few examples follow. (a) Inverting Configuration

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For R3 >> R1: Thus: (b) Non Inverting configuration

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Alternative scheme:

(c) Mixed configuration

In general, there are many reasonable balancing circuits that can be built.

Ad-Hoc offset voltage balancing schemes:

Many op-amp manufacturers provide extra terminal for offset nulling.

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General Offset Nulling Procedure:

1. build the circuit you want to implement 2. put the input terminals to ground 3. move the POT wiper until Vout is zero

NOTE: offset balancing is usually done after the circuit has been working for a couple of hours!!! f. Input Bias (=DC) Currents In order for the op amp to operate the two input transistors of differential stage have to be biased. As a result there may be dc currents flowing into the inputs of the op amp:

For op amps implemented in bipolar technology there is always a dc base current drawn (0.1-1 A) from each input

For op amp implemented in MOS technology there almost no dc currents.

The input bias currents create inaccuracies in the circuits. The error due to the input bias currents appear similar to the dc voltage offset effect (i.e., corrupt the output of the op amp). However, unlike the dc voltage offset, this phenomenon is not random. The effect of bipolar base currents can be modeled as current sources tied from the input to ground.

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Usually two parameters are specified to describe this op amp imperfection:

The average value of IB1 and IB2

The expected difference

a. Effect of the dc input currents on the non inverting configuration

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Setting Vin=0 (no signal applied) the circuit reduces as follows:

Since the + terminal is at ground then the node X is at virtual ground. As a result there is a zero voltage across R2, which means no current will flow through R2, so all current IB2 flows through R1:

Vout = IB2R1 The error due to the bias current appears similar to the dc voltage offset effect. Then, a reasonably simple method for canceling this error seems to be the application of a DC correction voltage in series with the positive terminal.

122

11 RIRRVV Bcorrout +

+=

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In order to produce a zero output it must be: In other words: If we assume that nominally IB1=IB2 obtaining Vcorr and canceling the effect of the bias currents for the non inverting amplifier becomes quite simple:

122

110 RIRRV Bcorr +

+=

21 BB II =

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b. Effect of the dc input currents on the inverting configuration

Canceling the effect of the bias currents for the non inverting amplifier c. Effect of bias currents on the unity gain amplifier and its cancellation

There is no effect on the non inverting configuration (thus no need for cancellation)

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d. Effect of bias currents on the summing amplifier and its cancellation

e. Effect of input bias currents on integrator

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Since IB2 is a DC current it will flow all through R1:

Input bias current will be integrated by the integrator and eventually saturate the amplifier. If we assume that IB2=IB1 by placing a resistor in series with the positive input, integrator input bias current can be cancelled.

( ) =t

Bout dtRICRV

012

11

1

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In reality, the output still saturates due to other effects such as the DC voltage offset, mismatch between IB1 and IB2, and mismatch between the resistors. To avoid saturation we can use the non ideal integrator circuit:

In this case the presence of R2 makes the op amp work in closed loop for the DC. As a result the negative input is at virtual ground, so all IB2 will flow in R2.

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* Detailed analysis of the error caused by the DC bias currents: A straightforward way of assessing the effect of the input bias currents is to find the output with all input signals set to zero. To analyze in detail the effect of the error caused by the DC bias currents, lets consider the inverting configuration: Expand (**):

2BNBP

BIII +=

BNBPOS III =

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Substitute (*) in: Lets now consider:

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Lets now substitute in (): And if we impose RP = R1||R2 the term involving IB will be eliminated, leaving: Which is a quite small quantity since it is proportional to IOS (IOS = IPIN 0)

OSO IRRRRV

+= )||(1 21

2

1

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g. Speed Limitations Finite Bandwidth (Small Signal Speed) Slew Rate (Large Signal Speed)

Finite Bandwidth (Small Signal Speed)

Because of its internal capacitances, the gain of the op amp begins to fall as the frequency of operation exceeds a certain break value.

The internal circuitry of the op amp can be modeled (approximated) by a first-order (one pole) system:

( )

1

0

21

21)(

)(

fs

AsVsVs

VVV

d

out

inin

out

+

==

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At frequencies well below the break frequency (s/1 > 1): and since the op amp gain falls to unity at u: Having a loop around the op amp (inverting, non-inverting, etc) helps to increase the bandwidth of the system, however, it also decreases the gain (Bandwidth and Gain Tradeoff) Non-inverting Amplifier Example: (Bandwidth Gain Tradeoff)

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Graphically:

In conclusion: we can trade gain for bandwidth and vice versa

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Slew Rate (Large Signal Speed) Slew rate is a non linear phenomenon. Lets consider a non inverting configuration and its small signal voltage transfer function:

Then for simplicity, lets make the configuration into a voltage follower (R2=):

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Applying to the input of a follower a voltage step of sufficiently small amplitude VP will result in an exponential response: The rate at which Vout changes with time is highest at the beginning of the exponential transition. If we increase VP the rate at which the output slews will have to increase accordingly. In practice, we observe that the rate at which the output voltage changes (i.e. the output slope) cannot exceed a certain limit called the slew rate (= SR).

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If the input is small (linear region), when the input doubles then the output and the output slope also double. However, when the input is large, the op amp slews.

Slew rate limiting is a non linear effect due to the limited ability of the internal circuitry to charge or discharge the internal capacitance.

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As long as the input step amplitude VP is sufficiently small, the op amp will respond in proportion (i.e., linearly) and yield: However, if we overdrive the op amp applying a large input voltage, the Iout will saturate at ITAIL. Then the capacitor C will become current starved and the speed of the op amp is further limited.

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The non linearity effect of slew rate can also be observed by applying a large sine wave to the circuit.

+=

2

1

max

1RRV

dtdV

Pout

tRRV

dtdV

Pout cos1

2

1

+=

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As long as the output slope is less than the slew rate, the op amp can

avoid slewing. However, as operating frequency and/or amplitude is increased, the

slew rate becomes insufficient and the output becomes distorted. Full-Power Bandwidth (FP)

To determine the maximum frequency before op amp slews, we assume the op amp produces its maximum allowable voltage swing without saturating (worst case scenario). If the op amp provides a slew rate of SR: Then in conclusion:

2sin

2minmaxminmax VVtVVVout

++

=

2minmax VV

SRFP =

2minmax

max

VVdtdVSR out ==

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h. Finite Gain, Finite Input Impedance and non-zero Output Impedance Actual op amps do not provide infinite gain, infinite input impedance (MOS based op amps have a very high input impedance at low frequencies), and non-zero output impedance.

The effect of these limitations is to increase the gain error of the circuit.

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Lets consider the effects of finite gain, finite input impedance, and non-zero output impedance on a non-inverting configuration: Voltage Gain Derivation:

Nid vvv =

21 Rv

Rvv

rvv NNOd

Ni =

+

1

0

Rvv

rvAv NO

O

dO =

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Matlab Code: clear all; close all; clc; syms Vout Vin VN Rd Ro R1 R2 Ao Vd; s = solve( (Vin-VN)/Rd+(Vout-VN)/R1-VN/R2,(Vout-Ao*(Vin-VN))/Ro-(Vout-VN)/R1,Vin,Vout); Vin = s.Vin; Vout = s.Vout; AV=Vout/Vin; fprintf('AV = '); pretty(AV); IdealAV = limit(AV,Ao,inf); disp('IdealAV = '); pretty(IdealAV); AV = Rd R1 Ao - R2 Ro + Rd R2 Ao ------------------------------------------------ R1 R2 + Rd R2 + Rd R1 - Rd Ro - R2 Ro + Rd R2 Ao IdealAV = R1 + R2 ------- R2

i

OV v

vA =

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Input Resistance Derivation:

Matlab Code: clear all; close all; clc; syms VN Rd Ro R1 R2 Ao; % Ax = b ; x(1) = Vt, x(2) = It A = [1 -Rd ; 1/Rd+Ao/(R1+Ro) 0]; b = [VN ; VN*(1/Rd+1/R2+Ao/(R1+Ro)+1/(R1+Ro))]; x = A\b; Rin = x(1)/x(2); disp('Rin = '); pretty(Rin); IdealRin = limit(Rin,Ao,inf); disp('IdealRin = ') pretty(IdealRin); R2 R1 + R2 Ro + Rd R1 + Rd Ro + Ao Rd R2 + Rd R2 Rin = ------------------------------------------------ R1 + Ro + R2 signum(Rd) signum(R2) Inf IdealRin = ------------------------- signum(R1 + Ro + R2)

i

iin i

vR =

0)(

1

0

2

=+

+

o

NNiN

d

Ni

rRvvvA

Rv

rvv

d

Nii r

vvi =

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Output Resistance Derivation:

0)01

=

=o

NxdNxx r

vvvARvvi

)||(|| 221

RrRrRvvv dd

NxN +

=

Nd vv =

x

xout i

vR =

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Matlab Code: clear all; close all; clc; syms Vd VN Ix Vx Ro R1 Rp Ao s = solve('Vd=-VN', 'Ix +(-Ao*VN-Vx)/Ro-(Vx-VN)/R1 = 0', 'VN=Vx*Rp/(R1+Rp)', 'Vd', 'Ix', 'Vx'); Vx = s.Vx; Ix = s.Ix; Rout=Vx/Ix; fprintf('Rout = '); pretty(Rout); IdealRout = limit(Rout,Ao,inf); disp('IdealRout = '); pretty(IdealRout); Rout = (R1 + Rp) Ro -------------------- R1 + Rp Ao + Rp + Ro IdealRout = 0

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Example 8.16 A student has an OA with Ao=10000, Rout=1 and want to design an inverting amplifier with R1=50 and R2=10. The amplifier fails to provide the output swing of 2V we need. Why? _____

40 mA is a quite big current and many op amps provide only a very small output current

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Example 8.17 Design an inverting amplifier with a nominal gain of 4 a gain error of 0.1% and a nominal input impedance of at least 10K. ______

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In conclusion: Thus: Just for the record, it can be shown that the |% Gain Error| for the non inverting configuration is also given by (1+R1/R2)/A0

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Example 8.18 Design a non-inverting amplifier with the following spec.: closed loop gain = 5, gain error = 1%, closed loop BW = 50 MHz. Assume the op amp has IBIAS=0.2A. Determine the required open loop gain and BW of the OA. _______

The choice of R1 and R2 depends on the driving capability (output resistance) of the OA.

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The BW is given by:

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Example 8.19 Design an integrator for a unity gain frequency 10MHz and an input impedance of 20K. If the OA provides a slew rate of 0.1V/ns, what is the largest peak-to-peak sinusoidal swing at the input at 1MHz that produces an output free from slewing? ______

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For a sinusoidal input Vin = Vpcos t: Then in order for the OA to do not slew it must be SR VP/(R1C1):

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