week 7 low-power modes msp430 teaching materials hacettepe university copyright 2009 texas...

Week 7

Low-Power Modes

MSP430 Teaching Materials

Hacettepe University

Copyright 2009 Texas Instruments All Rights Reserved

2 Copyright 2009 Texas Instruments

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Low-Power Modes

One of the main features of the MSP430 families: Low power consumption Important in battery operated embedded systems.

Low power consumption is only accomplished: Using low power operating modes design; Depends on several factors such as:

• Clock frequency;• Ambient temperature;• Supply voltage;• Peripheral selection;• Input/output usage;• Memory type;• ...


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Low power modes (LPM): 6 operating modes; Configured by the SR bits: CPUOFF, OSCOFF, SCG1, SCG0. Active mode (AM) - highest power consumption:

Active mode: MSP430 starts up in this mode, which must be used when the CPU is required, i.e., to

run code An interrupt automatically switches MSP430 to active Current can be reduced by running at lowest supply voltage consistent with the

frequency of MCLK, e.g. VCC to 1.8V for fDCO = 1MHz

• Configured by disabling the SR bits described above;• CPU is active;• All enabled clocks are active;• Current consumption: 250 A.

Low-Power Modes

Software selection up to 5 LPM of operation;

Operation:

• An interrupt event can wake up the CPU from any LPM;• Service the interrupt request;• Restore back to the LPM.


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Low-Power Modes

Low-Power Modes

• Low power modes (LPM):• Example: Typical current consumption (41x family).

Low-Power Modes

Low-Power Modes


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Low power modes (LPM):

Mode Current SR bits configuration Clock signals Oscillator

[A] CPUOFF OSCOFF SCG1 SCG0 ACLK SMCLK MCLK DCO DC gen.

Low-power mode 0 (LPM0) 35 1 0 0 0 1 1 0 1 1

Low-power mode 1 (LPM1) 44 1 0 0 1 1 1 0 1 1*

Low-power mode 2 (LPM2) 19 1 0 1 0 1 0 0 0 1

Low-power mode 3 (LPM3) 0.8 1 0 1 1 1 0 0 0 0

Low-power mode 4 (LPM4) 0.1 1 1 1 1 0 0 0 0 0

*DCO’s DC generator is enabled if it is used by peripherals.


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Low power operating modes

Low power modes (LPM) characteristics: LPM0 to LPM3: Periodic processing based on a timer interrupt;

• LPM0: CPU and MCLK are disabled, SMCLK and ACLK remain active. Both DCO source signal and DCO’s DC generator are active. This is used when the CPU is not required but some modules require a fast clock from SMCLK and the DCO

• LPM1: Main difference to LPM0 is the condition of enable/disable the DCO’s DC generator;

• LPM2: DCO’s DC generator is active and DCO is disabled;• LPM3: CPU, MCLK, SMCLK, and DCO are disabled; only ACLK remains active (< 2

μA). This is the standard low-power mode when the device must wake itself at regular intervals and therefore needs a (slow) clock. It is also required if the MSP430 must maintain a real-time clock.

LPM4:• The device can be wakened only by an external signal.• No clocks are active and available for peripherals.• Reduced current consumption (0.1 μA).


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Low power operating modes


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Through four bits in status register (SR) in CPU SCG0 (System clock generator 0): when set, turns off DCO, if DCOCLK is

not used for MCLK or SMCLK SCG1 (System clock generator 1): when set, turns off the SMCLK OSCOFF (Oscillator off): when set, turns off LFXT1 crystal oscillator, when

LFXT1CLK is not use for MCLK or SMCLK CPUOFF (CPU off): when set, turns off the CPU All are clear in active mode

Low power modes (LPM) selection:


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How to put in LPM

bis.w #LPM3 ,SR ; enter LPM3 but can we wake again?

bis.w #GIE|LPM3 ,SR ; enter LPM3 with interrupts enabled

This cannot be done in standard C, of course, and an intrinsic function is required. The function that follows is taken from intrinsics.h and sets both the low-power and GIE bits:

_low_power_mode_3 (); // enter LPM3 with interrupts enabled


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Low power operating modes (6/11)

Program flow steps: Enter Low-power mode:

• Enable/disable CPUOFF, OSCOFF, SCG0, SCG1 bits in SR;• LPM is now active after writing to SR!• CPU will suspend the program execution;• Disabled peripherals:

– Peripherals operating with any disabled clock;– Individual control register settings.

• All I/O port pins and RAM/registers are unchanged;• Wake up is now possible through any enabled interrupt.


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MCLK and Low-Power Mode

An interrupt is needed to awaken the MSP430. The processor handles an interrupt from a low-power mode

in almost the same way as in active mode. The only difference is that MCLK must first be started so that the CPU can handle the interrupt; this replaces the first step when the CPU is active, which is to complete the current instruction.

MCLK is started automatically by the hardware for servicing interrupts and requires no intervention from the programmer. Remember that the status register is cleared when an interrupt is accepted, which puts the processor into active mode.

Similarly, MCLK is automatically turned off at the end of the ISR if the MSP430 returns to a low-power mode when the status register is restored.


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Program flow steps: An enabled interrupt event wakes the MSP430; Enter ISR:

• The operating mode is saved on the stack during ISR;• The PC and SR are stored on the stack;• Interrupt vector is moved to the PC;• The CPUOFF, SCG1, and OSCOFF bits are automatically reset, enabling

normal CPU operation;• Corresponding IFG flag cleared on single source flags.

Returning from the ISR:

• The original SR is popped from the stack, restoring the previous operating mode;

• The SR bits are restored from the stack returning to a different operating mode after RETI instruction.


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Examples of applications development using the MSP430 with and without low power modes consideration: Example Without low power mode With low power mode

Toggling the bit 0 of port 1 (P1.0) periodically

Endless loop(100 % CPU load)

LPM0Timer interrupt

UART to transmit the received message at a 9600 baud rate

Polling UART receive(100 % CPU load)

UART receive interrupt(0.1 % CPU load)

Set/reset during a time interval, periodically, of the peripheral

connected to the bit 2 of port 1 (P1.2)


Setup output unit(Zero CPU load)

Power manage external devices like Op-Amp

Putting the OPA Quiescent(Average current: 1 A)

Shutdown the Op-Amp between data acquisition

(Average current: 0.06 A)Power manage internal devices like

Comparator AAlways active

(Average typical current: 35 A)Disable Comparator A between data

acquisition

Respond to button-press interrupt in P1.0 and toggle LED on P2.1


Using LPMs while the LED is switch off:

LPM3: 1.4 ALPM4: 0.3 A

Configure unused ports in output direction

P1 interrupt service routine


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// timintC1.c - toggles LEDs with period of about 1.0s// Toggle LEDs in ISR using interrupts from timer A CCR0// in Up mode with period of about 0.5s// Timer clock is SMCLK divided by 8, up mode , period 50000// Olimex 1121STK , LED1 ,2 active low on P2.3,4// J H Davies , 2006 -10 -11; IAR Kickstart version 3.41A// ----------------------------------------------------------------------#include <io430x11x1.h> // Specific device#include <intrinsics.h> // Intrinsic functions// ----------------------------------------------------------------------// Pins for LEDs#define LED1 BIT3#define LED2 BIT4// ----------------------------------------------------------------------void main (void)

WDTCTL = WDTPW|WDTHOLD; // Stop watchdog timerP2OUT = ˜LED1; // Preload LED1 on , LED2 offP2DIR = LED1|LED2; // Set pins with LED1 ,2 to outputTACCR0 = 49999; // Upper limit of count for TARTACCTL0 = CCIE; // Enable interrupts on Compare 0TACTL = MC_1|ID_3|TASSEL_2|TACLR; // Set up and start Timer A// "Up to CCR0" mode , divide clock by 8, clock from SMCLK , clear timer__enable _interrupt (); // Enable interrupts (intrinsic)for (;;) // Loop forever doing nothing // Interrupts do the work

// ----------------------------------------------------------------------// Interrupt service routine for Timer A channel 0// ----------------------------------------------------------------------#pragma vector = TIMERA0_VECTOR__interrupt void TA0_ISR (void)

P2OUT ˆ= LED1|LED2; // Toggle LEDs

// timintC1.c - toggles LEDs with period of about 1.0s// Toggle LEDs in ISR using interrupts from timer A CCR0// in Up mode with period of about 0.5s// Timer clock is SMCLK divided by 8, up mode , period 50000// Olimex 1121STK , LED1 ,2 active low on P2.3,4// J H Davies , 2006 -10 -11; IAR Kickstart version 3.41A// ----------------------------------------------------------------------#include <io430x11x1.h> // Specific device#include <intrinsics.h> // Intrinsic functions// ----------------------------------------------------------------------// Pins for LEDs#define LED1 BIT3#define LED2 BIT4// ----------------------------------------------------------------------void main (void)

WDTCTL = WDTPW|WDTHOLD; // Stop watchdog timerP2OUT = ˜LED1; // Preload LED1 on , LED2 offP2DIR = LED1|LED2; // Set pins with LED1 ,2 to outputTACCR0 = 49999; // Upper limit of count for TARTACCTL0 = CCIE; // Enable interrupts on Compare 0TACTL = MC_1|ID_3|TASSEL_2|TACLR; // Set up and start Timer A// "Up to CCR0" mode , divide clock by 8, clock from SMCLK , clear timer__enable _interrupt (); // Enable interrupts (intrinsic)for (;;) // Loop forever doing nothing

__low_power_mode_0 (); // Enter LPM0 // Interrupts do the work

// ----------------------------------------------------------------------// Interrupt service routine for Timer A channel 0// ----------------------------------------------------------------------#pragma vector = TIMERA0_VECTOR__interrupt void TA0_ISR (void)

P2OUT ˆ= LED1|LED2; // Toggle LEDs


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Assembly version

interrupts from Timer_A. The device enters low-power

mode 0 between interrupts.

InfLoop:

bis.w #LPM0|GIE ,SR ; this is added

; Enable ints and low power mode 0

jmp InfLoop ; Infinite loop (should never happen)


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; timrint1.s43 - toggles LEDs with period of about 1s; TACCR0 interrupts from timer A with period of about 0.5s; Timer clock is SMCLK divided by 8, up mode , period 50000; Olimex 1121STK , LED1 ,2 active low on P2.3,4;-----------------------------------------------------------------------#include <msp430x11x1.h> ; Header file for this device;-----------------------------------------------------------------------; Pins for LED on port 2LED1 EQU BIT3LED2 EQU BIT4;-----------------------------------------------------------------------RSEG CSTACK ; Create stack (in RAM);-----------------------------------------------------------------------RSEG CODE ; Program goes in code memoryReset: ; Execution starts heremov.w #SFE(CSTACK),SP ; Initialize stack pointermain: ; Equivalent to start of main() in Cmov.w #WDTPW|WDTHOLD ,& WDTCTL ; Stop watchdog timermov.b #LED2 ,& P2OUT ; Preload LED1 on , LED2 offbis.b #LED1|LED2 ,& P2DIR ; Set pins with LED1 ,2 to outputmov.w #49999 ,& TACCR0 ; Period for up modemov.w #CCIE ,& TACCTL0 ; Enable interrupts on Compare 0mov.w #MC_1|ID_3|TASSEL_2|TACLR ,& TACTL ; Set up Timer A; Up mode , divide clock by 8, clock from SMCLK , clear TARbis.w #GIE ,SR ; Enable interrupts (just TACCR0)jmp $ ; Loop forever; interrupts do all;-----------------------------------------------------------------------; Interrupt service routine for TACCR0 , called when TAR = TACCR0; No need to acknowledge interrupt explicitly - done automaticallyTA0_ISR: ; ISR for TACCR0 CCIFGxor.b #LED1|LED2 ,& P2OUT ; Toggle LEDsreti ; That's all: return from interrupt;-----------------------------------------------------------------------COMMON INTVEC ; Segment for vectors (in Flash)ORG TIMERA0_VECTORDW TA0_ISR ; ISR for TA0 interruptORG RESET_VECTORDW Reset ; Address to start executionEND

interrupts from Timer_A. The device enters low-power mode 0

InfLoop:bis.w #LPM0|GIE ,SR ; this is added ; Enable ints and low power mode 0jmp InfLoop ; Infinite loop (should never happen)


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We could save more power by using low-power mode 3 rather than mode 0. Two small changes are needed. The TASSEL bits in TACTL must be adjusted so that the timer runs from ACLK rather than SMCLK. Then the MCU can be put into LPM3 instead of LPM0 between interrupts.


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Returning from a Low-Power Mode to the Main Function

Sometimes it is not appropriate to carry out all actions in an ISR and it is better to return to the main function in active mode. To be more precise, this means returning to the function that put the device into the low-power mode.

In this case we must clear all the low-power bits in the saved value of SR on the stack before it is restored at the end of the interrupt service routine. This sounds alarming but is actually straightforward, particularly in C because an intrinsic function _ _low_power_mode_off_on_exit()

is available to do the job.


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Part of program to toggle LEDs using interrupts from Timer_A. The device enters low-power mode 0, is awakened by an interrupt and returns to the main function to toggle the LED.

for (;;) // Loop forever__low_power_mode_3 (); // Enter low power mode LPM3// Wait here , pace loop until timer expires and ISR restores

Active ModeP2OUT ˆ= LED1|LED2; // Toggle LEDs

// ----------------------------------------------------------------------// Interrupt service routine for Timer A channel 0// Processor remains in Active Mode after ISR// ----------------------------------------------------------------------#pragma vector = TIMERA0_VECTOR__interrupt void TA0_ISR (void)__low_power_mode_off_on_exit(); // Restore Active Mode on return


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The main function is now like the paced loop of except that the processor goes to sleep and waits to be awakened by an interrupt from the timer instead of polling the overflow flag. In fact _ _low_ power_mode_3() behaves just like a simple delay function. The ISR is trivial and contains only one line for the intrinsic function to clear the stacked low-power mode.

The more general function _ _bic_SR_register_on_exit() can be used to clear selected bits in SR if finer control is required.

It is also called _BIC_SR_IRQ().


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Part of program timain1.s43 to toggle LEDs using interrupts from Timer_A. The device enters low-power mode 0, is awakened by an interrupt and returns to the main function to toggle the LED.

InfLoop:bis.w #LPM3|GIE,SR ; Enable interrupts and enter LPM3

; Wait here, pace loop until timer expires and ISR restores Active Mode

nop ; Helps debugging

xor.b #LED1|LED2 ,& P2OUT ; Toggle LEDs

jmp InfLoop ; Infinite loop

;------------------------------------------------------------------

; Interrupt service routine for TACCR0 , called when TAR = TACCR0

; No need to acknowledge interrupt explicitly - done automatically

TA0_ISR: ; ISR for TACCR0 CCIFG

bic.w #LPM3 ,0(SP) ; Delete LPM3 on exit: Active Mode

reti ; That's all: return from interrupt


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Input/0utput Interfacing

Up to ten 8-bit digital Input/Output (I/O) ports, P1 to P10 (depending on the MSP430 device);

I/O ports P1 and P2 have interrupt capability;

Each interrupt for these I/O lines can be individually configured: To provide an interrupt on a rising or falling edge; All interruptible I/O lines source a single interrupt vector.

The available digital I/O pins for the hardware development tools: eZ430-F2013: 10 pins - Port P1 (8 bits) and Port P2 (2 bits); eZ430-RF2500: 32 pins - Port P1 to P4 (8 bits); Experimenter’s board: 80 pins – Port P1 to P10 (8 bits).


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Each I/O port can be:

Programmed independently for each bit;

Combine input, output, and interrupt functionality;

Edge-selectable input interrupt capability for all 8 bits of ports P1 and P2;

Read/write access to port-control registers is supported

Individually programmable pull-up/pull-down resistor (2xx family only).



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The port pins can be individually configured as I/O for special functions, such as:

USART – Universal Synchronous/Asynchronous Receive/Transmit for serial data;

Input comparator for analogue signals;

Analogue-to-Digital converter;

Others functions (see specific datasheet for details).



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Registers (1/6)

Independent of the I/O port type (non-interruptible or interruptible), the operation of the ports is configured by user software, as defined by the following registers:

Direction Registers (PxDIR):

• Read/write 8-bit registers;• Select the direction of the corresponding I/O pin, regardless of the selected

function of the pin (general purpose I/O or as a special function I/O);• For other module functions, must be set as required by the other function.

• PxDIR configuration:

Bit = 1: the individual port pin is set as an output;Bit = 0: the individual port pin is set as an input.


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Registers (2/6)

Input Registers (PxIN):

• When pins are configured as GPIO, each bit of these read-only registers reflects the input signal at the corresponding I/O pin;

• PxIN configuration:

Bit = 1: The input is high;Bit = 0: The input is low;

• Tip: Avoid writing to these read-only registers because it will result in increased current consumption.


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Registers (3/6)

Output Registers (PxOUT):

• Each bit of these registers reflects the value written to the corresponding output pin.

• PxOUT configuration:

Bit = 1: The output is high;Bit = 0: The output is low.

– Note: the PxOUT Register is read-write. This means that the previous value written to it can be read back and modified to generate the next output signal.


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Registers (5/6)

Function Select Registers: (PxSEL) and (PxSEL2):

• Some port pins are multiplexed with other peripheral module functions (see the device-specific datasheet);

• These bits: PxSEL and PxSEL2 (see specific device datasheet), are used to select the pin function:

– I/O general purpose port;– Peripheral module function.

• PxSEL configuration:

Bit = 0: I/O Function is selected for the pin;Bit = 1: Peripheral module function enabled for pin.


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Interruptible ports (P1 and P2) (1/2)

Each pin of ports P1 and P2 is able to make an interrupt request;

Pins are configured with additional registers:

Interrupt Enable (PxIE):

• Read-write register to enable interrupts on individual pins;

• PxIE configuration:

Bit = 1: The interrupt is enabled;Bit = 0: The interrupt is disabled.

• Each PxIE bit enables the interrupt request associated with the corresponding PxIFG interrupt flag;

• Writing to PxOUT and/or PxDIR can result in setting PxIFG.


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Interruptible ports (P1 and P2) (2/2)

Interrupt Edge Select Registers (PxIES):

• Selects the transition on which an interrupt occurs (if PxIE and GIE are set);

• PxIES configuration:

Bit = 1: Interrupt flag is set on a high-to-low transition;Bit = 0: Interrupt flag is set on a low-to-high transition.

Interrupt Flag Registers (PxIFG)

• Set automatically when a programmed signal transition (edge) occurs;• PxIFG flag can be set and must be reset by software.

• PxIFG configuration:

Bit = 0: No interrupt is pending;Bit = 1: An interrupt is pending.


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Interrupts on Digital Inputs Ports P1 and P2 can request an interrupt when the value on an input changes.

This is one of the few interrupts that remains active in LPM4 and is therefore useful to wake the CPU in portable equipment that lies idle for a long time

Interrupts for port P1 are controlled by the registers P1IE and P1IES, and similarly for port P2. There is a single vector for each port, so the user must check P1IFG to determine the bit that caused the interrupt. This bit must be cleared explicitly; it does not happen automatically as with interrupts that have a single source.

The direction of the transition that causes the interrupt can be changed in P1IES at any time by the program. This is useful if both edges of a pulse need to be detected, for example, when a button is pressed and released. There is a danger that spurious interrupts may be generated, so it is a good idea to disable this interrupt, change P1IES, and clear any spurious flags in P1IFG before reenabling the interrupt!


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// butled4.c - press button B1 to light LED1// Responds to interrupts on input pin , LPM4 between interrupts// Olimex 1121 STK board , LED1 active low on P2.3,// button B1 active low on P2.1// J H Davies , 2006 -11 -18; IAR Kickstart version 3.41A// ----------------------------------------------------------------------#include <io430x11x1.h> // Specific device#include <intrinsics.h> // Intrinsic functions// ----------------------------------------------------------------------void main (void)

WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timerP2OUT_bit.P2OUT_3 = 1; // Preload LED1 off (active low!)P2DIR_bit.P2DIR_3 = 1; // Set pin with LED1 to outputP2IE_bit.P2IE_1 = 1; // Enable interrupts on edgeP2IES_bit.P2IES_1 = 1; // Sensitive to negative edge (H->L)do P2IFG = 0; // Clear any pending interrupts ... while (P2IFG != 0); // ... until none remainfor (;;) // Loop forever (should not need)__low_power_mode_4 (); // LPM4 with int'pts , all clocks off // (RAM retention mode)

// ----------------------------------------------------------------------


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// Interrupt service routine for port 2 inputs// Only one bit is active so no need to check which// Toggle LED , toggle edge sensitivity , clear any pending interrupts// Device returns to low power mode automatically after ISR// ------------------------------------------------------------------#pragma vector = PORT2_VECTOR__interrupt void PORT2_ISR (void)

P2OUT_bit.P2OUT_3 ˆ= 1; // Toggle LEDP2IES_bit.P2IES_3 ˆ= 1; // Toggle edge sensitivitydo

P2IFG = 0; // Clear any pending interrupts ... while (P2IFG != 0); // ... until none remain


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Multiplexed Inputs: Scanning a Matrix Keypad

Many products require numerical input and provide a keypad for the user. These often have 12 keys, like a telephone, or more. An individual connection for each switch would use an exorbitant number of pins so they are usually arranged as a matrix instead. Only seven pins are needed for a 12-key pad, or eight pins for 16 keys.

As usual this economy comes at a price. The matrix must be scanned, which is more complicated than reading individual inputs. Moreover, the reading may become ambiguous if more than one key is depressed


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There are, as usual, many ways of dealing with a keypad. Here is a straightforward approach, although it needs refinement in practice. Do not worry about debouncing at this stage and assume that no more than one switch is closed.

Connect the rows Y1–Y4 as inputs to the microcontroller while the columns X1–X3 are driven by outputs. (It could equally well be the other way around.) Pull-up resistors are required on the inputs. These could be internal for the MSP430F2xx family but must be provided externally for other devices


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1. Drive X1 low and the other columns X2 and X3 high. This makes the switches in column X1 active and the corresponding Y input goes low if a button is pressed. Thus we can detect the state of switches 1, 4, 7, or *. The switches in the other columns have no effect because both of their terminals are at VCC.

2. Drive X2 low and the other columns high to read the switches in column X2.

3. Repeat this for column X3. 4. This process can be repeated as often as required


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A problem with this simple method arises if two buttons, such as 1 and 2, are pressed, which short-circuits the column drives X1 and X2. This damages the output of the microcontroller if they are connected directly. Resistors should therefore be connected between the pins of the microcontroller and the columns of the keypad.


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It is a waste of energy to scan the keypad when no button is being pressed. In this case it is more efficient to drive all

columns low and wait for an interrupt generated by a falling edge on any of the row inputs.

The keypad can then be scanned to determine which key has been pressed.


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Often in applications with keypads, the condition can occur where a key can be held or stuck down, causing excess current consumption and reducing the battery life of a battery-operated product.

This application report shows a solution. The keypad interface in this report, based on the MSP430, draws .1uA while waiting for a key press, is completely interrupt driven requring no polling, and consumes a maximum of only 2uA at 3V if all keys are pressed and held simutaneously.

See Implementing an Ultralow-Power Keypad Interface with the MSP430

http://www.ti.com/lit/an/slaa139/slaa139.pdf

http://www.ti.com/lit/an/slaa139/slaa139.pdf


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Implementing an Ultralow-Power Keypad Interface

• 100 nA typical current consumption while waiting for key press• 2 µA maximum current consumption if all keys are held

simultaneously• No polling required• No crystal required• Minimum external components• Suitable for any MSP430 device


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Implementing an Ultralow-Power Keypad Interface

The rows of the keypad are connected to port pins P3.0 – P3.3. The columns are connected to pins P1.0 – P1.2. Connecting the rows to port 3 pins, instead of port 1 pins, leaves the other port 1 pins for other interrupt sources, because the P1 pins have interrupt capability, but the P3 pins do not.

In normal mode, while the circuit is awaiting a key press (wait-for-press mode), the rows are driven high (1), and the P1.x column pins are configured as inputs, with interrupts enabled and set to interrupt on a rising edge. The 4.7 MΩ pulldown resistors hold the inputs low in this state. The MSP430 is then put into low-power mode 4, where the MSP430 current consumption is about 100nA. This state is maintained indefinitely until a key is pressed. The circuit is completely interrupt-driven with no need for polling.


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After a key has been pressed, the MSP430 goes into a wait-for-release mode in which it drives high only the necessary row for the key being pressed (other rows are driven low).

It reconfigures the P1.x I/O lines to interrupt on a falling edge, and it goes back into low power mode 4, waiting for the release of the key. Again, there is no polling necessary at this point. The detection of the key release is completely interrupt driven allowing the microcontroller to stay asleep while the key is held, thus reducing current consumption.

Once the key is released, the debounce delay is again executed. After the debounce delay, the keypad is scanned again to determine if any other keys are being held. If so, the wait-for-release mode continues, waiting for all keys to be released. When all keys are released the MSP430 goes back to the wait-for-press mode again.


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During the wait-for-release mode, only one row of the keypad is driven high, therefore limiting the maximum amount of current consumption to the condition where all three keys on a single row are pressed and held. For a 3-V system, that equates to about 2 µA. Any other key press does not result in increased current consumption because the corresponding row is not driven high.

In this 3×4 keypad example, the rows are driven rather than the columns to limit the maximum current consumption by the circuit when all keys are pressed and held simultaneously. Had the columns been driven instead, the rows would have had the pulldown resistors, therefore increasing the number of paths to ground when all the keys are held and increasing the possible current consumption.

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