welcome to engn3213 2010! digital systems and...

Welcome to ENGN3213 2010!Digital Systems and

Microprocessors

1 ENGN3213: Digital Systems and Microprocessors L#1-2

Contact Details

➤ Lecturer: Gerard Borg

➤ email: [email protected]

➤ RSISE B148. ph. 6125 8567

➤ Revamped Webpage: http://engnet.anu.edu.au/DEcourses/engn3213

➤ WATTLE: http://wattle.anu.edu.au

➤ Tutors Lab demonstrators: Rais Ahmed, Dhammika Amarasinghe and PatBernardi


The Course

➤ No assumed knowledge but uses a novel abstraction level approach thatwill be mandatory for complex designs

➤ Both WATTLE and WEB based

➤ Strongly lab and design oriented course and assessed accordingly

➤ There is one three hour session of either a CLAB (Computer lab or tutorial)or a HLAB (hardware lab) each week

➤ There will be an individual project requiring a report of length ≤ 30 pagesto be submitted at the end of semester. Choice of two projects for 2010

➤ Assessment, 10% CLAB Quizzes, 20% Labs, 30% Exam and 40%Project


Overview of Resources

➤ Text book - Katz and Boriello (Contemporary Logic Design, Prentice Hall) -some in bookshop

➤ Lectures recorded

➤ There will be a reading brick with lab notes (eventually)

➤ Reading material on the web site is quite extensive

➤ Course is strong on both hardware and software

➤ Experience in FPGA and micro(processor) development boards,electronics, software and hardware testbenches, firmware


Reading Material On the WEBSITE

Reading material at http://engnet.anu.edu.au/DEcourses/engn3213/Documents➤ The detailed tour of the course (next lecture).

➤ Download it for tomorrow’s lecture and follow along while taking notes.Important to understand the approach taken in the course

➤ Datasheets and manuals for Xilinx FPGAs and ARM processors

➤ PICOBLAZE softcore manuals: hardware manual (xapp213.pdf) and Ccompiler (pccomp manual.pdf)

➤ Several documents on Finite State Machines (FSMs), Register TransferLevel (RTL) Design, switch debouncing and VERILOG HDL etc


Labs

➤ A CLAB is a computerised tutorial. HLABs are hands on digital design labsrequiring a notebook

➤ CLABS will be held in COP (Copeland) G020

➤ HLABs will be conducted in IR (Ian Ross) 103 and are assessed during thelabs

➤ All CLABS have assessable quizzes at the beginning of the lab.

➤ In all labs you work alone

➤ Due to a lack of PC work stations in HLABs, students with lapto ps arestrongly encouraged to bring these along

➤ Students must reuse old designs in labs and the project. KEEP YOUROLD DESIGNS AND DOCUMENT THEM WELL

➤ HLABs assessed on your notebook documentation and the succe ssof your designs.


Lab Availability

➤ The CLABS and HLABS are conducted in alternate weeks and in differentlocations - Ian Ross 103 might be available during CLAB weeks.

➤ This depends on the availability of a demonstrator and other uses forIR103. Hours are limited to office hours 9:00-17:00

➤ There will also be a CLAB and a HLAB dedicated specifically to the project.

➤ If you wish to use the labs out of the regular lab times then please contactme at least one week in advance.

➤ Alternatively you can buy your own hardare and work at home.


Hardware Lab Rules

➤ Do prelab work before coming to the HLABs

➤ You must keep a neat and simple lab notebook that documents the date,notes, results and nomenclature of your filing system

➤ No food, no drink in the labs and no bags etc in the aisles

➤ It will not be possible to recover marks for missed labs

➤ Save your own files to a flash drive - each student will need their ownflash drive (worth up to 5 marks every lab)

➤ Delete your computer files and clean up your work area before you leave

➤ Turn off equipment


Software

➤ We use FREE and OPEN SOURCE software that you can and mustuse on your home or laptop PCs

➤ All the software can be downloaded fromhttp://engnet.anu.edu.au/DEcourses/engn3213/Software

➤ DVD can be made available


Software used in the course: Xilinx ISE WebPACK 9.2i

➤ An application from Xilinx that is a complete design suite for Xilinx FPGAsincluding simulation, synthesis and device download.

➤ ISE WebPACK can be downloaded from the Xilinx website www.xilinx.com(≈ 3GB) and installed for free.

➤ ISE WebPACK is the course work horse. It is crucial for you to h ave apersonal copy for home use

➤ ISE WebPACK has XST Simulator - a GUI style simulator with signal traces

➤ Mastering ISE is the minimal technical achievement of the course

➤ Downside - only for WINDOWS (and maybe MAC)


Software used in the course: ICARUS Verilog and GTKwave

➤ ICARUS Verilog is a very popular open source command line tool forLINUX and WINDOWS. http://www.icarus.com/eda/verilog

➤ Also allows you to simulate VERILOG. The output can be dumped to a textfile for analysis. This is all we will use it for

➤ You should obtain a copy of ICARUS VERILOG for yourself and st artplaying with it immediately - much less computer overhead th an ISEWebPACK .

➤ ICARUS Verilog is a command line tool and CYGWIN (the unix shell forwindows) has been installed on IC and IR computers.

➤ You can use ICARUS VERILOG with the WINDOWS CMD prompt .

➤ GTKwave is an open source tool that allows ICARUS output to bedisplayed as traces (logic state analyser)


Software used in the course: C and Assembly Language Program ming

➤ XAPP213 is the tool suite needed to create the PICOBLAZE embeddedmicroprocessor softcore in SPARTAN FPGAs. It contains the KCSMPPICOBLAZE assembly language to VHDL compiler.

➤ PCCOMP is a C-compiler for PICOBLAZE. It compiles C-code intoPICOBLAZE assembly language

➤ picoblazeIDE is a simulation environment for PICOBLAZE.

➤ XAPP213, PCCOMP and picoblazeIDE do not need installation and arenot installed on the uni computers. Download these from the coursewebsite and take them to labs

➤ There is also the MinGW C-compiler for WINDOWS

➤ MinGW is only for C programming practice. It is not otherwise used in thecourse

➤ Keil compiler for ARM (?)


Hardware

➤ We use the Spartan 3E Development board.http://www.digilentinc.com/Products/Detail.cfm?Prod =S3EBOARD

➤ The board includes an XC3S500E FPGA. Peripherals include PS/2,switches, buttons, LEDs, LCD, LDC, DAC, VGA port.

➤ There is an electronic expansion breadboard for the inclusion of userhardware.

➤ The ARM2368 controller:http://www.futurlec.com/ARM2368Controller.shtml

➤ Manuals on course website.


The Spartan 3E Development Board


The ARM2368 Development Board


Course Approach

➤ We learn digital design via a block hardware abstraction app roach

➤ What does that mean?

➤ A small number of hardware units are modelled by a ’Verilog mo delfor synthesis’ or ’a block schematic’

➤ What does that mean?


Hardware Block Abstractions (I)

We develop models for the following entities.

➤ A combinational block - a device that responds instantaneously to inputs

➤ A sequential block - a device that responds to inputs only at the tick of aclock (they have memory)

➤ A Finite State Machine - a simple electronic model of controller or a HiddenMarkov System (consists of one sequential bank and two combinationalbanks - various models)

➤ A Datapath - a circuit that performs a mathematical algorithm (can consistof combinational or sequential sub-blocks)

➤ A Register Transfer Level (RTL) system - a circuit involving a FSM and adatapath


Hardware Block Abstractions (II)

➤ We will assume that all hardware can be treated as an interconnection ofthese fundamental models and that all systems can be built by connectinga set of Verilog modules or schematics together

➤ In addition we will assume that all hardware is clock synchronous.Asynchronous designs are not permitted in this course (although wewill visit them)

➤ We therefore use pipelining

➤ A flagship RTL example will guide us in our thinking - The MU0microprocessor softcore

➤ MU0 will allow us to transition to the PICOBLAZE softcore

➤ From there transition from gates to programming


Course Summary

1. Course overview2. Course overview hosted by microprocessor MU0 (I)

3. Course overview hosted by microprocessor MU0 (II)4. Numbers5. Verilog HDL

6. Digital system components using schematics and Verilog7. Combinational logic abstraction. Karnaugh maps

8. Combinational ccts and configurable logic devices9. Simple Sequential circuit abstraction - synchronous versus asynchronous

10. Sequential circuits, counters, registers, memories11. Non-ideal effects in digital circuits

12. Finite State Machines13. Design of FSMs14. Datapath abstraction

15. Design of Datapaths16. Register Transfer Level System (RTL) abstraction

17. Design of RTLs18. The PICOBLAZE Softcore

19. Assembly Language programming20. C programming

21. ARM microprocessors (I)22. ARM microprocessors (II)


MU0 Data Path Diagram


The Project (I)

➤ A major source of marks for the course.

➤ Each student will hand in an individual 30 page report at the end ofsemester.

➤ The project will consist of the complete digital design and implementationof a complex digital system.

➤ Everyone writes an individual report about their original work.


The Project (II)

➤ The project will be implemented on the SPARTAN 3E boards using onlydigital logic - No IP Cores, no multipliers. Set up a User Constraints File

➤ Project specifications will be provided by me by Week 3 (next week)

➤ The RTL Design of MU0 in lectures will be the best early indicator of themagnitude of the project, although the project will also have gradedmilestones.

➤ Make sure that you download and study the MU0 design (includi ngthe Verilog implementation) on the ENGN3213 website

➤ You should start as soon as possible


The Project (A): A reverse polish calculator

➤ A complex RTL system

➤ Design and build a calculator to take characters from a keyboard overPS/2, perform reverse polish calculations in the Spartan 3E FPGA anddisplay results on an LCD.

➤ Milestone driven assessment


The Project (A): A reverse polish calculator

Key Holding Register (KHR)

Arithmetic Logic Unit

Stack OutStack In

FSM

Input

Output

ResetkeyID from KB interface

Display

Output

Output

Input

interface


The Project (B): A wireless acoustic transceiver

➤ A complex datapath project

➤ Design and build a transceiver to take commands from a keyboard overPS/2, perform DSP in the Spartan 3E FPGA to transmit and receivecharacters acoustically and display characters transmitted on a VGAmonitor.

➤ Milestone driven assessment


The Project (B): Echoceiver: A wireless acoustic transceiv er


Course Outcomes

➤ Use top-down design to translate system requirements into a practicaldigital design.

➤ Design complex digital systems and implement these in programmablelogic.

➤ Learn fixed point arithmetic.

➤ Learn how to program in C and VERILOG HDL.

➤ Learn to use ISE WebPACK to realise complex digital designs in FPGAs.

➤ Learn about other free and open source design software.

➤ Learn practical electronics testbench skills and the ability to communicateappropriately via a lab notebook.

➤ Learn to build and use microprocessors


Example of a Real World Digital System

➤ The following viewgraphs show the block diagram (Data path ) of a terrestrial DVB (Digital Video Broadcast)transmitter

➤ The system as shown in the diagram is all digital and could be implemented in FPGA.

➤ If so implemented then the configuration could be modified and reloaded. Such an implementation wouldconstitute a Software Defined Radio

➤ Two particular system blocks have been highlighted:

➤ The Transport Multiplexer is a data scrambler . Its job is to randomise the data stream. This device hasthe property that repassing the scrambled data through the device reconstitutes the original datastream. There are identical data scramblers at the transmitter and the receiver.

➤ The second subsystem is the inner encoder . It is a convolutional encoder that imbues the datastream with memory as a result of a tapped delay line. By memory one means that the data symbol atany symbol time is dependent upon the values of previous data symbols. Such memory can beexploited by a convolutional decoder in order to achieve forward error correction . The algorithm inuse for convolutional decoding in modern DVB receivers is the Viterbi algorithm .


DVB-T Transmitter Block Diagram (ETSI EN 300 744 V1.4.1 (200 1-01))

(ETSI = European Telecommunications Standards Institute)


DVB-T ETSI EN 300 744 V1.4.1 (2001-01) (ctd)

The system is defined as the functional block of equipment performing theadaptation of the baseband TV signals from the output of the MPEG-2transport multiplexer, to the terrestrial channel characteristics. The followingprocesses shall be applied to the data stream (see figure 1):➤ transport multiplex adaptation and randomization for energy dispersal;➤ outer coding (i.e. Reed-Sol omon code);➤ outer interleaving (i.e. convolutional interleaving);➤ inner coding (i.e. punctured convolutional code);➤ inner interleaving;➤ mapping and modulation;➤ Orthogonal Frequency Division Multiplexing (OFDM) transmission.

The system is directly compatible with MPEG-2 coded TV signals ISO/IEC13818 [1].


DVB-T Transport Multiplexer (ETSI EN 300 744 V1.4.1 (2001-0 1))

To ensure adequate binary transitions, the data of the input MPEG-2 multiplexshall be randomized in accordance with the configurations depicted below.


DVB-T Inner Coder (ETSI EN 300 744 V1.4.1 (2001-01))

The system shall allow for a range of punctured convolutional codes, based ona mother convolutional code of rate 1/2 with 64 states.
