What are the Benefits of Area Constraints?

Create effective Area Constraints using PlanAhead tool

Identify Floorplanning Methodologies

Avoid the most common design and synthesis mistakes during floorplanning

Gain timing closure with the PlanAhead™ tool

Place the dedicated hardware resources

Objectives

Definition of Floorplanning (Area Constraints)

In the past, the term “ Floorplanning” meant to make placement constraints on CLB logic (assign it to specific locations)

– The term “ floor planning“ in the ASIC world still means to place (assign) gates in a specific location on an array

– Floorplanning is NOT necessary in an FPGA but can help to improve timing

Xilinx recommends the use of area constraints, rather than the use of placement constraints

– However, this does require some skill

Floorplanning is now commonly referred to as “placing Area constraints”

– So whenever you see “Floorplanning” we mean “Area Constraints”

Reasons to Floorplan with Area Constraints

Floorplanning is considered when the design has not met timing or does not meet timing consistently

Floorplanning condenses and contains critical logic to improve performance

Reduce routing congestion– Isolate non-critical logic– Create a data flow-based floorplan

Use unique Pblock capabilities in the PlanAhead tool

– Improve module-level performance and area– Improve implementation run time and consistency with

Partitions

Design and Synthesis Recommendations

Set up your synthesis tool to preserve the hierarchy in the netlist

– Flattened netlists may be optimal from a synthesis perspective, but they make it very difficult to reliably floorplan and constrain placement

Structure the RTL logic so that critical timing paths are confined to individual modules

– Critical paths that span large numbers of hierarchical modules can be difficult to floorplan

Register the outputs of all the modules to help limit the number of modules involved in a critical path

Replicate the drivers of nets that will be separated on the die

– Synthesis may need an attribute to preserve equivalent logic

Design and Synthesis Recommendations

Intermingled critical paths can be difficult to floorplan– Consider dividing large critical blocks into smaller and separate

hierarchical blocks

If the design is expected to change often, consider an incremental approach to synthesis

– In an incremental approach, individual blocks can be synthesized separately or the synthesis attributes (SYN_HIER=HARD) can be used to preserve the hierarchy

– Hierarchy preservation helps an incremental flow but may hurt performance because global optimizations across hierarchy are disabled

Design and Synthesis Recommendations

Consider using the synthesis option to rebuild the hierarchy– For XST, use –netlist_hierarchy = rebuilt– If using the PlanAhead tool for synthesis, the PlanAhead tool default

synthesis strategy includes this option

Long paths in single large hierarchical block can make floorplanning difficult

– Divide large hierarchical blocks in the RTL

Re-Use Flow Methodology

Can help a design that meets timing only some of the time– The idea is to re-use some of the block RAM and DSP slice placements

from a successful implementation

Synthesize the design

Run implementation many times with only timing constraints and pin assignments

Choose the result that has met timing and had the fastest implementation time

– Fix the placement of the block RAMs and DSP slices • Either by manually placing them or using the Find command• With a little experience you may want to manually place them

Re-implement as needed

Hierarchical Methodology

Synthesize the design

Run implementation with only timing constraints and pin assignments

If it fails to meet timing (many paths fail across many components)– Make the area constraints based on the highest levels of your design hierarchy

• Possibly constrain the entire design

Ask yourself these questions– What are the timing failures?– What are the critical hierarchical blocks?– Are changes to the floorplan or critical logic going to be sufficient to meet

timing?– Does anything else need to be floorplanned?– Can just the critical hierarchies be floorplanned?– Where should my logic be placed?

Placement of Dedicated Resources

Placing dedicated hardware is a terrific strategy– The implementation tools do not always do the best job– Consider placing block RAMs and DSP slices– This works well when you make area constraints

• Placement of dedicated resources guides the implementation tools to move CLB logic closer

• to the desired location• Place area constraints near the I/O pins and

dedicated hardware you plan to use

Block RAM

Block RAM

Where are the Dedicated Hardware Resources?

Virtex-6 FPGAsSpartan-6 FPGAs

150K Logic Cell

Device

760K Logic Cell

Device

Common Resources

3.3 Volt Compatible I/O

Hardened Memory Controllers

LUT-6 CLB

DSP Slices

Block RAM

HSS Transceivers*

Parallel I/O FIFO Logic

System Monitor

Tri-Mode EMAC

PCIe® Interface

High-performance Clocking

Assigning LOC Constraints

Most logic objects can be manually assigned to a specific site

Click the Create Site Constraint Mode toolbar button (to place)

– Note that placed logic has a blue bar

Logic is easily found with the Find command and then dragged to be placed

– Cursor indicates legal placement sites– Right-click allows you to un-place

Assigning BEL (Basic Elements) Constraints

Click the Create BEL Constraint Mode toolbar button

Drag a LUT or FF primitive from the Find menu or Netlist view onto a specific slice

– Primitives with LOC constraints are displayed in the Netlist view with blue striped icons

Click the Assign Instance Mode toolbar button to return to floorplanning mode

LOC Constraint Applications

To clear LOC constraints– Select Tools > Clear Placement

– Many options to selectively clear LOCs

– Separate controls for I/O ports

– Importing an implementation result leaves the logic

unfixed

– Importing LOCs from a UCF file is considered manually

assigned and remains placed

Right-click a placed object to Fix Instances (LOC)

– I/O interfaces or cores, for example

– Lock down non-slice-based logic (block RAMS,

or DSP, for example)

– Maximize module performance and consistency

– Export constraints with File > Export Constraints

Summary

Area constraint guidelines– Use the timing report to identify logic to floorplan– Leverage the implementation results to guide placement of area

constraints

Placement of dedicated resources can guide the implementation tools

– Be sure to make an area constraint with the associated logic and assign it near the dedicated hardware to improve performance

– Placement improves implementation consistency between each iteration

More Information

To learn more, visit the PlanAhead tool web site– www.xilinx.com/planahead– Articles, documentation, white papers, and training enrollment

User Guide– PlanAhead Software Tutorial, Design Analysis and Floorplanning for

Performace, UG676– Floorplanning Methodology Guide, UG633

View the PlanAhead tool video demonstrations– Quick Tour of the PlanAhead Design and Analysis Tool– I/O pin planning with PinAhead Technology– Improve Design Performance with the PlanAhead Design and Analysis tool

Where Can I Learn More?

Xilinx Education Services courses– www.xilinx.com/training

• Xilinx tools and architecture courses• Hardware description language courses• Basic FPGA architecture, Basic HDL Coding Techniques, and other free

Videos!• How to make Area Constraints with PlanAhead tool Video!

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