winter-spring 2001codesign of embedded systems1 introduction to hw/sw codesign part of hw/sw...
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Winter-Spring 2001 Codesign of Embedded Syste
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Introduction to HW/SW Codesign
Part ofHW/SW Codesign of
Embedded Systems Course (CE 40-226)
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Today programme Introduction to HW/SW Codesign
Distinguishing features of electronic systems
System-level codesign issues
Reference:
G. De Micheli, M. Sami, “Hardware/Software Co-design”, NATO ASI Series, Kluwer Academic Publishers, 1996.
Reference:
G. De Micheli, M. Sami, “Hardware/Software Co-design”, NATO ASI Series, Kluwer Academic Publishers, 1996.
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Introduction to HW/SW Codesign
Distinguishing features of electronic systems
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Distinguishing features of electronic systems
ApplicationDomain
Degree ofProgrammability
Level ofIntegration
HardwareTechnology
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Application domains General-purpose computing
systems Dedicated computing and control
systems Emulation and prototyping
systems
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Application domains (cont’d) GP computing systems
Traditional computers End-user can program them Support applications of different kinds
Dedicated computing and/or control systems Specific target applications Limited programming access for the user Dedicated software programs Known as Embedded Systems
“Control functions” or “Data comm. and processing” or both
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Application domains (cont’d) Emulation and prototyping systems
Programmable HW technology Hardware configuration by HW compilers
(synthesis systems) Specialized users program them Intermediate points of the design and
manufacturing of a product
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Degree of programmability Programmability at the
Application level Instruction level Hardware level
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Degree of programmability (cont’d) Application level
Most restricted level User have to use specialized language
VCR - Automated navigation systems
Instruction level Personal computer users Writing, compiling and executing programs Processor architecture defines degree of
programmability
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Degree of programmability (cont’d) Hardware level
Configuring HW after manufacturing Micro-programming: emulation of
other ISAs Common for DSPs, not for ISPs (esp. RISC)
FPGAs
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Degree of programmability (cont’d) Programmability
Increases applicability, but not performance Top performance in
GP computing: super-scalar RISC architectures Dedicated applications: ASICs
Some app. domains (ex. Comm.) ASIPs: specialized instruction-level
programmable processors Midway between ASIC and ISP: Performance, Power,
Production volume
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Technology Digital-system components have
Different scale of integration Discrete and integrated components
Different fabrication technology Bipolar, CMOS
To us, technology affects field-programmability Storing programs in memory Configurable HW
One-time configurable Re-configurable
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Level of Integration Digital systems are
Lumped => System-on-Chip Distributed
Advantages of higher integration Higher reliability Lower power budget Increased performance
Disadvantages Larger chip sizes. More complex
debugging
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Introduction to HW/SW Codesign
System-level Co-Design Issues
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General-purposecomputing systems ISP: Primarily in general-purpose computing
Codesign of ISP is strange Architectural support for OS Compiler development: Retargetable,
Optimizing Codesign areas:
organizational choices: pipelines, concurrency, memory hierarchy
Instruction-set selection Performance Compatibility
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Dedicated computing and control systems Data-processing systems
GP DSP / ASIP ASIP
Less compatibility, more performance Need for application-specific compilers
Retargetable compilers Computer-Aided compiler generation
fixed-point arithmetic operations Hence, use assembly Today design time: SW > HW
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Dedicated computing … (cont’d) Embedded control systems
Sen
sors
Memory CPU
Act
uato
rs
Hardwired UnitRandom Logic
TimersA/D D/A
Embedded System
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Dedicated computing … (cont’d) Control systems
Often have a data-processing component Reactive systems
RT: hard/soft Timers
Safety and reliability more important than performance
Safety: Formal verification+ System-level testing Reliability: Redundancy
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Emulation and prototyping systems Codesign application 1:
SW accelerators/coprocessors Specific operations: floating-point ops. Critical loops: exploiting local parallelism
for(j=0; j<N; j++) a[j] = a[j] + b[j]; for(j=1; j<N; j++) a[j] = a[j] + a[j-1];
Coprocessors based on programmable HW
Example: PAM (PeRLe-0, PeRLe-1)
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Emulation and prototyping systems (cont’d)
Major codesign problems: Identifying critical parts of SW Compile critical SW parts for HW
emulation
Codesign application 2: Acceleration of system-level
simulation by HW emulation
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Emulation and prototyping systems (cont’d) Codesign application 3:
Computer-aided prototyping Validate HW before manufacturing to
avoid expensive redesign Prototyping of complex digital systems
(HW + SW)
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What we learned today Categorized digital systems
This helps in decision-makings in codesign strategies and algorithms
Reviewed problem areas within each application domain
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Complementary notes Verilog Short Course
Instructor: Farshid Soheili, Emad Semicon. Co.
First session Saturday: Esfand 6th
“Avecina-16” room
VHDL short course will also be held soon
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Complementary notes (cont’d) Optional paper presentation
Any subtopic from second topic of today programme:
System-Level Co-Design Issues